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path: root/drivers/gpu/nvgpu/common/fifo/tsg.c
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Diffstat (limited to 'drivers/gpu/nvgpu/common/fifo/tsg.c')
-rw-r--r--drivers/gpu/nvgpu/common/fifo/tsg.c33
1 files changed, 24 insertions, 9 deletions
diff --git a/drivers/gpu/nvgpu/common/fifo/tsg.c b/drivers/gpu/nvgpu/common/fifo/tsg.c
index 5883667f..7f61b273 100644
--- a/drivers/gpu/nvgpu/common/fifo/tsg.c
+++ b/drivers/gpu/nvgpu/common/fifo/tsg.c
@@ -452,13 +452,15 @@ int nvgpu_tsg_set_mmu_debug_mode(struct tsg_gk20a *tsg,
452 struct gk20a *g; 452 struct gk20a *g;
453 int err = 0; 453 int err = 0;
454 u32 tsg_refcnt; 454 u32 tsg_refcnt;
455 u32 fb_refcnt;
455 456
456 if ((ch == NULL) || (tsg == NULL)) { 457 if ((ch == NULL) || (tsg == NULL)) {
457 return -EINVAL; 458 return -EINVAL;
458 } 459 }
459 g = ch->g; 460 g = ch->g;
460 461
461 if (g->ops.gr.set_mmu_debug_mode == NULL) { 462 if ((g->ops.fb.set_mmu_debug_mode == NULL) &&
463 (g->ops.gr.set_mmu_debug_mode == NULL)) {
462 return -ENOSYS; 464 return -ENOSYS;
463 } 465 }
464 466
@@ -468,26 +470,39 @@ int nvgpu_tsg_set_mmu_debug_mode(struct tsg_gk20a *tsg,
468 return 0; 470 return 0;
469 } 471 }
470 tsg_refcnt = tsg->mmu_debug_mode_refcnt + 1U; 472 tsg_refcnt = tsg->mmu_debug_mode_refcnt + 1U;
473 fb_refcnt = g->mmu_debug_mode_refcnt + 1U;
471 } else { 474 } else {
472 if (!ch->mmu_debug_mode_enabled) { 475 if (!ch->mmu_debug_mode_enabled) {
473 /* already disabled for this channel */ 476 /* already disabled for this channel */
474 return 0; 477 return 0;
475 } 478 }
476 tsg_refcnt = tsg->mmu_debug_mode_refcnt - 1U; 479 tsg_refcnt = tsg->mmu_debug_mode_refcnt - 1U;
480 fb_refcnt = g->mmu_debug_mode_refcnt - 1U;
477 } 481 }
478 482
479 /* 483 if (g->ops.gr.set_mmu_debug_mode != NULL) {
480 * enable GPC MMU debug mode if it was requested for at 484 /*
481 * least one channel in the TSG 485 * enable GPC MMU debug mode if it was requested for at
482 */ 486 * least one channel in the TSG
483 err = g->ops.gr.set_mmu_debug_mode(g, ch, tsg_refcnt > 0U); 487 */
484 if (err != 0) { 488 err = g->ops.gr.set_mmu_debug_mode(g, ch, tsg_refcnt > 0U);
485 nvgpu_err(g, "set mmu debug mode failed, err=%d", err); 489 if (err != 0) {
486 return err; 490 nvgpu_err(g, "set mmu debug mode failed, err=%d", err);
491 return err;
492 }
493 }
494
495 if (g->ops.fb.set_mmu_debug_mode != NULL) {
496 /*
497 * enable FB/HS MMU debug mode if it was requested for
498 * at least one TSG
499 */
500 g->ops.fb.set_mmu_debug_mode(g, fb_refcnt > 0U);
487 } 501 }
488 502
489 ch->mmu_debug_mode_enabled = enable; 503 ch->mmu_debug_mode_enabled = enable;
490 tsg->mmu_debug_mode_refcnt = tsg_refcnt; 504 tsg->mmu_debug_mode_refcnt = tsg_refcnt;
505 g->mmu_debug_mode_refcnt = fb_refcnt;
491 506
492 return err; 507 return err;
493} 508}