diff options
Diffstat (limited to 'drivers/gpu/nvgpu/common/fifo/tsg.c')
-rw-r--r-- | drivers/gpu/nvgpu/common/fifo/tsg.c | 48 |
1 files changed, 47 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/common/fifo/tsg.c b/drivers/gpu/nvgpu/common/fifo/tsg.c index 6d6c322e..5883667f 100644 --- a/drivers/gpu/nvgpu/common/fifo/tsg.c +++ b/drivers/gpu/nvgpu/common/fifo/tsg.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -445,3 +445,49 @@ void gk20a_tsg_update_sm_error_state_locked(struct tsg_gk20a *tsg, | |||
445 | tsg_sm_error_states->hww_warp_esr_report_mask = | 445 | tsg_sm_error_states->hww_warp_esr_report_mask = |
446 | sm_error_state->hww_warp_esr_report_mask; | 446 | sm_error_state->hww_warp_esr_report_mask; |
447 | } | 447 | } |
448 | |||
449 | int nvgpu_tsg_set_mmu_debug_mode(struct tsg_gk20a *tsg, | ||
450 | struct channel_gk20a *ch, bool enable) | ||
451 | { | ||
452 | struct gk20a *g; | ||
453 | int err = 0; | ||
454 | u32 tsg_refcnt; | ||
455 | |||
456 | if ((ch == NULL) || (tsg == NULL)) { | ||
457 | return -EINVAL; | ||
458 | } | ||
459 | g = ch->g; | ||
460 | |||
461 | if (g->ops.gr.set_mmu_debug_mode == NULL) { | ||
462 | return -ENOSYS; | ||
463 | } | ||
464 | |||
465 | if (enable) { | ||
466 | if (ch->mmu_debug_mode_enabled) { | ||
467 | /* already enabled for this channel */ | ||
468 | return 0; | ||
469 | } | ||
470 | tsg_refcnt = tsg->mmu_debug_mode_refcnt + 1U; | ||
471 | } else { | ||
472 | if (!ch->mmu_debug_mode_enabled) { | ||
473 | /* already disabled for this channel */ | ||
474 | return 0; | ||
475 | } | ||
476 | tsg_refcnt = tsg->mmu_debug_mode_refcnt - 1U; | ||
477 | } | ||
478 | |||
479 | /* | ||
480 | * enable GPC MMU debug mode if it was requested for at | ||
481 | * least one channel in the TSG | ||
482 | */ | ||
483 | err = g->ops.gr.set_mmu_debug_mode(g, ch, tsg_refcnt > 0U); | ||
484 | if (err != 0) { | ||
485 | nvgpu_err(g, "set mmu debug mode failed, err=%d", err); | ||
486 | return err; | ||
487 | } | ||
488 | |||
489 | ch->mmu_debug_mode_enabled = enable; | ||
490 | tsg->mmu_debug_mode_refcnt = tsg_refcnt; | ||
491 | |||
492 | return err; | ||
493 | } | ||