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path: root/drivers/gpu/nvgpu/common/fb/fb_gv11b.c
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Diffstat (limited to 'drivers/gpu/nvgpu/common/fb/fb_gv11b.c')
-rw-r--r--drivers/gpu/nvgpu/common/fb/fb_gv11b.c16
1 files changed, 10 insertions, 6 deletions
diff --git a/drivers/gpu/nvgpu/common/fb/fb_gv11b.c b/drivers/gpu/nvgpu/common/fb/fb_gv11b.c
index 30bf17f8..b98d1c41 100644
--- a/drivers/gpu/nvgpu/common/fb/fb_gv11b.c
+++ b/drivers/gpu/nvgpu/common/fb/fb_gv11b.c
@@ -839,6 +839,7 @@ static void gv11b_fb_handle_mmu_fault_common(struct gk20a *g,
839 int err = 0; 839 int err = 0;
840 u32 id = FIFO_INVAL_TSG_ID; 840 u32 id = FIFO_INVAL_TSG_ID;
841 unsigned int rc_type = RC_TYPE_NO_RC; 841 unsigned int rc_type = RC_TYPE_NO_RC;
842 struct tsg_gk20a *tsg = NULL;
842 843
843 if (!mmfault->valid) { 844 if (!mmfault->valid) {
844 return; 845 return;
@@ -912,14 +913,17 @@ static void gv11b_fb_handle_mmu_fault_common(struct gk20a *g,
912 mmfault->refch->mmu_nack_handled = true; 913 mmfault->refch->mmu_nack_handled = true;
913 } 914 }
914 915
915 rc_type = RC_TYPE_MMU_FAULT; 916 tsg = tsg_gk20a_from_ch(mmfault->refch);
916 if (gk20a_is_channel_marked_as_tsg(mmfault->refch)) { 917 if (tsg != NULL) {
917 id = mmfault->refch->tsgid; 918 id = mmfault->refch->tsgid;
918 if (id != FIFO_INVAL_TSG_ID) { 919 id_type = ID_TYPE_TSG;
919 id_type = ID_TYPE_TSG; 920 rc_type = RC_TYPE_MMU_FAULT;
920 }
921 } else { 921 } else {
922 nvgpu_err(g, "bare channels not supported"); 922 nvgpu_err(g, "chid: %d is referenceable but "
923 "not bound to tsg",
924 mmfault->refch->chid);
925 id_type = ID_TYPE_CHANNEL;
926 rc_type = RC_TYPE_NO_RC;
923 } 927 }
924 } 928 }
925 929