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path: root/drivers/gpu/nvgpu/common/fb/fb_gv100.c
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Diffstat (limited to 'drivers/gpu/nvgpu/common/fb/fb_gv100.c')
-rw-r--r--drivers/gpu/nvgpu/common/fb/fb_gv100.c26
1 files changed, 25 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/common/fb/fb_gv100.c b/drivers/gpu/nvgpu/common/fb/fb_gv100.c
index 193cf2f0..508259e7 100644
--- a/drivers/gpu/nvgpu/common/fb/fb_gv100.c
+++ b/drivers/gpu/nvgpu/common/fb/fb_gv100.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * GV100 FB 2 * GV100 FB
3 * 3 *
4 * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a 6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"), 7 * copy of this software and associated documentation files (the "Software"),
@@ -300,3 +300,27 @@ size_t gv100_fb_get_vidmem_size(struct gk20a *g)
300 300
301 return bytes; 301 return bytes;
302} 302}
303
304void gv100_fb_set_mmu_debug_mode(struct gk20a *g, bool enable)
305{
306 u32 data, fb_ctrl, hsmmu_ctrl;
307
308 if (enable) {
309 fb_ctrl = fb_mmu_debug_ctrl_debug_enabled_f();
310 hsmmu_ctrl = fb_hsmmu_pri_mmu_debug_ctrl_debug_enabled_f();
311 g->mmu_debug_ctrl = true;
312 } else {
313 fb_ctrl = fb_mmu_debug_ctrl_debug_disabled_f();
314 hsmmu_ctrl = fb_hsmmu_pri_mmu_debug_ctrl_debug_disabled_f();
315 g->mmu_debug_ctrl = false;
316 }
317
318 data = nvgpu_readl(g, fb_mmu_debug_ctrl_r());
319 data = set_field(data, fb_mmu_debug_ctrl_debug_m(), fb_ctrl);
320 nvgpu_writel(g, fb_mmu_debug_ctrl_r(), data);
321
322 data = nvgpu_readl(g, fb_hsmmu_pri_mmu_debug_ctrl_r());
323 data = set_field(data,
324 fb_hsmmu_pri_mmu_debug_ctrl_debug_m(), hsmmu_ctrl);
325 nvgpu_writel(g, fb_hsmmu_pri_mmu_debug_ctrl_r(), data);
326}