1 files changed, 9 insertions, 4 deletions

diff --git a/drivers/gpu/nvgpu/common/fb/fb_gm20b.c b/drivers/gpu/nvgpu/common/fb/fb_gm20b.c
index f62bf9df..739274c5 100644
--- a/drivers/gpu/nvgpu/common/fb/fb_gm20b.c
+++ b/drivers/gpu/nvgpu/common/fb/fb_gm20b.c
@@ -1,7 +1,7 @@
 /*
  * GM20B GPC MMU
  *
- * Copyright (c) 2014-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2020, NVIDIA CORPORATION.  All rights reserved.
 *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -311,7 +311,7 @@ bool gm20b_fb_debug_mode_enabled(struct gk20a *g)
                         fb_mmu_debug_ctrl_debug_enabled_v();
 }
 
-void gm20b_fb_set_debug_mode(struct gk20a *g, bool enable)
+void gm20b_fb_set_mmu_debug_mode(struct gk20a *g, bool enable)
 {
         u32 reg_val, fb_debug_ctrl;
 
@@ -323,10 +323,15 @@ void gm20b_fb_set_debug_mode(struct gk20a *g, bool enable)
                 g->mmu_debug_ctrl = false;
         }
 
-        reg_val = gk20a_readl(g, fb_mmu_debug_ctrl_r());
+        reg_val = nvgpu_readl(g, fb_mmu_debug_ctrl_r());
         reg_val = set_field(reg_val,
                         fb_mmu_debug_ctrl_debug_m(), fb_debug_ctrl);
-        gk20a_writel(g, fb_mmu_debug_ctrl_r(), reg_val);
+        nvgpu_writel(g, fb_mmu_debug_ctrl_r(), reg_val);
+}
 
+void gm20b_fb_set_debug_mode(struct gk20a *g, bool enable)
+{
+        gm20b_fb_set_mmu_debug_mode(g, enable);
         g->ops.gr.set_debug_mode(g, enable);
 }
+