diff options
Diffstat (limited to 'drivers/gpu/nvgpu/common/falcon/falcon.c')
-rw-r--r-- | drivers/gpu/nvgpu/common/falcon/falcon.c | 40 |
1 files changed, 37 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/common/falcon/falcon.c b/drivers/gpu/nvgpu/common/falcon/falcon.c index d8420ece..42b33c27 100644 --- a/drivers/gpu/nvgpu/common/falcon/falcon.c +++ b/drivers/gpu/nvgpu/common/falcon/falcon.c | |||
@@ -25,6 +25,13 @@ | |||
25 | 25 | ||
26 | #include "gk20a/gk20a.h" | 26 | #include "gk20a/gk20a.h" |
27 | 27 | ||
28 | /* Dealy depends on memory size and pwr_clk | ||
29 | * delay = MAX {IMEM_SIZE, DMEM_SIZE} * 64 + 1) / pwr_clk | ||
30 | * Timeout set is 1msec & status check at interval 10usec | ||
31 | */ | ||
32 | #define MEM_SCRUBBING_TIMEOUT_MAX 1000 | ||
33 | #define MEM_SCRUBBING_TIMEOUT_DEFAULT 10 | ||
34 | |||
28 | int nvgpu_flcn_wait_idle(struct nvgpu_falcon *flcn) | 35 | int nvgpu_flcn_wait_idle(struct nvgpu_falcon *flcn) |
29 | { | 36 | { |
30 | struct gk20a *g = flcn->g; | 37 | struct gk20a *g = flcn->g; |
@@ -56,15 +63,42 @@ int nvgpu_flcn_wait_idle(struct nvgpu_falcon *flcn) | |||
56 | return 0; | 63 | return 0; |
57 | } | 64 | } |
58 | 65 | ||
66 | int nvgpu_flcn_mem_scrub_wait(struct nvgpu_falcon *flcn) | ||
67 | { | ||
68 | struct nvgpu_timeout timeout; | ||
69 | int status = 0; | ||
70 | |||
71 | /* check IMEM/DMEM scrubbing complete status */ | ||
72 | nvgpu_timeout_init(flcn->g, &timeout, | ||
73 | MEM_SCRUBBING_TIMEOUT_MAX / | ||
74 | MEM_SCRUBBING_TIMEOUT_DEFAULT, | ||
75 | NVGPU_TIMER_RETRY_TIMER); | ||
76 | do { | ||
77 | if (nvgpu_flcn_get_mem_scrubbing_status(flcn)) | ||
78 | goto exit; | ||
79 | nvgpu_udelay(MEM_SCRUBBING_TIMEOUT_DEFAULT); | ||
80 | } while (!nvgpu_timeout_expired(&timeout)); | ||
81 | |||
82 | if (nvgpu_timeout_peek_expired(&timeout)) | ||
83 | status = -ETIMEDOUT; | ||
84 | |||
85 | exit: | ||
86 | return status; | ||
87 | } | ||
88 | |||
59 | int nvgpu_flcn_reset(struct nvgpu_falcon *flcn) | 89 | int nvgpu_flcn_reset(struct nvgpu_falcon *flcn) |
60 | { | 90 | { |
61 | int status = -EINVAL; | 91 | int status = 0; |
62 | 92 | ||
63 | if (flcn->flcn_ops.reset) | 93 | if (flcn->flcn_ops.reset) { |
64 | status = flcn->flcn_ops.reset(flcn); | 94 | status = flcn->flcn_ops.reset(flcn); |
65 | else | 95 | if (!status) |
96 | status = nvgpu_flcn_mem_scrub_wait(flcn); | ||
97 | } else { | ||
66 | nvgpu_warn(flcn->g, "Invalid op on falcon 0x%x ", | 98 | nvgpu_warn(flcn->g, "Invalid op on falcon 0x%x ", |
67 | flcn->flcn_id); | 99 | flcn->flcn_id); |
100 | status = -EINVAL; | ||
101 | } | ||
68 | 102 | ||
69 | return status; | 103 | return status; |
70 | } | 104 | } |