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path: root/drivers/gpu/nvgpu/common/clock_gating/gv11b_gating_reglist.c
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Diffstat (limited to 'drivers/gpu/nvgpu/common/clock_gating/gv11b_gating_reglist.c')
-rw-r--r--drivers/gpu/nvgpu/common/clock_gating/gv11b_gating_reglist.c821
1 files changed, 375 insertions, 446 deletions
diff --git a/drivers/gpu/nvgpu/common/clock_gating/gv11b_gating_reglist.c b/drivers/gpu/nvgpu/common/clock_gating/gv11b_gating_reglist.c
index 998783e4..418f2c12 100644
--- a/drivers/gpu/nvgpu/common/clock_gating/gv11b_gating_reglist.c
+++ b/drivers/gpu/nvgpu/common/clock_gating/gv11b_gating_reglist.c
@@ -22,164 +22,163 @@
22 * This file is autogenerated. Do not edit. 22 * This file is autogenerated. Do not edit.
23 */ 23 */
24 24
25#ifndef __gv11b_gating_reglist_h__
26#define __gv11b_gating_reglist_h__
27
28#include <nvgpu/types.h> 25#include <nvgpu/types.h>
29#include "gv11b_gating_reglist.h" 26#include <nvgpu/io.h>
30#include <nvgpu/enabled.h> 27#include <nvgpu/enabled.h>
31 28
32struct gating_desc { 29#include "gating_reglist.h"
33 u32 addr; 30#include "gv11b_gating_reglist.h"
34 u32 prod; 31
35 u32 disable; 32#define GATING_DESC_SIZE (u32)(sizeof(struct gating_desc))
36}; 33
37/* slcg bus */ 34/* slcg bus */
38static const struct gating_desc gv11b_slcg_bus[] = { 35static const struct gating_desc gv11b_slcg_bus[] = {
39 {.addr = 0x00001c04, .prod = 0x00000000, .disable = 0x000003fe}, 36 {.addr = 0x00001c04U, .prod = 0x00000000U, .disable = 0x000003feU},
40}; 37};
41 38
42/* slcg ce2 */ 39/* slcg ce2 */
43static const struct gating_desc gv11b_slcg_ce2[] = { 40static const struct gating_desc gv11b_slcg_ce2[] = {
44 {.addr = 0x00104204, .prod = 0x00000040, .disable = 0x000007fe}, 41 {.addr = 0x00104204U, .prod = 0x00000040U, .disable = 0x000007feU},
45}; 42};
46 43
47/* slcg chiplet */ 44/* slcg chiplet */
48static const struct gating_desc gv11b_slcg_chiplet[] = { 45static const struct gating_desc gv11b_slcg_chiplet[] = {
49 {.addr = 0x0010c07c, .prod = 0x00000000, .disable = 0x00000007}, 46 {.addr = 0x0010c07cU, .prod = 0x00000000U, .disable = 0x00000007U},
50 {.addr = 0x0010e07c, .prod = 0x00000000, .disable = 0x00000007}, 47 {.addr = 0x0010e07cU, .prod = 0x00000000U, .disable = 0x00000007U},
51 {.addr = 0x0010d07c, .prod = 0x00000000, .disable = 0x00000007}, 48 {.addr = 0x0010d07cU, .prod = 0x00000000U, .disable = 0x00000007U},
52 {.addr = 0x0010e17c, .prod = 0x00000000, .disable = 0x00000007}, 49 {.addr = 0x0010e17cU, .prod = 0x00000000U, .disable = 0x00000007U},
53}; 50};
54 51
55/* slcg fb */ 52/* slcg fb */
56static const struct gating_desc gv11b_slcg_fb[] = { 53static const struct gating_desc gv11b_slcg_fb[] = {
57 {.addr = 0x00100d14, .prod = 0x00000000, .disable = 0xfffffffe}, 54 {.addr = 0x00100d14U, .prod = 0x00000000U, .disable = 0xfffffffeU},
58 {.addr = 0x00100c9c, .prod = 0x00000000, .disable = 0x000001fe}, 55 {.addr = 0x00100c9cU, .prod = 0x00000000U, .disable = 0x000001feU},
59}; 56};
60 57
61/* slcg fifo */ 58/* slcg fifo */
62static const struct gating_desc gv11b_slcg_fifo[] = { 59static const struct gating_desc gv11b_slcg_fifo[] = {
63 {.addr = 0x000026ec, .prod = 0x00000000, .disable = 0x0001fffe}, 60 {.addr = 0x000026ecU, .prod = 0x00000000U, .disable = 0x0001fffeU},
64}; 61};
65 62
66/* slcg gr */ 63/* slcg gr */
67static const struct gating_desc gv11b_slcg_gr[] = { 64static const struct gating_desc gv11b_slcg_gr[] = {
68 {.addr = 0x004041f4, .prod = 0x00000000, .disable = 0x07fffffe}, 65 {.addr = 0x004041f4U, .prod = 0x00000000U, .disable = 0x07fffffeU},
69 {.addr = 0x00409134, .prod = 0x00020008, .disable = 0x0003fffe}, 66 {.addr = 0x00409134U, .prod = 0x00020008U, .disable = 0x0003fffeU},
70 {.addr = 0x00409894, .prod = 0x00000000, .disable = 0x0000fffe}, 67 {.addr = 0x00409894U, .prod = 0x00000000U, .disable = 0x0000fffeU},
71 {.addr = 0x004078c4, .prod = 0x00000000, .disable = 0x000001fe}, 68 {.addr = 0x004078c4U, .prod = 0x00000000U, .disable = 0x000001feU},
72 {.addr = 0x00406004, .prod = 0x00000200, .disable = 0x0001fffe}, 69 {.addr = 0x00406004U, .prod = 0x00000200U, .disable = 0x0001fffeU},
73 {.addr = 0x00405864, .prod = 0x00000000, .disable = 0x000001fe}, 70 {.addr = 0x00405864U, .prod = 0x00000000U, .disable = 0x000001feU},
74 {.addr = 0x00405910, .prod = 0xfffffff0, .disable = 0xfffffffe}, 71 {.addr = 0x00405910U, .prod = 0xfffffff0U, .disable = 0xfffffffeU},
75 {.addr = 0x00408044, .prod = 0x00000000, .disable = 0x000007fe}, 72 {.addr = 0x00408044U, .prod = 0x00000000U, .disable = 0x000007feU},
73 /* fix priv error */
74 /*{.addr = 0x00407004U, .prod = 0x00000000U, .disable = 0x000001feU},*/
75 /*{.addr = 0x00405bf4U, .prod = 0x00000000U, .disable = 0x00000002U},*/
76 {.addr = 0x0041a134U, .prod = 0x00020008U, .disable = 0x0003fffeU},
77 {.addr = 0x0041a894U, .prod = 0x00000000U, .disable = 0x0000fffeU},
78 {.addr = 0x00418504U, .prod = 0x00000000U, .disable = 0x0007fffeU},
76 /* fix priv error */ 79 /* fix priv error */
77 /*{.addr = 0x00407004, .prod = 0x00000000, .disable = 0x000001fe},*/ 80 /*{.addr = 0x0041860cU, .prod = 0x00000000U, .disable = 0x000001feU},*/
78 /*{.addr = 0x00405bf4, .prod = 0x00000000, .disable = 0x00000002},*/ 81 {.addr = 0x0041868cU, .prod = 0x00000000U, .disable = 0x0000001eU},
79 {.addr = 0x0041a134, .prod = 0x00020008, .disable = 0x0003fffe}, 82 {.addr = 0x0041871cU, .prod = 0x00000000U, .disable = 0x000003feU},
80 {.addr = 0x0041a894, .prod = 0x00000000, .disable = 0x0000fffe}, 83 {.addr = 0x00418388U, .prod = 0x00000000U, .disable = 0x00000001U},
81 {.addr = 0x00418504, .prod = 0x00000000, .disable = 0x0007fffe}, 84 {.addr = 0x0041882cU, .prod = 0x00000000U, .disable = 0x0001fffeU},
85 {.addr = 0x00418bc0U, .prod = 0x00000000U, .disable = 0x000001feU},
86 {.addr = 0x00418974U, .prod = 0x00000000U, .disable = 0x0001fffeU},
82 /* fix priv error */ 87 /* fix priv error */
83 /*{.addr = 0x0041860c, .prod = 0x00000000, .disable = 0x000001fe},*/ 88 /*{.addr = 0x00418c74U, .prod = 0xffffff80U, .disable = 0xfffffffeU},*/
84 {.addr = 0x0041868c, .prod = 0x00000000, .disable = 0x0000001e}, 89 {.addr = 0x00418cf4U, .prod = 0xfffffff8U, .disable = 0xfffffffeU},
85 {.addr = 0x0041871c, .prod = 0x00000000, .disable = 0x000003fe}, 90 {.addr = 0x00418d74U, .prod = 0xffffffe0U, .disable = 0xfffffffeU},
86 {.addr = 0x00418388, .prod = 0x00000000, .disable = 0x00000001}, 91 {.addr = 0x00418f10U, .prod = 0xffffffe0U, .disable = 0xfffffffeU},
87 {.addr = 0x0041882c, .prod = 0x00000000, .disable = 0x0001fffe}, 92 {.addr = 0x00418e10U, .prod = 0xfffffffeU, .disable = 0xfffffffeU},
88 {.addr = 0x00418bc0, .prod = 0x00000000, .disable = 0x000001fe}, 93 {.addr = 0x00419024U, .prod = 0x000001feU, .disable = 0x000001feU},
89 {.addr = 0x00418974, .prod = 0x00000000, .disable = 0x0001fffe}, 94 {.addr = 0x0041889cU, .prod = 0x00000000U, .disable = 0x000001feU},
95 {.addr = 0x00419d24U, .prod = 0x00000000U, .disable = 0x000000ffU},
96 {.addr = 0x0041986cU, .prod = 0x00000104U, .disable = 0x00fffffeU},
97 {.addr = 0x00419c74U, .prod = 0x0000001eU, .disable = 0x0000001eU},
90 /* fix priv error */ 98 /* fix priv error */
91 /*{.addr = 0x00418c74, .prod = 0xffffff80, .disable = 0xfffffffe},*/ 99 /*{.addr = 0x00419c84U, .prod = 0x0003fff8U, .disable = 0x0003fffeU},*/
92 {.addr = 0x00418cf4, .prod = 0xfffffff8, .disable = 0xfffffffe}, 100 {.addr = 0x00419c8cU, .prod = 0xffffff84U, .disable = 0xfffffffeU},
93 {.addr = 0x00418d74, .prod = 0xffffffe0, .disable = 0xfffffffe}, 101 {.addr = 0x00419c94U, .prod = 0x00080040U, .disable = 0x000ffffeU},
94 {.addr = 0x00418f10, .prod = 0xffffffe0, .disable = 0xfffffffe}, 102 {.addr = 0x00419ca4U, .prod = 0x00003ffeU, .disable = 0x00003ffeU},
95 {.addr = 0x00418e10, .prod = 0xfffffffe, .disable = 0xfffffffe}, 103 {.addr = 0x00419cacU, .prod = 0x0001fffeU, .disable = 0x0001fffeU},
96 {.addr = 0x00419024, .prod = 0x000001fe, .disable = 0x000001fe}, 104 {.addr = 0x00419a44U, .prod = 0x00000008U, .disable = 0x0000000eU},
97 {.addr = 0x0041889c, .prod = 0x00000000, .disable = 0x000001fe}, 105 {.addr = 0x00419a4cU, .prod = 0x000001f8U, .disable = 0x000001feU},
98 {.addr = 0x00419d24, .prod = 0x00000000, .disable = 0x000000ff}, 106 {.addr = 0x00419a54U, .prod = 0x0000003cU, .disable = 0x0000003eU},
99 {.addr = 0x0041986c, .prod = 0x00000104, .disable = 0x00fffffe}, 107 {.addr = 0x00419a5cU, .prod = 0x0000000cU, .disable = 0x0000000eU},
100 {.addr = 0x00419c74, .prod = 0x0000001e, .disable = 0x0000001e}, 108 {.addr = 0x00419a64U, .prod = 0x000001baU, .disable = 0x000001feU},
101 {.addr = 0x00419c8c, .prod = 0xffffff84, .disable = 0xfffffffe}, 109 {.addr = 0x00419a7cU, .prod = 0x0000003cU, .disable = 0x0000003eU},
102 {.addr = 0x00419c94, .prod = 0x00080040, .disable = 0x000ffffe}, 110 {.addr = 0x00419a84U, .prod = 0x0000000cU, .disable = 0x0000000eU},
103 {.addr = 0x00419ca4, .prod = 0x00003ffe, .disable = 0x00003ffe}, 111 {.addr = 0x0041be2cU, .prod = 0x04115fc0U, .disable = 0xfffffffeU},
104 {.addr = 0x00419cac, .prod = 0x0001fffe, .disable = 0x0001fffe}, 112 {.addr = 0x0041bfecU, .prod = 0xfffffff0U, .disable = 0xfffffffeU},
105 {.addr = 0x00419a44, .prod = 0x00000008, .disable = 0x0000000e},
106 {.addr = 0x00419a4c, .prod = 0x000001f8, .disable = 0x000001fe},
107 {.addr = 0x00419a54, .prod = 0x0000003c, .disable = 0x0000003e},
108 {.addr = 0x00419a5c, .prod = 0x0000000c, .disable = 0x0000000e},
109 {.addr = 0x00419a64, .prod = 0x000001ba, .disable = 0x000001fe},
110 {.addr = 0x00419a7c, .prod = 0x0000003c, .disable = 0x0000003e},
111 {.addr = 0x00419a84, .prod = 0x0000000c, .disable = 0x0000000e},
112 {.addr = 0x0041be2c, .prod = 0x04115fc0, .disable = 0xfffffffe},
113 {.addr = 0x0041bfec, .prod = 0xfffffff0, .disable = 0xfffffffe},
114 /* fix priv error */ 113 /* fix priv error */
115 /*{.addr = 0x0041bed4, .prod = 0xfffffff8, .disable = 0xfffffffe},*/ 114 /*{.addr = 0x0041bed4U, .prod = 0xfffffff8U, .disable = 0xfffffffeU},*/
116 {.addr = 0x00408814, .prod = 0x00000000, .disable = 0x0001fffe}, 115 {.addr = 0x00408814U, .prod = 0x00000000U, .disable = 0x0001fffeU},
117 {.addr = 0x00408a84, .prod = 0x00000000, .disable = 0x0001fffe}, 116 {.addr = 0x00408a84U, .prod = 0x00000000U, .disable = 0x0001fffeU},
118 {.addr = 0x004089ac, .prod = 0x00000000, .disable = 0x0001fffe}, 117 {.addr = 0x004089acU, .prod = 0x00000000U, .disable = 0x0001fffeU},
119 {.addr = 0x00408a24, .prod = 0x00000000, .disable = 0x000000ff}, 118 {.addr = 0x00408a24U, .prod = 0x00000000U, .disable = 0x000000ffU},
120}; 119};
121 120
122/* slcg ltc */ 121/* slcg ltc */
123static const struct gating_desc gv11b_slcg_ltc[] = { 122static const struct gating_desc gv11b_slcg_ltc[] = {
124 {.addr = 0x0017e050, .prod = 0x00000000, .disable = 0xfffffffe}, 123 {.addr = 0x0017e050U, .prod = 0x00000000U, .disable = 0xfffffffeU},
125 {.addr = 0x0017e35c, .prod = 0x00000000, .disable = 0xfffffffe}, 124 {.addr = 0x0017e35cU, .prod = 0x00000000U, .disable = 0xfffffffeU},
126}; 125};
127 126
128/* slcg perf */ 127/* slcg perf */
129static const struct gating_desc gv11b_slcg_perf[] = { 128static const struct gating_desc gv11b_slcg_perf[] = {
130 {.addr = 0x00248018, .prod = 0xffffffff, .disable = 0x00000000}, 129 {.addr = 0x00248018U, .prod = 0xffffffffU, .disable = 0x00000000U},
131 {.addr = 0x00248018, .prod = 0xffffffff, .disable = 0x00000000}, 130 {.addr = 0x00248018U, .prod = 0xffffffffU, .disable = 0x00000000U},
132 {.addr = 0x00246018, .prod = 0xffffffff, .disable = 0x00000000}, 131 {.addr = 0x00246018U, .prod = 0xffffffffU, .disable = 0x00000000U},
133 {.addr = 0x00246018, .prod = 0xffffffff, .disable = 0x00000000}, 132 {.addr = 0x00246018U, .prod = 0xffffffffU, .disable = 0x00000000U},
134 {.addr = 0x00246018, .prod = 0xffffffff, .disable = 0x00000000}, 133 {.addr = 0x00246018U, .prod = 0xffffffffU, .disable = 0x00000000U},
135 {.addr = 0x00244018, .prod = 0xffffffff, .disable = 0x00000000}, 134 {.addr = 0x00244018U, .prod = 0xffffffffU, .disable = 0x00000000U},
136 {.addr = 0x00244018, .prod = 0xffffffff, .disable = 0x00000000}, 135 {.addr = 0x00244018U, .prod = 0xffffffffU, .disable = 0x00000000U},
137 {.addr = 0x00244018, .prod = 0xffffffff, .disable = 0x00000000}, 136 {.addr = 0x00244018U, .prod = 0xffffffffU, .disable = 0x00000000U},
138 {.addr = 0x0024a124, .prod = 0x00000001, .disable = 0x00000000}, 137 {.addr = 0x0024a124U, .prod = 0x00000001U, .disable = 0x00000000U},
139}; 138};
140 139
141/* slcg PriRing */ 140/* slcg PriRing */
142static const struct gating_desc gv11b_slcg_priring[] = { 141static const struct gating_desc gv11b_slcg_priring[] = {
143 {.addr = 0x001200a8, .prod = 0x00000000, .disable = 0x00000001}, 142 {.addr = 0x001200a8U, .prod = 0x00000000U, .disable = 0x00000001U},
144}; 143};
145 144
146/* slcg pwr_csb */ 145/* slcg pwr_csb */
147static const struct gating_desc gv11b_slcg_pwr_csb[] = { 146static const struct gating_desc gv11b_slcg_pwr_csb[] = {
148 {.addr = 0x00000134, .prod = 0x00020008, .disable = 0x0003fffe}, 147 {.addr = 0x00000134U, .prod = 0x00020008U, .disable = 0x0003fffeU},
149 {.addr = 0x00000e74, .prod = 0x00000000, .disable = 0x0000000f}, 148 {.addr = 0x00000e74U, .prod = 0x00000000U, .disable = 0x0000000fU},
150 {.addr = 0x00000a74, .prod = 0x00004040, .disable = 0x00007ffe}, 149 {.addr = 0x00000a74U, .prod = 0x00004040U, .disable = 0x00007ffeU},
151 {.addr = 0x000206b8, .prod = 0x00000008, .disable = 0x0000000f}, 150 {.addr = 0x000206b8U, .prod = 0x00000008U, .disable = 0x0000000fU},
152}; 151};
153 152
154/* slcg pmu */ 153/* slcg pmu */
155static const struct gating_desc gv11b_slcg_pmu[] = { 154static const struct gating_desc gv11b_slcg_pmu[] = {
156 {.addr = 0x0010a134, .prod = 0x00020008, .disable = 0x0003fffe}, 155 {.addr = 0x0010a134U, .prod = 0x00020008U, .disable = 0x0003fffeU},
157 {.addr = 0x0010aa74, .prod = 0x00004040, .disable = 0x00007ffe}, 156 {.addr = 0x0010aa74U, .prod = 0x00004040U, .disable = 0x00007ffeU},
158 {.addr = 0x0010ae74, .prod = 0x00000000, .disable = 0x0000000f}, 157 {.addr = 0x0010ae74U, .prod = 0x00000000U, .disable = 0x0000000fU},
159}; 158};
160 159
161/* therm gr */ 160/* therm gr */
162static const struct gating_desc gv11b_slcg_therm[] = { 161static const struct gating_desc gv11b_slcg_therm[] = {
163 {.addr = 0x000206b8, .prod = 0x00000008, .disable = 0x0000000f}, 162 {.addr = 0x000206b8U, .prod = 0x00000008U, .disable = 0x0000000fU},
164}; 163};
165 164
166/* slcg Xbar */ 165/* slcg Xbar */
167static const struct gating_desc gv11b_slcg_xbar[] = { 166static const struct gating_desc gv11b_slcg_xbar[] = {
168 {.addr = 0x0013c824, .prod = 0x00000000, .disable = 0x7ffffffe}, 167 {.addr = 0x0013c824U, .prod = 0x00000000U, .disable = 0x7ffffffeU},
169 {.addr = 0x0013dc08, .prod = 0x00000000, .disable = 0xfffffffe}, 168 {.addr = 0x0013dc08U, .prod = 0x00000000U, .disable = 0xfffffffeU},
170 {.addr = 0x0013c924, .prod = 0x00000000, .disable = 0x7ffffffe}, 169 {.addr = 0x0013c924U, .prod = 0x00000000U, .disable = 0x7ffffffeU},
171 {.addr = 0x0013cbe4, .prod = 0x00000000, .disable = 0x1ffffffe}, 170 {.addr = 0x0013cbe4U, .prod = 0x00000000U, .disable = 0x1ffffffeU},
172 {.addr = 0x0013cc04, .prod = 0x00000000, .disable = 0x1ffffffe}, 171 {.addr = 0x0013cc04U, .prod = 0x00000000U, .disable = 0x1ffffffeU},
173}; 172};
174 173
175/* blcg bus */ 174/* blcg bus */
176static const struct gating_desc gv11b_blcg_bus[] = { 175static const struct gating_desc gv11b_blcg_bus[] = {
177 {.addr = 0x00001c00, .prod = 0x00000042, .disable = 0x00000000}, 176 {.addr = 0x00001c00U, .prod = 0x00000042U, .disable = 0x00000000U},
178}; 177};
179 178
180/* blcg ce */ 179/* blcg ce */
181static const struct gating_desc gv11b_blcg_ce[] = { 180static const struct gating_desc gv11b_blcg_ce[] = {
182 {.addr = 0x00104200, .prod = 0x0000c242, .disable = 0x00000000}, 181 {.addr = 0x00104200U, .prod = 0x0000c242U, .disable = 0x00000000U},
183}; 182};
184 183
185/* blcg ctxsw prog */ 184/* blcg ctxsw prog */
@@ -188,97 +187,99 @@ static const struct gating_desc gv11b_blcg_ctxsw_prog[] = {
188 187
189/* blcg fb */ 188/* blcg fb */
190static const struct gating_desc gv11b_blcg_fb[] = { 189static const struct gating_desc gv11b_blcg_fb[] = {
191 {.addr = 0x00100d10, .prod = 0x0000c242, .disable = 0x00000000}, 190 {.addr = 0x00100d10U, .prod = 0x0000c242U, .disable = 0x00000000U},
192 {.addr = 0x00100d30, .prod = 0x0000c242, .disable = 0x00000000}, 191 {.addr = 0x00100d30U, .prod = 0x0000c242U, .disable = 0x00000000U},
193 {.addr = 0x00100d3c, .prod = 0x00000242, .disable = 0x00000000}, 192 {.addr = 0x00100d3cU, .prod = 0x00000242U, .disable = 0x00000000U},
194 {.addr = 0x00100d48, .prod = 0x0000c242, .disable = 0x00000000}, 193 {.addr = 0x00100d48U, .prod = 0x0000c242U, .disable = 0x00000000U},
195 {.addr = 0x00100c98, .prod = 0x00004242, .disable = 0x00000000}, 194 /* fix priv error */
195 /*{.addr = 0x00100d1cU, .prod = 0x00000042U, .disable = 0x00000000U},*/
196 {.addr = 0x00100c98U, .prod = 0x00004242U, .disable = 0x00000000U},
196}; 197};
197 198
198/* blcg fifo */ 199/* blcg fifo */
199static const struct gating_desc gv11b_blcg_fifo[] = { 200static const struct gating_desc gv11b_blcg_fifo[] = {
200 {.addr = 0x000026e0, .prod = 0x0000c244, .disable = 0x00000000}, 201 {.addr = 0x000026e0U, .prod = 0x0000c244U, .disable = 0x00000000U},
201}; 202};
202 203
203/* blcg gr */ 204/* blcg gr */
204static const struct gating_desc gv11b_blcg_gr[] = { 205static const struct gating_desc gv11b_blcg_gr[] = {
205 {.addr = 0x004041f0, .prod = 0x0000c646, .disable = 0x00000000}, 206 {.addr = 0x004041f0U, .prod = 0x0000c646U, .disable = 0x00000000U},
206 {.addr = 0x00409890, .prod = 0x0000007f, .disable = 0x00000000}, 207 {.addr = 0x00409890U, .prod = 0x0000007fU, .disable = 0x00000000U},
207 {.addr = 0x004098b0, .prod = 0x0000007f, .disable = 0x00000000}, 208 {.addr = 0x004098b0U, .prod = 0x0000007fU, .disable = 0x00000000U},
208 {.addr = 0x004078c0, .prod = 0x00004242, .disable = 0x00000000}, 209 {.addr = 0x004078c0U, .prod = 0x00004242U, .disable = 0x00000000U},
209 {.addr = 0x00406000, .prod = 0x0000c444, .disable = 0x00000000}, 210 {.addr = 0x00406000U, .prod = 0x0000c444U, .disable = 0x00000000U},
210 {.addr = 0x00405860, .prod = 0x0000c242, .disable = 0x00000000}, 211 {.addr = 0x00405860U, .prod = 0x0000c242U, .disable = 0x00000000U},
211 {.addr = 0x0040590c, .prod = 0x0000c444, .disable = 0x00000000}, 212 {.addr = 0x0040590cU, .prod = 0x0000c444U, .disable = 0x00000000U},
212 {.addr = 0x00408040, .prod = 0x0000c444, .disable = 0x00000000}, 213 {.addr = 0x00408040U, .prod = 0x0000c444U, .disable = 0x00000000U},
213 {.addr = 0x00407000, .prod = 0x4000c242, .disable = 0x00000000}, 214 {.addr = 0x00407000U, .prod = 0x4000c242U, .disable = 0x00000000U},
214 {.addr = 0x00405bf0, .prod = 0x0000c444, .disable = 0x00000000}, 215 {.addr = 0x00405bf0U, .prod = 0x0000c444U, .disable = 0x00000000U},
215 {.addr = 0x0041a890, .prod = 0x0000427f, .disable = 0x00000000}, 216 {.addr = 0x0041a890U, .prod = 0x0000427fU, .disable = 0x00000000U},
216 {.addr = 0x0041a8b0, .prod = 0x0000007f, .disable = 0x00000000}, 217 {.addr = 0x0041a8b0U, .prod = 0x0000007fU, .disable = 0x00000000U},
217 {.addr = 0x00418500, .prod = 0x0000c244, .disable = 0x00000000}, 218 {.addr = 0x00418500U, .prod = 0x0000c244U, .disable = 0x00000000U},
218 {.addr = 0x00418608, .prod = 0x0000c242, .disable = 0x00000000}, 219 {.addr = 0x00418608U, .prod = 0x0000c242U, .disable = 0x00000000U},
219 {.addr = 0x00418688, .prod = 0x0000c242, .disable = 0x00000000}, 220 {.addr = 0x00418688U, .prod = 0x0000c242U, .disable = 0x00000000U},
220 {.addr = 0x00418718, .prod = 0x00000042, .disable = 0x00000000}, 221 {.addr = 0x00418718U, .prod = 0x00000042U, .disable = 0x00000000U},
221 {.addr = 0x00418828, .prod = 0x00008444, .disable = 0x00000000}, 222 {.addr = 0x00418828U, .prod = 0x00008444U, .disable = 0x00000000U},
222 {.addr = 0x00418bbc, .prod = 0x0000c242, .disable = 0x00000000}, 223 {.addr = 0x00418bbcU, .prod = 0x0000c242U, .disable = 0x00000000U},
223 {.addr = 0x00418970, .prod = 0x0000c242, .disable = 0x00000000}, 224 {.addr = 0x00418970U, .prod = 0x0000c242U, .disable = 0x00000000U},
224 {.addr = 0x00418c70, .prod = 0x0000c444, .disable = 0x00000000}, 225 {.addr = 0x00418c70U, .prod = 0x0000c444U, .disable = 0x00000000U},
225 {.addr = 0x00418cf0, .prod = 0x0000c444, .disable = 0x00000000}, 226 {.addr = 0x00418cf0U, .prod = 0x0000c444U, .disable = 0x00000000U},
226 {.addr = 0x00418d70, .prod = 0x0000c444, .disable = 0x00000000}, 227 {.addr = 0x00418d70U, .prod = 0x0000c444U, .disable = 0x00000000U},
227 {.addr = 0x00418f0c, .prod = 0x0000c444, .disable = 0x00000000}, 228 {.addr = 0x00418f0cU, .prod = 0x0000c444U, .disable = 0x00000000U},
228 {.addr = 0x00418e0c, .prod = 0x0000c444, .disable = 0x00000000}, 229 {.addr = 0x00418e0cU, .prod = 0x0000c444U, .disable = 0x00000000U},
229 {.addr = 0x00419020, .prod = 0x0000c242, .disable = 0x00000000}, 230 {.addr = 0x00419020U, .prod = 0x0000c242U, .disable = 0x00000000U},
230 {.addr = 0x00419038, .prod = 0x00000042, .disable = 0x00000000}, 231 {.addr = 0x00419038U, .prod = 0x00000042U, .disable = 0x00000000U},
231 {.addr = 0x00418898, .prod = 0x00004242, .disable = 0x00000000}, 232 {.addr = 0x00418898U, .prod = 0x00004242U, .disable = 0x00000000U},
232 {.addr = 0x00419868, .prod = 0x00008243, .disable = 0x00000000}, 233 {.addr = 0x00419868U, .prod = 0x00008243U, .disable = 0x00000000U},
233 {.addr = 0x00419c70, .prod = 0x0000c444, .disable = 0x00000000}, 234 {.addr = 0x00419c70U, .prod = 0x0000c444U, .disable = 0x00000000U},
234 {.addr = 0x00419c80, .prod = 0x00004045, .disable = 0x00000000}, 235 {.addr = 0x00419c80U, .prod = 0x00004045U, .disable = 0x00000000U},
235 {.addr = 0x00419c88, .prod = 0x00004043, .disable = 0x00000000}, 236 {.addr = 0x00419c88U, .prod = 0x00004043U, .disable = 0x00000000U},
236 {.addr = 0x00419c90, .prod = 0x0000004a, .disable = 0x00000000}, 237 {.addr = 0x00419c90U, .prod = 0x0000004aU, .disable = 0x00000000U},
237 {.addr = 0x00419c98, .prod = 0x00000042, .disable = 0x00000000}, 238 {.addr = 0x00419c98U, .prod = 0x00000042U, .disable = 0x00000000U},
238 {.addr = 0x00419ca0, .prod = 0x00000043, .disable = 0x00000000}, 239 {.addr = 0x00419ca0U, .prod = 0x00000043U, .disable = 0x00000000U},
239 {.addr = 0x00419ca8, .prod = 0x00000003, .disable = 0x00000000}, 240 {.addr = 0x00419ca8U, .prod = 0x00000003U, .disable = 0x00000000U},
240 {.addr = 0x00419cb0, .prod = 0x00000002, .disable = 0x00000000}, 241 {.addr = 0x00419cb0U, .prod = 0x00000002U, .disable = 0x00000000U},
241 {.addr = 0x00419a40, .prod = 0x00000242, .disable = 0x00000000}, 242 {.addr = 0x00419a40U, .prod = 0x00000242U, .disable = 0x00000000U},
242 {.addr = 0x00419a48, .prod = 0x00000242, .disable = 0x00000000}, 243 {.addr = 0x00419a48U, .prod = 0x00000242U, .disable = 0x00000000U},
243 {.addr = 0x00419a50, .prod = 0x00000242, .disable = 0x00000000}, 244 {.addr = 0x00419a50U, .prod = 0x00000242U, .disable = 0x00000000U},
244 {.addr = 0x00419a58, .prod = 0x00000242, .disable = 0x00000000}, 245 {.addr = 0x00419a58U, .prod = 0x00000242U, .disable = 0x00000000U},
245 {.addr = 0x00419a60, .prod = 0x00000202, .disable = 0x00000000}, 246 {.addr = 0x00419a60U, .prod = 0x00000202U, .disable = 0x00000000U},
246 {.addr = 0x00419a68, .prod = 0x00000202, .disable = 0x00000000}, 247 {.addr = 0x00419a68U, .prod = 0x00000202U, .disable = 0x00000000U},
247 {.addr = 0x00419a78, .prod = 0x00000242, .disable = 0x00000000}, 248 {.addr = 0x00419a78U, .prod = 0x00000242U, .disable = 0x00000000U},
248 {.addr = 0x00419a80, .prod = 0x00000242, .disable = 0x00000000}, 249 {.addr = 0x00419a80U, .prod = 0x00000242U, .disable = 0x00000000U},
249 {.addr = 0x0041be28, .prod = 0x00008242, .disable = 0x00000000}, 250 {.addr = 0x0041be28U, .prod = 0x00008242U, .disable = 0x00000000U},
250 {.addr = 0x0041bfe8, .prod = 0x0000c444, .disable = 0x00000000}, 251 {.addr = 0x0041bfe8U, .prod = 0x0000c444U, .disable = 0x00000000U},
251 {.addr = 0x0041bed0, .prod = 0x0000c444, .disable = 0x00000000}, 252 {.addr = 0x0041bed0U, .prod = 0x0000c444U, .disable = 0x00000000U},
252 {.addr = 0x00408810, .prod = 0x0000c242, .disable = 0x00000000}, 253 {.addr = 0x00408810U, .prod = 0x0000c242U, .disable = 0x00000000U},
253 {.addr = 0x00408a80, .prod = 0x0000c242, .disable = 0x00000000}, 254 {.addr = 0x00408a80U, .prod = 0x0000c242U, .disable = 0x00000000U},
254 {.addr = 0x004089a8, .prod = 0x0000c242, .disable = 0x00000000}, 255 {.addr = 0x004089a8U, .prod = 0x0000c242U, .disable = 0x00000000U},
255}; 256};
256 257
257/* blcg ltc */ 258/* blcg ltc */
258static const struct gating_desc gv11b_blcg_ltc[] = { 259static const struct gating_desc gv11b_blcg_ltc[] = {
259 {.addr = 0x0017e030, .prod = 0x00000044, .disable = 0x00000000}, 260 {.addr = 0x0017e030U, .prod = 0x00000044U, .disable = 0x00000000U},
260 {.addr = 0x0017e040, .prod = 0x00000044, .disable = 0x00000000}, 261 {.addr = 0x0017e040U, .prod = 0x00000044U, .disable = 0x00000000U},
261 {.addr = 0x0017e3e0, .prod = 0x00000044, .disable = 0x00000000}, 262 {.addr = 0x0017e3e0U, .prod = 0x00000044U, .disable = 0x00000000U},
262 {.addr = 0x0017e3c8, .prod = 0x00000044, .disable = 0x00000000}, 263 {.addr = 0x0017e3c8U, .prod = 0x00000044U, .disable = 0x00000000U},
263}; 264};
264 265
265/* blcg pwr_csb */ 266/* blcg pwr_csb */
266static const struct gating_desc gv11b_blcg_pwr_csb[] = { 267static const struct gating_desc gv11b_blcg_pwr_csb[] = {
267 {.addr = 0x00000a70, .prod = 0x00000045, .disable = 0x00000000}, 268 {.addr = 0x00000a70U, .prod = 0x00000045U, .disable = 0x00000000U},
268}; 269};
269 270
270/* blcg pmu */ 271/* blcg pmu */
271static const struct gating_desc gv11b_blcg_pmu[] = { 272static const struct gating_desc gv11b_blcg_pmu[] = {
272 {.addr = 0x0010aa70, .prod = 0x00000045, .disable = 0x00000000}, 273 {.addr = 0x0010aa70U, .prod = 0x00000045U, .disable = 0x00000000U},
273}; 274};
274 275
275/* blcg Xbar */ 276/* blcg Xbar */
276static const struct gating_desc gv11b_blcg_xbar[] = { 277static const struct gating_desc gv11b_blcg_xbar[] = {
277 {.addr = 0x0013c820, .prod = 0x0001004a, .disable = 0x00000000}, 278 {.addr = 0x0013c820U, .prod = 0x0001004aU, .disable = 0x00000000U},
278 {.addr = 0x0013dc04, .prod = 0x0001004a, .disable = 0x00000000}, 279 {.addr = 0x0013dc04U, .prod = 0x0001004aU, .disable = 0x00000000U},
279 {.addr = 0x0013c920, .prod = 0x0000004a, .disable = 0x00000000}, 280 {.addr = 0x0013c920U, .prod = 0x0000004aU, .disable = 0x00000000U},
280 {.addr = 0x0013cbe0, .prod = 0x00000042, .disable = 0x00000000}, 281 {.addr = 0x0013cbe0U, .prod = 0x00000042U, .disable = 0x00000000U},
281 {.addr = 0x0013cc00, .prod = 0x00000042, .disable = 0x00000000}, 282 {.addr = 0x0013cc00U, .prod = 0x00000042U, .disable = 0x00000000U},
282}; 283};
283 284
284/* pg gr */ 285/* pg gr */
@@ -290,18 +291,15 @@ void gv11b_slcg_bus_load_gating_prod(struct gk20a *g,
290 bool prod) 291 bool prod)
291{ 292{
292 u32 i; 293 u32 i;
293 u32 size = sizeof(gv11b_slcg_bus) / sizeof(struct gating_desc); 294 u32 size = (u32)(sizeof(gv11b_slcg_bus) / GATING_DESC_SIZE);
294 295
295 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) 296 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
296 return; 297 for (i = 0; i < size; i++) {
297 298 u32 reg = gv11b_slcg_bus[i].addr;
298 for (i = 0; i < size; i++) { 299 u32 val = prod ? gv11b_slcg_bus[i].prod :
299 if (prod) 300 gv11b_slcg_bus[i].disable;
300 gk20a_writel(g, gv11b_slcg_bus[i].addr, 301 gk20a_writel(g, reg, val);
301 gv11b_slcg_bus[i].prod); 302 }
302 else
303 gk20a_writel(g, gv11b_slcg_bus[i].addr,
304 gv11b_slcg_bus[i].disable);
305 } 303 }
306} 304}
307 305
@@ -309,18 +307,15 @@ void gv11b_slcg_ce2_load_gating_prod(struct gk20a *g,
309 bool prod) 307 bool prod)
310{ 308{
311 u32 i; 309 u32 i;
312 u32 size = sizeof(gv11b_slcg_ce2) / sizeof(struct gating_desc); 310 u32 size = (u32)(sizeof(gv11b_slcg_ce2) / GATING_DESC_SIZE);
313 311
314 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) 312 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
315 return; 313 for (i = 0; i < size; i++) {
316 314 u32 reg = gv11b_slcg_ce2[i].addr;
317 for (i = 0; i < size; i++) { 315 u32 val = prod ? gv11b_slcg_ce2[i].prod :
318 if (prod) 316 gv11b_slcg_ce2[i].disable;
319 gk20a_writel(g, gv11b_slcg_ce2[i].addr, 317 gk20a_writel(g, reg, val);
320 gv11b_slcg_ce2[i].prod); 318 }
321 else
322 gk20a_writel(g, gv11b_slcg_ce2[i].addr,
323 gv11b_slcg_ce2[i].disable);
324 } 319 }
325} 320}
326 321
@@ -328,42 +323,38 @@ void gv11b_slcg_chiplet_load_gating_prod(struct gk20a *g,
328 bool prod) 323 bool prod)
329{ 324{
330 u32 i; 325 u32 i;
331 u32 size = sizeof(gv11b_slcg_chiplet) / sizeof(struct gating_desc); 326 u32 size = (u32)(sizeof(gv11b_slcg_chiplet) / GATING_DESC_SIZE);
332 327
333 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) 328 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
334 return; 329 for (i = 0; i < size; i++) {
335 330 u32 reg = gv11b_slcg_chiplet[i].addr;
336 for (i = 0; i < size; i++) { 331 u32 val = prod ? gv11b_slcg_chiplet[i].prod :
337 if (prod) 332 gv11b_slcg_chiplet[i].disable;
338 gk20a_writel(g, gv11b_slcg_chiplet[i].addr, 333 gk20a_writel(g, reg, val);
339 gv11b_slcg_chiplet[i].prod); 334 }
340 else
341 gk20a_writel(g, gv11b_slcg_chiplet[i].addr,
342 gv11b_slcg_chiplet[i].disable);
343 } 335 }
344} 336}
345 337
346void gv11b_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, 338void gv11b_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g,
347 bool prod) 339 bool prod)
348{ 340{
341 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
342 }
349} 343}
350 344
351void gv11b_slcg_fb_load_gating_prod(struct gk20a *g, 345void gv11b_slcg_fb_load_gating_prod(struct gk20a *g,
352 bool prod) 346 bool prod)
353{ 347{
354 u32 i; 348 u32 i;
355 u32 size = sizeof(gv11b_slcg_fb) / sizeof(struct gating_desc); 349 u32 size = (u32)(sizeof(gv11b_slcg_fb) / GATING_DESC_SIZE);
356 350
357 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) 351 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
358 return; 352 for (i = 0; i < size; i++) {
359 353 u32 reg = gv11b_slcg_fb[i].addr;
360 for (i = 0; i < size; i++) { 354 u32 val = prod ? gv11b_slcg_fb[i].prod :
361 if (prod) 355 gv11b_slcg_fb[i].disable;
362 gk20a_writel(g, gv11b_slcg_fb[i].addr, 356 gk20a_writel(g, reg, val);
363 gv11b_slcg_fb[i].prod); 357 }
364 else
365 gk20a_writel(g, gv11b_slcg_fb[i].addr,
366 gv11b_slcg_fb[i].disable);
367 } 358 }
368} 359}
369 360
@@ -371,18 +362,15 @@ void gv11b_slcg_fifo_load_gating_prod(struct gk20a *g,
371 bool prod) 362 bool prod)
372{ 363{
373 u32 i; 364 u32 i;
374 u32 size = sizeof(gv11b_slcg_fifo) / sizeof(struct gating_desc); 365 u32 size = (u32)(sizeof(gv11b_slcg_fifo) / GATING_DESC_SIZE);
375 366
376 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) 367 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
377 return; 368 for (i = 0; i < size; i++) {
378 369 u32 reg = gv11b_slcg_fifo[i].addr;
379 for (i = 0; i < size; i++) { 370 u32 val = prod ? gv11b_slcg_fifo[i].prod :
380 if (prod) 371 gv11b_slcg_fifo[i].disable;
381 gk20a_writel(g, gv11b_slcg_fifo[i].addr, 372 gk20a_writel(g, reg, val);
382 gv11b_slcg_fifo[i].prod); 373 }
383 else
384 gk20a_writel(g, gv11b_slcg_fifo[i].addr,
385 gv11b_slcg_fifo[i].disable);
386 } 374 }
387} 375}
388 376
@@ -390,18 +378,15 @@ void gr_gv11b_slcg_gr_load_gating_prod(struct gk20a *g,
390 bool prod) 378 bool prod)
391{ 379{
392 u32 i; 380 u32 i;
393 u32 size = sizeof(gv11b_slcg_gr) / sizeof(struct gating_desc); 381 u32 size = (u32)(sizeof(gv11b_slcg_gr) / GATING_DESC_SIZE);
394 382
395 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) 383 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
396 return; 384 for (i = 0; i < size; i++) {
397 385 u32 reg = gv11b_slcg_gr[i].addr;
398 for (i = 0; i < size; i++) { 386 u32 val = prod ? gv11b_slcg_gr[i].prod :
399 if (prod) 387 gv11b_slcg_gr[i].disable;
400 gk20a_writel(g, gv11b_slcg_gr[i].addr, 388 gk20a_writel(g, reg, val);
401 gv11b_slcg_gr[i].prod); 389 }
402 else
403 gk20a_writel(g, gv11b_slcg_gr[i].addr,
404 gv11b_slcg_gr[i].disable);
405 } 390 }
406} 391}
407 392
@@ -409,18 +394,15 @@ void ltc_gv11b_slcg_ltc_load_gating_prod(struct gk20a *g,
409 bool prod) 394 bool prod)
410{ 395{
411 u32 i; 396 u32 i;
412 u32 size = sizeof(gv11b_slcg_ltc) / sizeof(struct gating_desc); 397 u32 size = (u32)(sizeof(gv11b_slcg_ltc) / GATING_DESC_SIZE);
413
414 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
415 return;
416 398
399 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
417 for (i = 0; i < size; i++) { 400 for (i = 0; i < size; i++) {
418 if (prod) 401 u32 reg = gv11b_slcg_ltc[i].addr;
419 gk20a_writel(g, gv11b_slcg_ltc[i].addr, 402 u32 val = prod ? gv11b_slcg_ltc[i].prod :
420 gv11b_slcg_ltc[i].prod); 403 gv11b_slcg_ltc[i].disable;
421 else 404 gk20a_writel(g, reg, val);
422 gk20a_writel(g, gv11b_slcg_ltc[i].addr, 405 }
423 gv11b_slcg_ltc[i].disable);
424 } 406 }
425} 407}
426 408
@@ -428,18 +410,15 @@ void gv11b_slcg_perf_load_gating_prod(struct gk20a *g,
428 bool prod) 410 bool prod)
429{ 411{
430 u32 i; 412 u32 i;
431 u32 size = sizeof(gv11b_slcg_perf) / sizeof(struct gating_desc); 413 u32 size = (u32)(sizeof(gv11b_slcg_perf) / GATING_DESC_SIZE);
432 414
433 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) 415 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
434 return; 416 for (i = 0; i < size; i++) {
435 417 u32 reg = gv11b_slcg_perf[i].addr;
436 for (i = 0; i < size; i++) { 418 u32 val = prod ? gv11b_slcg_perf[i].prod :
437 if (prod) 419 gv11b_slcg_perf[i].disable;
438 gk20a_writel(g, gv11b_slcg_perf[i].addr, 420 gk20a_writel(g, reg, val);
439 gv11b_slcg_perf[i].prod); 421 }
440 else
441 gk20a_writel(g, gv11b_slcg_perf[i].addr,
442 gv11b_slcg_perf[i].disable);
443 } 422 }
444} 423}
445 424
@@ -447,18 +426,15 @@ void gv11b_slcg_priring_load_gating_prod(struct gk20a *g,
447 bool prod) 426 bool prod)
448{ 427{
449 u32 i; 428 u32 i;
450 u32 size = sizeof(gv11b_slcg_priring) / sizeof(struct gating_desc); 429 u32 size = (u32)(sizeof(gv11b_slcg_priring) / GATING_DESC_SIZE);
451 430
452 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) 431 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
453 return; 432 for (i = 0; i < size; i++) {
454 433 u32 reg = gv11b_slcg_priring[i].addr;
455 for (i = 0; i < size; i++) { 434 u32 val = prod ? gv11b_slcg_priring[i].prod :
456 if (prod) 435 gv11b_slcg_priring[i].disable;
457 gk20a_writel(g, gv11b_slcg_priring[i].addr, 436 gk20a_writel(g, reg, val);
458 gv11b_slcg_priring[i].prod); 437 }
459 else
460 gk20a_writel(g, gv11b_slcg_priring[i].addr,
461 gv11b_slcg_priring[i].disable);
462 } 438 }
463} 439}
464 440
@@ -466,18 +442,15 @@ void gv11b_slcg_pwr_csb_load_gating_prod(struct gk20a *g,
466 bool prod) 442 bool prod)
467{ 443{
468 u32 i; 444 u32 i;
469 u32 size = sizeof(gv11b_slcg_pwr_csb) / sizeof(struct gating_desc); 445 u32 size = (u32)(sizeof(gv11b_slcg_pwr_csb) / GATING_DESC_SIZE);
470 446
471 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) 447 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
472 return; 448 for (i = 0; i < size; i++) {
473 449 u32 reg = gv11b_slcg_pwr_csb[i].addr;
474 for (i = 0; i < size; i++) { 450 u32 val = prod ? gv11b_slcg_pwr_csb[i].prod :
475 if (prod) 451 gv11b_slcg_pwr_csb[i].disable;
476 gk20a_writel(g, gv11b_slcg_pwr_csb[i].addr, 452 gk20a_writel(g, reg, val);
477 gv11b_slcg_pwr_csb[i].prod); 453 }
478 else
479 gk20a_writel(g, gv11b_slcg_pwr_csb[i].addr,
480 gv11b_slcg_pwr_csb[i].disable);
481 } 454 }
482} 455}
483 456
@@ -485,18 +458,15 @@ void gv11b_slcg_pmu_load_gating_prod(struct gk20a *g,
485 bool prod) 458 bool prod)
486{ 459{
487 u32 i; 460 u32 i;
488 u32 size = sizeof(gv11b_slcg_pmu) / sizeof(struct gating_desc); 461 u32 size = (u32)(sizeof(gv11b_slcg_pmu) / GATING_DESC_SIZE);
489 462
490 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) 463 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
491 return; 464 for (i = 0; i < size; i++) {
492 465 u32 reg = gv11b_slcg_pmu[i].addr;
493 for (i = 0; i < size; i++) { 466 u32 val = prod ? gv11b_slcg_pmu[i].prod :
494 if (prod) 467 gv11b_slcg_pmu[i].disable;
495 gk20a_writel(g, gv11b_slcg_pmu[i].addr, 468 gk20a_writel(g, reg, val);
496 gv11b_slcg_pmu[i].prod); 469 }
497 else
498 gk20a_writel(g, gv11b_slcg_pmu[i].addr,
499 gv11b_slcg_pmu[i].disable);
500 } 470 }
501} 471}
502 472
@@ -504,18 +474,15 @@ void gv11b_slcg_therm_load_gating_prod(struct gk20a *g,
504 bool prod) 474 bool prod)
505{ 475{
506 u32 i; 476 u32 i;
507 u32 size = sizeof(gv11b_slcg_therm) / sizeof(struct gating_desc); 477 u32 size = (u32)(sizeof(gv11b_slcg_therm) / GATING_DESC_SIZE);
508 478
509 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) 479 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
510 return; 480 for (i = 0; i < size; i++) {
511 481 u32 reg = gv11b_slcg_therm[i].addr;
512 for (i = 0; i < size; i++) { 482 u32 val = prod ? gv11b_slcg_therm[i].prod :
513 if (prod) 483 gv11b_slcg_therm[i].disable;
514 gk20a_writel(g, gv11b_slcg_therm[i].addr, 484 gk20a_writel(g, reg, val);
515 gv11b_slcg_therm[i].prod); 485 }
516 else
517 gk20a_writel(g, gv11b_slcg_therm[i].addr,
518 gv11b_slcg_therm[i].disable);
519 } 486 }
520} 487}
521 488
@@ -523,18 +490,15 @@ void gv11b_slcg_xbar_load_gating_prod(struct gk20a *g,
523 bool prod) 490 bool prod)
524{ 491{
525 u32 i; 492 u32 i;
526 u32 size = sizeof(gv11b_slcg_xbar) / sizeof(struct gating_desc); 493 u32 size = (u32)(sizeof(gv11b_slcg_xbar) / GATING_DESC_SIZE);
527 494
528 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) 495 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
529 return; 496 for (i = 0; i < size; i++) {
530 497 u32 reg = gv11b_slcg_xbar[i].addr;
531 for (i = 0; i < size; i++) { 498 u32 val = prod ? gv11b_slcg_xbar[i].prod :
532 if (prod) 499 gv11b_slcg_xbar[i].disable;
533 gk20a_writel(g, gv11b_slcg_xbar[i].addr, 500 gk20a_writel(g, reg, val);
534 gv11b_slcg_xbar[i].prod); 501 }
535 else
536 gk20a_writel(g, gv11b_slcg_xbar[i].addr,
537 gv11b_slcg_xbar[i].disable);
538 } 502 }
539} 503}
540 504
@@ -542,18 +506,15 @@ void gv11b_blcg_bus_load_gating_prod(struct gk20a *g,
542 bool prod) 506 bool prod)
543{ 507{
544 u32 i; 508 u32 i;
545 u32 size = sizeof(gv11b_blcg_bus) / sizeof(struct gating_desc); 509 u32 size = (u32)(sizeof(gv11b_blcg_bus) / GATING_DESC_SIZE);
546 510
547 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) 511 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
548 return; 512 for (i = 0; i < size; i++) {
549 513 u32 reg = gv11b_blcg_bus[i].addr;
550 for (i = 0; i < size; i++) { 514 u32 val = prod ? gv11b_blcg_bus[i].prod :
551 if (prod) 515 gv11b_blcg_bus[i].disable;
552 gk20a_writel(g, gv11b_blcg_bus[i].addr, 516 gk20a_writel(g, reg, val);
553 gv11b_blcg_bus[i].prod); 517 }
554 else
555 gk20a_writel(g, gv11b_blcg_bus[i].addr,
556 gv11b_blcg_bus[i].disable);
557 } 518 }
558} 519}
559 520
@@ -561,18 +522,15 @@ void gv11b_blcg_ce_load_gating_prod(struct gk20a *g,
561 bool prod) 522 bool prod)
562{ 523{
563 u32 i; 524 u32 i;
564 u32 size = sizeof(gv11b_blcg_ce) / sizeof(struct gating_desc); 525 u32 size = (u32)(sizeof(gv11b_blcg_ce) / GATING_DESC_SIZE);
565 526
566 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) 527 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
567 return; 528 for (i = 0; i < size; i++) {
568 529 u32 reg = gv11b_blcg_ce[i].addr;
569 for (i = 0; i < size; i++) { 530 u32 val = prod ? gv11b_blcg_ce[i].prod :
570 if (prod) 531 gv11b_blcg_ce[i].disable;
571 gk20a_writel(g, gv11b_blcg_ce[i].addr, 532 gk20a_writel(g, reg, val);
572 gv11b_blcg_ce[i].prod); 533 }
573 else
574 gk20a_writel(g, gv11b_blcg_ce[i].addr,
575 gv11b_blcg_ce[i].disable);
576 } 534 }
577} 535}
578 536
@@ -580,18 +538,15 @@ void gv11b_blcg_ctxsw_firmware_load_gating_prod(struct gk20a *g,
580 bool prod) 538 bool prod)
581{ 539{
582 u32 i; 540 u32 i;
583 u32 size = sizeof(gv11b_blcg_ctxsw_prog) / sizeof(struct gating_desc); 541 u32 size = (u32)(sizeof(gv11b_blcg_ctxsw_prog) / GATING_DESC_SIZE);
584 542
585 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) 543 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
586 return; 544 for (i = 0; i < size; i++) {
587 545 u32 reg = gv11b_blcg_ctxsw_prog[i].addr;
588 for (i = 0; i < size; i++) { 546 u32 val = prod ? gv11b_blcg_ctxsw_prog[i].prod :
589 if (prod) 547 gv11b_blcg_ctxsw_prog[i].disable;
590 gk20a_writel(g, gv11b_blcg_ctxsw_prog[i].addr, 548 gk20a_writel(g, reg, val);
591 gv11b_blcg_ctxsw_prog[i].prod); 549 }
592 else
593 gk20a_writel(g, gv11b_blcg_ctxsw_prog[i].addr,
594 gv11b_blcg_ctxsw_prog[i].disable);
595 } 550 }
596} 551}
597 552
@@ -599,18 +554,15 @@ void gv11b_blcg_fb_load_gating_prod(struct gk20a *g,
599 bool prod) 554 bool prod)
600{ 555{
601 u32 i; 556 u32 i;
602 u32 size = sizeof(gv11b_blcg_fb) / sizeof(struct gating_desc); 557 u32 size = (u32)(sizeof(gv11b_blcg_fb) / GATING_DESC_SIZE);
603 558
604 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) 559 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
605 return; 560 for (i = 0; i < size; i++) {
606 561 u32 reg = gv11b_blcg_fb[i].addr;
607 for (i = 0; i < size; i++) { 562 u32 val = prod ? gv11b_blcg_fb[i].prod :
608 if (prod) 563 gv11b_blcg_fb[i].disable;
609 gk20a_writel(g, gv11b_blcg_fb[i].addr, 564 gk20a_writel(g, reg, val);
610 gv11b_blcg_fb[i].prod); 565 }
611 else
612 gk20a_writel(g, gv11b_blcg_fb[i].addr,
613 gv11b_blcg_fb[i].disable);
614 } 566 }
615} 567}
616 568
@@ -618,18 +570,15 @@ void gv11b_blcg_fifo_load_gating_prod(struct gk20a *g,
618 bool prod) 570 bool prod)
619{ 571{
620 u32 i; 572 u32 i;
621 u32 size = sizeof(gv11b_blcg_fifo) / sizeof(struct gating_desc); 573 u32 size = (u32)(sizeof(gv11b_blcg_fifo) / GATING_DESC_SIZE);
622
623 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
624 return;
625 574
575 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
626 for (i = 0; i < size; i++) { 576 for (i = 0; i < size; i++) {
627 if (prod) 577 u32 reg = gv11b_blcg_fifo[i].addr;
628 gk20a_writel(g, gv11b_blcg_fifo[i].addr, 578 u32 val = prod ? gv11b_blcg_fifo[i].prod :
629 gv11b_blcg_fifo[i].prod); 579 gv11b_blcg_fifo[i].disable;
630 else 580 gk20a_writel(g, reg, val);
631 gk20a_writel(g, gv11b_blcg_fifo[i].addr, 581 }
632 gv11b_blcg_fifo[i].disable);
633 } 582 }
634} 583}
635 584
@@ -637,18 +586,15 @@ void gv11b_blcg_gr_load_gating_prod(struct gk20a *g,
637 bool prod) 586 bool prod)
638{ 587{
639 u32 i; 588 u32 i;
640 u32 size = sizeof(gv11b_blcg_gr) / sizeof(struct gating_desc); 589 u32 size = (u32)(sizeof(gv11b_blcg_gr) / GATING_DESC_SIZE);
641 590
642 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) 591 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
643 return; 592 for (i = 0; i < size; i++) {
644 593 u32 reg = gv11b_blcg_gr[i].addr;
645 for (i = 0; i < size; i++) { 594 u32 val = prod ? gv11b_blcg_gr[i].prod :
646 if (prod) 595 gv11b_blcg_gr[i].disable;
647 gk20a_writel(g, gv11b_blcg_gr[i].addr, 596 gk20a_writel(g, reg, val);
648 gv11b_blcg_gr[i].prod); 597 }
649 else
650 gk20a_writel(g, gv11b_blcg_gr[i].addr,
651 gv11b_blcg_gr[i].disable);
652 } 598 }
653} 599}
654 600
@@ -656,18 +602,15 @@ void gv11b_blcg_ltc_load_gating_prod(struct gk20a *g,
656 bool prod) 602 bool prod)
657{ 603{
658 u32 i; 604 u32 i;
659 u32 size = sizeof(gv11b_blcg_ltc) / sizeof(struct gating_desc); 605 u32 size = (u32)(sizeof(gv11b_blcg_ltc) / GATING_DESC_SIZE);
660 606
661 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) 607 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
662 return; 608 for (i = 0; i < size; i++) {
663 609 u32 reg = gv11b_blcg_ltc[i].addr;
664 for (i = 0; i < size; i++) { 610 u32 val = prod ? gv11b_blcg_ltc[i].prod :
665 if (prod) 611 gv11b_blcg_ltc[i].disable;
666 gk20a_writel(g, gv11b_blcg_ltc[i].addr, 612 gk20a_writel(g, reg, val);
667 gv11b_blcg_ltc[i].prod); 613 }
668 else
669 gk20a_writel(g, gv11b_blcg_ltc[i].addr,
670 gv11b_blcg_ltc[i].disable);
671 } 614 }
672} 615}
673 616
@@ -675,18 +618,15 @@ void gv11b_blcg_pwr_csb_load_gating_prod(struct gk20a *g,
675 bool prod) 618 bool prod)
676{ 619{
677 u32 i; 620 u32 i;
678 u32 size = sizeof(gv11b_blcg_pwr_csb) / sizeof(struct gating_desc); 621 u32 size = (u32)(sizeof(gv11b_blcg_pwr_csb) / GATING_DESC_SIZE);
679 622
680 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) 623 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
681 return; 624 for (i = 0; i < size; i++) {
682 625 u32 reg = gv11b_blcg_pwr_csb[i].addr;
683 for (i = 0; i < size; i++) { 626 u32 val = prod ? gv11b_blcg_pwr_csb[i].prod :
684 if (prod) 627 gv11b_blcg_pwr_csb[i].disable;
685 gk20a_writel(g, gv11b_blcg_pwr_csb[i].addr, 628 gk20a_writel(g, reg, val);
686 gv11b_blcg_pwr_csb[i].prod); 629 }
687 else
688 gk20a_writel(g, gv11b_blcg_pwr_csb[i].addr,
689 gv11b_blcg_pwr_csb[i].disable);
690 } 630 }
691} 631}
692 632
@@ -694,18 +634,15 @@ void gv11b_blcg_pmu_load_gating_prod(struct gk20a *g,
694 bool prod) 634 bool prod)
695{ 635{
696 u32 i; 636 u32 i;
697 u32 size = sizeof(gv11b_blcg_pmu) / sizeof(struct gating_desc); 637 u32 size = (u32)(sizeof(gv11b_blcg_pmu) / GATING_DESC_SIZE);
698 638
699 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) 639 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
700 return; 640 for (i = 0; i < size; i++) {
701 641 u32 reg = gv11b_blcg_pmu[i].addr;
702 for (i = 0; i < size; i++) { 642 u32 val = prod ? gv11b_blcg_pmu[i].prod :
703 if (prod) 643 gv11b_blcg_pmu[i].disable;
704 gk20a_writel(g, gv11b_blcg_pmu[i].addr, 644 gk20a_writel(g, reg, val);
705 gv11b_blcg_pmu[i].prod); 645 }
706 else
707 gk20a_writel(g, gv11b_blcg_pmu[i].addr,
708 gv11b_blcg_pmu[i].disable);
709 } 646 }
710} 647}
711 648
@@ -713,18 +650,15 @@ void gv11b_blcg_xbar_load_gating_prod(struct gk20a *g,
713 bool prod) 650 bool prod)
714{ 651{
715 u32 i; 652 u32 i;
716 u32 size = sizeof(gv11b_blcg_xbar) / sizeof(struct gating_desc); 653 u32 size = (u32)(sizeof(gv11b_blcg_xbar) / GATING_DESC_SIZE);
717 654
718 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) 655 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
719 return; 656 for (i = 0; i < size; i++) {
720 657 u32 reg = gv11b_blcg_xbar[i].addr;
721 for (i = 0; i < size; i++) { 658 u32 val = prod ? gv11b_blcg_xbar[i].prod :
722 if (prod) 659 gv11b_blcg_xbar[i].disable;
723 gk20a_writel(g, gv11b_blcg_xbar[i].addr, 660 gk20a_writel(g, reg, val);
724 gv11b_blcg_xbar[i].prod); 661 }
725 else
726 gk20a_writel(g, gv11b_blcg_xbar[i].addr,
727 gv11b_blcg_xbar[i].disable);
728 } 662 }
729} 663}
730 664
@@ -732,19 +666,14 @@ void gr_gv11b_pg_gr_load_gating_prod(struct gk20a *g,
732 bool prod) 666 bool prod)
733{ 667{
734 u32 i; 668 u32 i;
735 u32 size = sizeof(gv11b_pg_gr) / sizeof(struct gating_desc); 669 u32 size = (u32)(sizeof(gv11b_pg_gr) / GATING_DESC_SIZE);
736 670
737 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) 671 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
738 return; 672 for (i = 0; i < size; i++) {
739 673 u32 reg = gv11b_pg_gr[i].addr;
740 for (i = 0; i < size; i++) { 674 u32 val = prod ? gv11b_pg_gr[i].prod :
741 if (prod) 675 gv11b_pg_gr[i].disable;
742 gk20a_writel(g, gv11b_pg_gr[i].addr, 676 gk20a_writel(g, reg, val);
743 gv11b_pg_gr[i].prod); 677 }
744 else
745 gk20a_writel(g, gv11b_pg_gr[i].addr,
746 gv11b_pg_gr[i].disable);
747 } 678 }
748} 679}
749
750#endif /* __gv11b_gating_reglist_h__ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-07 13:13:12 -0400