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Diffstat (limited to 'drivers/gpu/nvgpu/common/clock_gating/gp106_gating_reglist.c')
-rw-r--r--drivers/gpu/nvgpu/common/clock_gating/gp106_gating_reglist.c769
1 files changed, 357 insertions, 412 deletions
diff --git a/drivers/gpu/nvgpu/common/clock_gating/gp106_gating_reglist.c b/drivers/gpu/nvgpu/common/clock_gating/gp106_gating_reglist.c
index 169a1fee..7a01200f 100644
--- a/drivers/gpu/nvgpu/common/clock_gating/gp106_gating_reglist.c
+++ b/drivers/gpu/nvgpu/common/clock_gating/gp106_gating_reglist.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a 4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"), 5 * copy of this software and associated documentation files (the "Software"),
@@ -22,249 +22,241 @@
22 * This file is autogenerated. Do not edit. 22 * This file is autogenerated. Do not edit.
23 */ 23 */
24 24
25#ifndef __gp106_gating_reglist_h__ 25#include <nvgpu/types.h>
26#define __gp106_gating_reglist_h__ 26#include <nvgpu/io.h>
27#include <nvgpu/enabled.h>
27 28
29#include "gating_reglist.h"
28#include "gp106_gating_reglist.h" 30#include "gp106_gating_reglist.h"
29#include <nvgpu/enabled.h>
30 31
31struct gating_desc { 32#define GATING_DESC_SIZE (u32)(sizeof(struct gating_desc))
32 u32 addr; 33
33 u32 prod;
34 u32 disable;
35};
36/* slcg bus */ 34/* slcg bus */
37static const struct gating_desc gp106_slcg_bus[] = { 35static const struct gating_desc gp106_slcg_bus[] = {
38 {.addr = 0x00001c04, .prod = 0x00000000, .disable = 0x000003fe}, 36 {.addr = 0x00001c04U, .prod = 0x00000000U, .disable = 0x000003feU},
39}; 37};
40 38
41/* slcg ce2 */ 39/* slcg ce2 */
42static const struct gating_desc gp106_slcg_ce2[] = { 40static const struct gating_desc gp106_slcg_ce2[] = {
43 {.addr = 0x00104204, .prod = 0x00000000, .disable = 0x000007fe}, 41 {.addr = 0x00104204U, .prod = 0x00000040U, .disable = 0x000007feU},
44}; 42};
45 43
46/* slcg chiplet */ 44/* slcg chiplet */
47static const struct gating_desc gp106_slcg_chiplet[] = { 45static const struct gating_desc gp106_slcg_chiplet[] = {
48 {.addr = 0x0010c07c, .prod = 0x00000000, .disable = 0x00000007}, 46 {.addr = 0x0010c07cU, .prod = 0x00000000U, .disable = 0x00000007U},
49 {.addr = 0x0010c0fc, .prod = 0x00000000, .disable = 0x00000007}, 47 {.addr = 0x0010e07cU, .prod = 0x00000000U, .disable = 0x00000007U},
50 {.addr = 0x0010e07c, .prod = 0x00000000, .disable = 0x00000007}, 48 {.addr = 0x0010d07cU, .prod = 0x00000000U, .disable = 0x00000007U},
51 {.addr = 0x0010d07c, .prod = 0x00000000, .disable = 0x00000007}, 49 {.addr = 0x0010e17cU, .prod = 0x00000000U, .disable = 0x00000007U},
52 {.addr = 0x0010d0fc, .prod = 0x00000000, .disable = 0x00000007},
53 {.addr = 0x0010e17c, .prod = 0x00000000, .disable = 0x00000007},
54}; 50};
55 51
56/* slcg fb */ 52/* slcg fb */
57static const struct gating_desc gp106_slcg_fb[] = { 53static const struct gating_desc gp106_slcg_fb[] = {
58 {.addr = 0x00100d14, .prod = 0x00000000, .disable = 0xfffffffe}, 54 {.addr = 0x00100d14U, .prod = 0x00000000U, .disable = 0xfffffffeU},
59 {.addr = 0x00100c9c, .prod = 0x00000000, .disable = 0x000001fe}, 55 {.addr = 0x00100c9cU, .prod = 0x00000000U, .disable = 0x000001feU},
60}; 56};
61 57
62/* slcg fifo */ 58/* slcg fifo */
63static const struct gating_desc gp106_slcg_fifo[] = { 59static const struct gating_desc gp106_slcg_fifo[] = {
64 {.addr = 0x000026ac, .prod = 0x00000000, .disable = 0x0001fffe}, 60 {.addr = 0x000026acU, .prod = 0x00000f40U, .disable = 0x0001fffeU},
65}; 61};
66 62
67/* slcg gr */ 63/* slcg gr */
68static const struct gating_desc gp106_slcg_gr[] = { 64static const struct gating_desc gp106_slcg_gr[] = {
69 {.addr = 0x004041f4, .prod = 0x00000000, .disable = 0x07fffffe}, 65 {.addr = 0x004041f4U, .prod = 0x00000002U, .disable = 0x03fffffeU},
70 {.addr = 0x0040917c, .prod = 0x00020008, .disable = 0x0003fffe}, 66 {.addr = 0x0040917cU, .prod = 0x00020008U, .disable = 0x0003fffeU},
71 {.addr = 0x00409894, .prod = 0x00000040, .disable = 0x03fffffe}, 67 {.addr = 0x00409894U, .prod = 0x00000040U, .disable = 0x03fffffeU},
72 {.addr = 0x004078c4, .prod = 0x00000000, .disable = 0x000001fe}, 68 {.addr = 0x004078c4U, .prod = 0x00000000U, .disable = 0x000001feU},
73 {.addr = 0x00406004, .prod = 0x00000000, .disable = 0x0001fffe}, 69 {.addr = 0x00406004U, .prod = 0x00000200U, .disable = 0x0001fffeU},
74 {.addr = 0x00405864, .prod = 0x00000000, .disable = 0x000001fe}, 70 {.addr = 0x00405864U, .prod = 0x00000000U, .disable = 0x000001feU},
75 {.addr = 0x00405910, .prod = 0xfffffff0, .disable = 0xfffffffe}, 71 {.addr = 0x00405910U, .prod = 0xfffffff0U, .disable = 0xfffffffeU},
76 {.addr = 0x00408044, .prod = 0x00000000, .disable = 0x000007fe}, 72 {.addr = 0x00408044U, .prod = 0x00000000U, .disable = 0x000007feU},
77 {.addr = 0x00407004, .prod = 0x00000000, .disable = 0x000001fe}, 73 {.addr = 0x00407004U, .prod = 0x00000000U, .disable = 0x000001feU},
78 {.addr = 0x0041a17c, .prod = 0x00020008, .disable = 0x0003fffe}, 74 {.addr = 0x0041a17cU, .prod = 0x00020008U, .disable = 0x0003fffeU},
79 {.addr = 0x0041a894, .prod = 0x00000040, .disable = 0x03fffffe}, 75 {.addr = 0x0041a894U, .prod = 0x00000040U, .disable = 0x03fffffeU},
80 {.addr = 0x00418504, .prod = 0x00000000, .disable = 0x0007fffe}, 76 {.addr = 0x00418504U, .prod = 0x00000000U, .disable = 0x0007fffeU},
81 {.addr = 0x0041860c, .prod = 0x00000000, .disable = 0x000001fe}, 77 {.addr = 0x0041860cU, .prod = 0x00000000U, .disable = 0x000001feU},
82 {.addr = 0x0041868c, .prod = 0x00000000, .disable = 0x0000001e}, 78 {.addr = 0x0041868cU, .prod = 0x00000000U, .disable = 0x0000001eU},
83 {.addr = 0x0041871c, .prod = 0x00000000, .disable = 0x000003fe}, 79 {.addr = 0x0041871cU, .prod = 0x00000000U, .disable = 0x0000003eU},
84 {.addr = 0x00418388, .prod = 0x00000000, .disable = 0x00000001}, 80 {.addr = 0x00418388U, .prod = 0x00000000U, .disable = 0x00000001U},
85 {.addr = 0x0041882c, .prod = 0x00000000, .disable = 0x0001fffe}, 81 {.addr = 0x0041882cU, .prod = 0x00000000U, .disable = 0x0001fffeU},
86 {.addr = 0x00418bc0, .prod = 0x00000000, .disable = 0x000001fe}, 82 {.addr = 0x00418bc0U, .prod = 0x00000000U, .disable = 0x000001feU},
87 {.addr = 0x00418974, .prod = 0x00000000, .disable = 0x0001fffe}, 83 {.addr = 0x00418974U, .prod = 0x00000000U, .disable = 0x0001fffeU},
88 {.addr = 0x00418c74, .prod = 0xffffff80, .disable = 0xfffffffe}, 84 {.addr = 0x00418c74U, .prod = 0xffffffc0U, .disable = 0xfffffffeU},
89 {.addr = 0x00418cf4, .prod = 0xfffffff8, .disable = 0xfffffffe}, 85 {.addr = 0x00418cf4U, .prod = 0xfffffffcU, .disable = 0xfffffffeU},
90 {.addr = 0x00418d74, .prod = 0xffffffe0, .disable = 0xfffffffe}, 86 {.addr = 0x00418d74U, .prod = 0xffffffe0U, .disable = 0xfffffffeU},
91 {.addr = 0x00418f10, .prod = 0xffffffe0, .disable = 0xfffffffe}, 87 {.addr = 0x00418f10U, .prod = 0xffffffe0U, .disable = 0xfffffffeU},
92 {.addr = 0x00418e10, .prod = 0xfffffffe, .disable = 0xfffffffe}, 88 {.addr = 0x00418e10U, .prod = 0xfffffffeU, .disable = 0xfffffffeU},
93 {.addr = 0x00419024, .prod = 0x000001fe, .disable = 0x000001fe}, 89 {.addr = 0x00419024U, .prod = 0x000001feU, .disable = 0x000001feU},
94 {.addr = 0x0041889c, .prod = 0x00000000, .disable = 0x000001fe}, 90 {.addr = 0x0041889cU, .prod = 0x00000000U, .disable = 0x000001feU},
95 {.addr = 0x00419d24, .prod = 0x00000000, .disable = 0x0000ffff}, 91 {.addr = 0x00419d24U, .prod = 0x00000000U, .disable = 0x0000ffffU},
96 {.addr = 0x00419a44, .prod = 0x00000000, .disable = 0x0000000e}, 92 {.addr = 0x00419a44U, .prod = 0x00000000U, .disable = 0x0000000eU},
97 {.addr = 0x00419a4c, .prod = 0x00000000, .disable = 0x000001fe}, 93 {.addr = 0x00419a4cU, .prod = 0x00000000U, .disable = 0x000001feU},
98 {.addr = 0x00419a54, .prod = 0x00000000, .disable = 0x0000003e}, 94 {.addr = 0x00419a54U, .prod = 0x00000000U, .disable = 0x0000003eU},
99 {.addr = 0x00419a5c, .prod = 0x00000000, .disable = 0x0000000e}, 95 {.addr = 0x00419a5cU, .prod = 0x00000000U, .disable = 0x0000000eU},
100 {.addr = 0x00419a64, .prod = 0x00000000, .disable = 0x000001fe}, 96 {.addr = 0x00419a64U, .prod = 0x00000000U, .disable = 0x000001feU},
101 {.addr = 0x00419a6c, .prod = 0x00000000, .disable = 0x0000000e}, 97 {.addr = 0x00419a6cU, .prod = 0x00000000U, .disable = 0x0000000eU},
102 {.addr = 0x00419a74, .prod = 0x00000000, .disable = 0x0000000e}, 98 {.addr = 0x00419a74U, .prod = 0x00000000U, .disable = 0x0000000eU},
103 {.addr = 0x00419a7c, .prod = 0x00000000, .disable = 0x0000003e}, 99 {.addr = 0x00419a7cU, .prod = 0x00000000U, .disable = 0x0000003eU},
104 {.addr = 0x00419a84, .prod = 0x00000000, .disable = 0x0000000e}, 100 {.addr = 0x00419a84U, .prod = 0x00000000U, .disable = 0x0000000eU},
105 {.addr = 0x0041986c, .prod = 0x00000104, .disable = 0x00fffffe}, 101 {.addr = 0x0041986cU, .prod = 0x00000104U, .disable = 0x00fffffeU},
106 {.addr = 0x00419cd8, .prod = 0x00000000, .disable = 0x001ffffe}, 102 {.addr = 0x00419cd8U, .prod = 0x00000000U, .disable = 0x001ffffeU},
107 {.addr = 0x00419ce0, .prod = 0x00000000, .disable = 0x001ffffe}, 103 {.addr = 0x00419ce0U, .prod = 0x00000000U, .disable = 0x001ffffeU},
108 {.addr = 0x00419c74, .prod = 0x0000001e, .disable = 0x0000001e}, 104 {.addr = 0x00419c74U, .prod = 0x0000001eU, .disable = 0x0000001eU},
109 {.addr = 0x00419fd4, .prod = 0x00000000, .disable = 0x0003fffe}, 105 {.addr = 0x00419fd4U, .prod = 0x00000000U, .disable = 0x0003fffeU},
110 {.addr = 0x00419fdc, .prod = 0xffedff00, .disable = 0xfffffffe}, 106 {.addr = 0x00419fdcU, .prod = 0xffedff00U, .disable = 0xfffffffeU},
111 {.addr = 0x00419fe4, .prod = 0x00001b00, .disable = 0x00001ffe}, 107 {.addr = 0x00419fe4U, .prod = 0x00001b00U, .disable = 0x00001ffeU},
112 {.addr = 0x00419ff4, .prod = 0x00000000, .disable = 0x00003ffe}, 108 {.addr = 0x00419ff4U, .prod = 0x00000000U, .disable = 0x00003ffeU},
113 {.addr = 0x00419ffc, .prod = 0x00000000, .disable = 0x0001fffe}, 109 {.addr = 0x00419ffcU, .prod = 0x00000000U, .disable = 0x0001fffeU},
114 {.addr = 0x0041be2c, .prod = 0x04115fc0, .disable = 0xfffffffe}, 110 {.addr = 0x0041be2cU, .prod = 0x04115fc0U, .disable = 0xfffffffeU},
115 {.addr = 0x0041bfec, .prod = 0xfffffff0, .disable = 0xfffffffe}, 111 {.addr = 0x0041bfecU, .prod = 0xfffffff0U, .disable = 0xfffffffeU},
116 {.addr = 0x0041bed4, .prod = 0xfffffff8, .disable = 0xfffffffe}, 112 {.addr = 0x0041bed4U, .prod = 0xfffffff8U, .disable = 0xfffffffeU},
117 {.addr = 0x00408814, .prod = 0x00000000, .disable = 0x0001fffe}, 113 {.addr = 0x00408814U, .prod = 0x00000000U, .disable = 0x0001fffeU},
118 {.addr = 0x00408a84, .prod = 0x00000000, .disable = 0x0001fffe}, 114 {.addr = 0x00408a84U, .prod = 0x00000000U, .disable = 0x0001fffeU},
119 {.addr = 0x004089ac, .prod = 0x00000000, .disable = 0x0001fffe}, 115 {.addr = 0x004089acU, .prod = 0x00000000U, .disable = 0x0001fffeU},
120 {.addr = 0x00408a24, .prod = 0x00000000, .disable = 0x0000ffff}, 116 {.addr = 0x00408a24U, .prod = 0x00000000U, .disable = 0x0000ffffU},
121}; 117};
122 118
123/* slcg ltc */ 119/* slcg ltc */
124static const struct gating_desc gp106_slcg_ltc[] = { 120static const struct gating_desc gp106_slcg_ltc[] = {
125 {.addr = 0x0017e050, .prod = 0x00000000, .disable = 0xfffffffe}, 121 {.addr = 0x0017e050U, .prod = 0x00000000U, .disable = 0xfffffffeU},
126 {.addr = 0x0017e35c, .prod = 0x00000000, .disable = 0xfffffffe}, 122 {.addr = 0x0017e35cU, .prod = 0x00000000U, .disable = 0xfffffffeU},
127}; 123};
128 124
129/* slcg perf */ 125/* slcg perf */
130static const struct gating_desc gp106_slcg_perf[] = { 126static const struct gating_desc gp106_slcg_perf[] = {
131 {.addr = 0x001be018, .prod = 0x000001ff, .disable = 0x00000000}, 127 {.addr = 0x001be018U, .prod = 0x000001ffU, .disable = 0x00000000U},
132 {.addr = 0x001bc018, .prod = 0x000001ff, .disable = 0x00000000}, 128 {.addr = 0x001bc018U, .prod = 0x000001ffU, .disable = 0x00000000U},
133 {.addr = 0x001bc218, .prod = 0x000001ff, .disable = 0x00000000}, 129 {.addr = 0x001b8018U, .prod = 0x000001ffU, .disable = 0x00000000U},
134 {.addr = 0x001b8018, .prod = 0x000001ff, .disable = 0x00000000}, 130 {.addr = 0x001b4124U, .prod = 0x00000001U, .disable = 0x00000000U},
135 {.addr = 0x001b8218, .prod = 0x000001ff, .disable = 0x00000000},
136 {.addr = 0x001b4124, .prod = 0x00000001, .disable = 0x00000000},
137}; 131};
138 132
139/* slcg PriRing */ 133/* slcg PriRing */
140static const struct gating_desc gp106_slcg_priring[] = { 134static const struct gating_desc gp106_slcg_priring[] = {
141 {.addr = 0x001200a8, .prod = 0x00000000, .disable = 0x00000001}, 135 {.addr = 0x001200a8U, .prod = 0x00000000U, .disable = 0x00000001U},
142}; 136};
143 137
144/* slcg pmu */ 138/* slcg pmu */
145static const struct gating_desc gp106_slcg_pmu[] = { 139static const struct gating_desc gp106_slcg_pmu[] = {
146 {.addr = 0x0010a134, .prod = 0x00020008, .disable = 0x0003fffe}, 140 {.addr = 0x0010a134U, .prod = 0x00020008U, .disable = 0x0003fffeU},
147 {.addr = 0x0010aa74, .prod = 0x00000000, .disable = 0x00007ffe}, 141 {.addr = 0x0010aa74U, .prod = 0x00004000U, .disable = 0x00007ffeU},
148 {.addr = 0x0010ae74, .prod = 0x00000000, .disable = 0x0000000f}, 142 {.addr = 0x0010ae74U, .prod = 0x00000000U, .disable = 0x0000000fU},
149}; 143};
150 144
151/* therm gr */ 145/* therm gr */
152static const struct gating_desc gp106_slcg_therm[] = { 146static const struct gating_desc gp106_slcg_therm[] = {
153 {.addr = 0x000206b8, .prod = 0x00000000, .disable = 0x0000000f}, 147 {.addr = 0x000206b8U, .prod = 0x00000000U, .disable = 0x0000000fU},
154}; 148};
155 149
156/* slcg Xbar */ 150/* slcg Xbar */
157static const struct gating_desc gp106_slcg_xbar[] = { 151static const struct gating_desc gp106_slcg_xbar[] = {
158 {.addr = 0x0013c824, .prod = 0x00000000, .disable = 0x7ffffffe}, 152 {.addr = 0x0013cbe4U, .prod = 0x00000000U, .disable = 0x1ffffffeU},
159 {.addr = 0x0013dc08, .prod = 0x00000000, .disable = 0xfffffffe}, 153 {.addr = 0x0013cc04U, .prod = 0x00000000U, .disable = 0x1ffffffeU},
160 {.addr = 0x0013c924, .prod = 0x00000000, .disable = 0x7ffffffe},
161 {.addr = 0x0013cbe4, .prod = 0x00000000, .disable = 0x1ffffffe},
162 {.addr = 0x0013cc04, .prod = 0x00000000, .disable = 0x1ffffffe},
163 {.addr = 0x0013cc24, .prod = 0x00000000, .disable = 0x1ffffffe},
164}; 154};
165 155
166/* blcg bus */ 156/* blcg bus */
167static const struct gating_desc gp106_blcg_bus[] = { 157static const struct gating_desc gp106_blcg_bus[] = {
168 {.addr = 0x00001c00, .prod = 0x00000042, .disable = 0x00000000}, 158 {.addr = 0x00001c00U, .prod = 0x00000042U, .disable = 0x00000000U},
169}; 159};
170 160
171/* blcg ce */ 161/* blcg ce */
172static const struct gating_desc gp106_blcg_ce[] = { 162static const struct gating_desc gp106_blcg_ce[] = {
173 {.addr = 0x00104200, .prod = 0x0000c242, .disable = 0x00000000}, 163 {.addr = 0x00104200U, .prod = 0x00008242U, .disable = 0x00000000U},
164};
165
166/* blcg ctxsw prog */
167static const struct gating_desc gp106_blcg_ctxsw_prog[] = {
174}; 168};
175 169
176/* blcg fb */ 170/* blcg fb */
177static const struct gating_desc gp106_blcg_fb[] = { 171static const struct gating_desc gp106_blcg_fb[] = {
178 {.addr = 0x00100d10, .prod = 0x0000c242, .disable = 0x00000000}, 172 {.addr = 0x00100d10U, .prod = 0x0000c242U, .disable = 0x00000000U},
179 {.addr = 0x00100d30, .prod = 0x0000c242, .disable = 0x00000000}, 173 {.addr = 0x00100d30U, .prod = 0x0000c242U, .disable = 0x00000000U},
180 {.addr = 0x00100d3c, .prod = 0x00000242, .disable = 0x00000000}, 174 {.addr = 0x00100d3cU, .prod = 0x00000242U, .disable = 0x00000000U},
181 {.addr = 0x00100d48, .prod = 0x0000c242, .disable = 0x00000000}, 175 {.addr = 0x00100d48U, .prod = 0x0000c242U, .disable = 0x00000000U},
182 {.addr = 0x00100c98, .prod = 0x00004242, .disable = 0x00000000}, 176 /* fix priv error */
177 /*{.addr = 0x00100d1cU, .prod = 0x00000042U, .disable = 0x00000000U},*/
178 {.addr = 0x00100c98U, .prod = 0x00004242U, .disable = 0x00000000U},
183}; 179};
184 180
185/* blcg fifo */ 181/* blcg fifo */
186static const struct gating_desc gp106_blcg_fifo[] = { 182static const struct gating_desc gp106_blcg_fifo[] = {
187 {.addr = 0x000026a4, .prod = 0x0000c242, .disable = 0x00000000}, 183 {.addr = 0x000026a4U, .prod = 0x0000c242U, .disable = 0x00000000U},
188}; 184};
189 185
190/* blcg gr */ 186/* blcg gr */
191static const struct gating_desc gp106_blcg_gr[] = { 187static const struct gating_desc gp106_blcg_gr[] = {
192 {.addr = 0x004041f0, .prod = 0x0000c646, .disable = 0x00000000}, 188 {.addr = 0x004041f0U, .prod = 0x0000c646U, .disable = 0x00000000U},
193 {.addr = 0x00409890, .prod = 0x0000007f, .disable = 0x00000000}, 189 {.addr = 0x00409890U, .prod = 0x0000007fU, .disable = 0x00000000U},
194 {.addr = 0x004098b0, .prod = 0x0000007f, .disable = 0x00000000}, 190 {.addr = 0x004098b0U, .prod = 0x0000007fU, .disable = 0x00000000U},
195 {.addr = 0x004078c0, .prod = 0x00004242, .disable = 0x00000000}, 191 {.addr = 0x004078c0U, .prod = 0x00004242U, .disable = 0x00000000U},
196 {.addr = 0x00406000, .prod = 0x0000c444, .disable = 0x00000000}, 192 {.addr = 0x00406000U, .prod = 0x0000c444U, .disable = 0x00000000U},
197 {.addr = 0x00405860, .prod = 0x0000c242, .disable = 0x00000000}, 193 {.addr = 0x00405860U, .prod = 0x0000c242U, .disable = 0x00000000U},
198 {.addr = 0x0040590c, .prod = 0x0000c444, .disable = 0x00000000}, 194 {.addr = 0x0040590cU, .prod = 0x0000c444U, .disable = 0x00000000U},
199 {.addr = 0x00408040, .prod = 0x0000c444, .disable = 0x00000000}, 195 {.addr = 0x00408040U, .prod = 0x0000c444U, .disable = 0x00000000U},
200 {.addr = 0x00407000, .prod = 0x4000c242, .disable = 0x00000000}, 196 {.addr = 0x00407000U, .prod = 0x4000c242U, .disable = 0x00000000U},
201 {.addr = 0x00405bf0, .prod = 0x0000c444, .disable = 0x00000000}, 197 {.addr = 0x00405bf0U, .prod = 0x0000c444U, .disable = 0x00000000U},
202 {.addr = 0x0041a890, .prod = 0x0000427f, .disable = 0x00000000}, 198 {.addr = 0x0041a890U, .prod = 0x0000427fU, .disable = 0x00000000U},
203 {.addr = 0x0041a8b0, .prod = 0x0000007f, .disable = 0x00000000}, 199 {.addr = 0x0041a8b0U, .prod = 0x0000007fU, .disable = 0x00000000U},
204 {.addr = 0x00418500, .prod = 0x0000c244, .disable = 0x00000000}, 200 {.addr = 0x00418500U, .prod = 0x0000c244U, .disable = 0x00000000U},
205 {.addr = 0x00418608, .prod = 0x0000c242, .disable = 0x00000000}, 201 {.addr = 0x00418608U, .prod = 0x0000c242U, .disable = 0x00000000U},
206 {.addr = 0x00418688, .prod = 0x0000c242, .disable = 0x00000000}, 202 {.addr = 0x00418688U, .prod = 0x0000c242U, .disable = 0x00000000U},
207 {.addr = 0x00418718, .prod = 0x00000042, .disable = 0x00000000}, 203 {.addr = 0x00418718U, .prod = 0x00000042U, .disable = 0x00000000U},
208 {.addr = 0x00418828, .prod = 0x00008444, .disable = 0x00000000}, 204 {.addr = 0x00418828U, .prod = 0x00008444U, .disable = 0x00000000U},
209 {.addr = 0x00418bbc, .prod = 0x0000c242, .disable = 0x00000000}, 205 {.addr = 0x00418bbcU, .prod = 0x0000c242U, .disable = 0x00000000U},
210 {.addr = 0x00418970, .prod = 0x0000c242, .disable = 0x00000000}, 206 {.addr = 0x00418970U, .prod = 0x0000c242U, .disable = 0x00000000U},
211 {.addr = 0x00418c70, .prod = 0x0000c444, .disable = 0x00000000}, 207 {.addr = 0x00418c70U, .prod = 0x0000c444U, .disable = 0x00000000U},
212 {.addr = 0x00418cf0, .prod = 0x0000c444, .disable = 0x00000000}, 208 {.addr = 0x00418cf0U, .prod = 0x0000c444U, .disable = 0x00000000U},
213 {.addr = 0x00418d70, .prod = 0x0000c444, .disable = 0x00000000}, 209 {.addr = 0x00418d70U, .prod = 0x0000c444U, .disable = 0x00000000U},
214 {.addr = 0x00418f0c, .prod = 0x0000c444, .disable = 0x00000000}, 210 {.addr = 0x00418f0cU, .prod = 0x0000c444U, .disable = 0x00000000U},
215 {.addr = 0x00418e0c, .prod = 0x00008444, .disable = 0x00000000}, 211 {.addr = 0x00418e0cU, .prod = 0x00008444U, .disable = 0x00000000U},
216 {.addr = 0x00419020, .prod = 0x0000c242, .disable = 0x00000000}, 212 {.addr = 0x00419020U, .prod = 0x0000c242U, .disable = 0x00000000U},
217 {.addr = 0x00419038, .prod = 0x00000042, .disable = 0x00000000}, 213 {.addr = 0x00419038U, .prod = 0x00000042U, .disable = 0x00000000U},
218 {.addr = 0x00418898, .prod = 0x00004242, .disable = 0x00000000}, 214 {.addr = 0x00418898U, .prod = 0x00004242U, .disable = 0x00000000U},
219 {.addr = 0x00419a40, .prod = 0x0000c242, .disable = 0x00000000}, 215 {.addr = 0x00419a40U, .prod = 0x0000c242U, .disable = 0x00000000U},
220 {.addr = 0x00419a48, .prod = 0x0000c242, .disable = 0x00000000}, 216 {.addr = 0x00419a48U, .prod = 0x0000c242U, .disable = 0x00000000U},
221 {.addr = 0x00419a50, .prod = 0x0000c242, .disable = 0x00000000}, 217 {.addr = 0x00419a50U, .prod = 0x0000c242U, .disable = 0x00000000U},
222 {.addr = 0x00419a58, .prod = 0x0000c242, .disable = 0x00000000}, 218 {.addr = 0x00419a58U, .prod = 0x0000c242U, .disable = 0x00000000U},
223 {.addr = 0x00419a60, .prod = 0x0000c242, .disable = 0x00000000}, 219 {.addr = 0x00419a60U, .prod = 0x0000c242U, .disable = 0x00000000U},
224 {.addr = 0x00419a68, .prod = 0x0000c242, .disable = 0x00000000}, 220 {.addr = 0x00419a68U, .prod = 0x0000c242U, .disable = 0x00000000U},
225 {.addr = 0x00419a70, .prod = 0x0000c242, .disable = 0x00000000}, 221 {.addr = 0x00419a70U, .prod = 0x0000c242U, .disable = 0x00000000U},
226 {.addr = 0x00419a78, .prod = 0x0000c242, .disable = 0x00000000}, 222 {.addr = 0x00419a78U, .prod = 0x0000c242U, .disable = 0x00000000U},
227 {.addr = 0x00419a80, .prod = 0x0000c242, .disable = 0x00000000}, 223 {.addr = 0x00419a80U, .prod = 0x0000c242U, .disable = 0x00000000U},
228 {.addr = 0x00419868, .prod = 0x00008242, .disable = 0x00000000}, 224 {.addr = 0x00419868U, .prod = 0x00008242U, .disable = 0x00000000U},
229 {.addr = 0x00419cd4, .prod = 0x00000002, .disable = 0x00000000}, 225 {.addr = 0x00419cd4U, .prod = 0x00000002U, .disable = 0x00000000U},
230 {.addr = 0x00419cdc, .prod = 0x00000002, .disable = 0x00000000}, 226 {.addr = 0x00419cdcU, .prod = 0x00000002U, .disable = 0x00000000U},
231 {.addr = 0x00419c70, .prod = 0x0000c444, .disable = 0x00000000}, 227 {.addr = 0x00419c70U, .prod = 0x0000c444U, .disable = 0x00000000U},
232 {.addr = 0x00419fd0, .prod = 0x0000c044, .disable = 0x00000000}, 228 {.addr = 0x00419fd0U, .prod = 0x0000c044U, .disable = 0x00000000U},
233 {.addr = 0x00419fd8, .prod = 0x0000c046, .disable = 0x00000000}, 229 {.addr = 0x00419fd8U, .prod = 0x0000c046U, .disable = 0x00000000U},
234 {.addr = 0x00419fe0, .prod = 0x0000c044, .disable = 0x00000000}, 230 {.addr = 0x00419fe0U, .prod = 0x0000c044U, .disable = 0x00000000U},
235 {.addr = 0x00419fe8, .prod = 0x0000c042, .disable = 0x00000000}, 231 {.addr = 0x00419fe8U, .prod = 0x0000c042U, .disable = 0x00000000U},
236 {.addr = 0x00419ff0, .prod = 0x0000c045, .disable = 0x00000000}, 232 {.addr = 0x00419ff0U, .prod = 0x0000c045U, .disable = 0x00000000U},
237 {.addr = 0x00419ff8, .prod = 0x00000002, .disable = 0x00000000}, 233 {.addr = 0x00419ff8U, .prod = 0x00000002U, .disable = 0x00000000U},
238 {.addr = 0x00419f90, .prod = 0x00000002, .disable = 0x00000000}, 234 {.addr = 0x00419f90U, .prod = 0x00000002U, .disable = 0x00000000U},
239 {.addr = 0x0041be28, .prod = 0x00008242, .disable = 0x00000000}, 235 {.addr = 0x0041be28U, .prod = 0x00008242U, .disable = 0x00000000U},
240 {.addr = 0x0041bfe8, .prod = 0x0000c444, .disable = 0x00000000}, 236 {.addr = 0x0041bfe8U, .prod = 0x0000c444U, .disable = 0x00000000U},
241 {.addr = 0x0041bed0, .prod = 0x0000c444, .disable = 0x00000000}, 237 {.addr = 0x0041bed0U, .prod = 0x0000c444U, .disable = 0x00000000U},
242 {.addr = 0x00408810, .prod = 0x0000c242, .disable = 0x00000000}, 238 {.addr = 0x00408810U, .prod = 0x0000c242U, .disable = 0x00000000U},
243 {.addr = 0x00408a80, .prod = 0x0000c242, .disable = 0x00000000}, 239 {.addr = 0x00408a80U, .prod = 0x0000c242U, .disable = 0x00000000U},
244 {.addr = 0x004089a8, .prod = 0x0000c242, .disable = 0x00000000}, 240 {.addr = 0x004089a8U, .prod = 0x0000c242U, .disable = 0x00000000U},
245}; 241};
246 242
247/* blcg ltc */ 243/* blcg ltc */
248static const struct gating_desc gp106_blcg_ltc[] = { 244static const struct gating_desc gp106_blcg_ltc[] = {
249 {.addr = 0x0017e030, .prod = 0x00000044, .disable = 0x00000000}, 245 {.addr = 0x0017e030U, .prod = 0x00000044U, .disable = 0x00000000U},
250 {.addr = 0x0017e040, .prod = 0x00000044, .disable = 0x00000000}, 246 {.addr = 0x0017e040U, .prod = 0x00000044U, .disable = 0x00000000U},
251 {.addr = 0x0017e3e0, .prod = 0x00000044, .disable = 0x00000000}, 247 {.addr = 0x0017e3e0U, .prod = 0x00000044U, .disable = 0x00000000U},
252 {.addr = 0x0017e3c8, .prod = 0x00000044, .disable = 0x00000000}, 248 {.addr = 0x0017e3c8U, .prod = 0x00000044U, .disable = 0x00000000U},
253}; 249};
254 250
255/* blcg pmu */ 251/* blcg pmu */
256static const struct gating_desc gp106_blcg_pmu[] = { 252static const struct gating_desc gp106_blcg_pmu[] = {
257 {.addr = 0x0010aa70, .prod = 0x00000045, .disable = 0x00000000}, 253 {.addr = 0x0010aa70U, .prod = 0x00000045U, .disable = 0x00000000U},
258}; 254};
259 255
260/* blcg Xbar */ 256/* blcg Xbar */
261static const struct gating_desc gp106_blcg_xbar[] = { 257static const struct gating_desc gp106_blcg_xbar[] = {
262 {.addr = 0x0013c820, .prod = 0x0001004a, .disable = 0x00000000}, 258 {.addr = 0x0013cbe0U, .prod = 0x00000042U, .disable = 0x00000000U},
263 {.addr = 0x0013dc04, .prod = 0x0001004a, .disable = 0x00000000}, 259 {.addr = 0x0013cc00U, .prod = 0x00000042U, .disable = 0x00000000U},
264 {.addr = 0x0013c920, .prod = 0x0000004a, .disable = 0x00000000},
265 {.addr = 0x0013cbe0, .prod = 0x00000042, .disable = 0x00000000},
266 {.addr = 0x0013cc00, .prod = 0x00000042, .disable = 0x00000000},
267 {.addr = 0x0013cc20, .prod = 0x00000042, .disable = 0x00000000},
268}; 260};
269 261
270/* pg gr */ 262/* pg gr */
@@ -276,18 +268,15 @@ void gp106_slcg_bus_load_gating_prod(struct gk20a *g,
276 bool prod) 268 bool prod)
277{ 269{
278 u32 i; 270 u32 i;
279 u32 size = sizeof(gp106_slcg_bus) / sizeof(struct gating_desc); 271 u32 size = (u32)(sizeof(gp106_slcg_bus) / GATING_DESC_SIZE);
280 272
281 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) 273 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
282 return; 274 for (i = 0; i < size; i++) {
283 275 u32 reg = gp106_slcg_bus[i].addr;
284 for (i = 0; i < size; i++) { 276 u32 val = prod ? gp106_slcg_bus[i].prod :
285 if (prod) 277 gp106_slcg_bus[i].disable;
286 gk20a_writel(g, gp106_slcg_bus[i].addr, 278 gk20a_writel(g, reg, val);
287 gp106_slcg_bus[i].prod); 279 }
288 else
289 gk20a_writel(g, gp106_slcg_bus[i].addr,
290 gp106_slcg_bus[i].disable);
291 } 280 }
292} 281}
293 282
@@ -295,18 +284,15 @@ void gp106_slcg_ce2_load_gating_prod(struct gk20a *g,
295 bool prod) 284 bool prod)
296{ 285{
297 u32 i; 286 u32 i;
298 u32 size = sizeof(gp106_slcg_ce2) / sizeof(struct gating_desc); 287 u32 size = (u32)(sizeof(gp106_slcg_ce2) / GATING_DESC_SIZE);
299 288
300 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) 289 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
301 return; 290 for (i = 0; i < size; i++) {
302 291 u32 reg = gp106_slcg_ce2[i].addr;
303 for (i = 0; i < size; i++) { 292 u32 val = prod ? gp106_slcg_ce2[i].prod :
304 if (prod) 293 gp106_slcg_ce2[i].disable;
305 gk20a_writel(g, gp106_slcg_ce2[i].addr, 294 gk20a_writel(g, reg, val);
306 gp106_slcg_ce2[i].prod); 295 }
307 else
308 gk20a_writel(g, gp106_slcg_ce2[i].addr,
309 gp106_slcg_ce2[i].disable);
310 } 296 }
311} 297}
312 298
@@ -314,42 +300,38 @@ void gp106_slcg_chiplet_load_gating_prod(struct gk20a *g,
314 bool prod) 300 bool prod)
315{ 301{
316 u32 i; 302 u32 i;
317 u32 size = sizeof(gp106_slcg_chiplet) / sizeof(struct gating_desc); 303 u32 size = (u32)(sizeof(gp106_slcg_chiplet) / GATING_DESC_SIZE);
318 304
319 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) 305 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
320 return; 306 for (i = 0; i < size; i++) {
321 307 u32 reg = gp106_slcg_chiplet[i].addr;
322 for (i = 0; i < size; i++) { 308 u32 val = prod ? gp106_slcg_chiplet[i].prod :
323 if (prod) 309 gp106_slcg_chiplet[i].disable;
324 gk20a_writel(g, gp106_slcg_chiplet[i].addr, 310 gk20a_writel(g, reg, val);
325 gp106_slcg_chiplet[i].prod); 311 }
326 else
327 gk20a_writel(g, gp106_slcg_chiplet[i].addr,
328 gp106_slcg_chiplet[i].disable);
329 } 312 }
330} 313}
331 314
332void gp106_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, 315void gp106_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g,
333 bool prod) 316 bool prod)
334{ 317{
318 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
319 }
335} 320}
336 321
337void gp106_slcg_fb_load_gating_prod(struct gk20a *g, 322void gp106_slcg_fb_load_gating_prod(struct gk20a *g,
338 bool prod) 323 bool prod)
339{ 324{
340 u32 i; 325 u32 i;
341 u32 size = sizeof(gp106_slcg_fb) / sizeof(struct gating_desc); 326 u32 size = (u32)(sizeof(gp106_slcg_fb) / GATING_DESC_SIZE);
342 327
343 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) 328 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
344 return; 329 for (i = 0; i < size; i++) {
345 330 u32 reg = gp106_slcg_fb[i].addr;
346 for (i = 0; i < size; i++) { 331 u32 val = prod ? gp106_slcg_fb[i].prod :
347 if (prod) 332 gp106_slcg_fb[i].disable;
348 gk20a_writel(g, gp106_slcg_fb[i].addr, 333 gk20a_writel(g, reg, val);
349 gp106_slcg_fb[i].prod); 334 }
350 else
351 gk20a_writel(g, gp106_slcg_fb[i].addr,
352 gp106_slcg_fb[i].disable);
353 } 335 }
354} 336}
355 337
@@ -357,18 +339,15 @@ void gp106_slcg_fifo_load_gating_prod(struct gk20a *g,
357 bool prod) 339 bool prod)
358{ 340{
359 u32 i; 341 u32 i;
360 u32 size = sizeof(gp106_slcg_fifo) / sizeof(struct gating_desc); 342 u32 size = (u32)(sizeof(gp106_slcg_fifo) / GATING_DESC_SIZE);
361 343
362 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) 344 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
363 return; 345 for (i = 0; i < size; i++) {
364 346 u32 reg = gp106_slcg_fifo[i].addr;
365 for (i = 0; i < size; i++) { 347 u32 val = prod ? gp106_slcg_fifo[i].prod :
366 if (prod) 348 gp106_slcg_fifo[i].disable;
367 gk20a_writel(g, gp106_slcg_fifo[i].addr, 349 gk20a_writel(g, reg, val);
368 gp106_slcg_fifo[i].prod); 350 }
369 else
370 gk20a_writel(g, gp106_slcg_fifo[i].addr,
371 gp106_slcg_fifo[i].disable);
372 } 351 }
373} 352}
374 353
@@ -376,18 +355,15 @@ void gr_gp106_slcg_gr_load_gating_prod(struct gk20a *g,
376 bool prod) 355 bool prod)
377{ 356{
378 u32 i; 357 u32 i;
379 u32 size = sizeof(gp106_slcg_gr) / sizeof(struct gating_desc); 358 u32 size = (u32)(sizeof(gp106_slcg_gr) / GATING_DESC_SIZE);
380 359
381 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) 360 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
382 return; 361 for (i = 0; i < size; i++) {
383 362 u32 reg = gp106_slcg_gr[i].addr;
384 for (i = 0; i < size; i++) { 363 u32 val = prod ? gp106_slcg_gr[i].prod :
385 if (prod) 364 gp106_slcg_gr[i].disable;
386 gk20a_writel(g, gp106_slcg_gr[i].addr, 365 gk20a_writel(g, reg, val);
387 gp106_slcg_gr[i].prod); 366 }
388 else
389 gk20a_writel(g, gp106_slcg_gr[i].addr,
390 gp106_slcg_gr[i].disable);
391 } 367 }
392} 368}
393 369
@@ -395,18 +371,15 @@ void ltc_gp106_slcg_ltc_load_gating_prod(struct gk20a *g,
395 bool prod) 371 bool prod)
396{ 372{
397 u32 i; 373 u32 i;
398 u32 size = sizeof(gp106_slcg_ltc) / sizeof(struct gating_desc); 374 u32 size = (u32)(sizeof(gp106_slcg_ltc) / GATING_DESC_SIZE);
399
400 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
401 return;
402 375
376 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
403 for (i = 0; i < size; i++) { 377 for (i = 0; i < size; i++) {
404 if (prod) 378 u32 reg = gp106_slcg_ltc[i].addr;
405 gk20a_writel(g, gp106_slcg_ltc[i].addr, 379 u32 val = prod ? gp106_slcg_ltc[i].prod :
406 gp106_slcg_ltc[i].prod); 380 gp106_slcg_ltc[i].disable;
407 else 381 gk20a_writel(g, reg, val);
408 gk20a_writel(g, gp106_slcg_ltc[i].addr, 382 }
409 gp106_slcg_ltc[i].disable);
410 } 383 }
411} 384}
412 385
@@ -414,18 +387,15 @@ void gp106_slcg_perf_load_gating_prod(struct gk20a *g,
414 bool prod) 387 bool prod)
415{ 388{
416 u32 i; 389 u32 i;
417 u32 size = sizeof(gp106_slcg_perf) / sizeof(struct gating_desc); 390 u32 size = (u32)(sizeof(gp106_slcg_perf) / GATING_DESC_SIZE);
418 391
419 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) 392 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
420 return; 393 for (i = 0; i < size; i++) {
421 394 u32 reg = gp106_slcg_perf[i].addr;
422 for (i = 0; i < size; i++) { 395 u32 val = prod ? gp106_slcg_perf[i].prod :
423 if (prod) 396 gp106_slcg_perf[i].disable;
424 gk20a_writel(g, gp106_slcg_perf[i].addr, 397 gk20a_writel(g, reg, val);
425 gp106_slcg_perf[i].prod); 398 }
426 else
427 gk20a_writel(g, gp106_slcg_perf[i].addr,
428 gp106_slcg_perf[i].disable);
429 } 399 }
430} 400}
431 401
@@ -433,18 +403,15 @@ void gp106_slcg_priring_load_gating_prod(struct gk20a *g,
433 bool prod) 403 bool prod)
434{ 404{
435 u32 i; 405 u32 i;
436 u32 size = sizeof(gp106_slcg_priring) / sizeof(struct gating_desc); 406 u32 size = (u32)(sizeof(gp106_slcg_priring) / GATING_DESC_SIZE);
437 407
438 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) 408 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
439 return; 409 for (i = 0; i < size; i++) {
440 410 u32 reg = gp106_slcg_priring[i].addr;
441 for (i = 0; i < size; i++) { 411 u32 val = prod ? gp106_slcg_priring[i].prod :
442 if (prod) 412 gp106_slcg_priring[i].disable;
443 gk20a_writel(g, gp106_slcg_priring[i].addr, 413 gk20a_writel(g, reg, val);
444 gp106_slcg_priring[i].prod); 414 }
445 else
446 gk20a_writel(g, gp106_slcg_priring[i].addr,
447 gp106_slcg_priring[i].disable);
448 } 415 }
449} 416}
450 417
@@ -452,18 +419,15 @@ void gp106_slcg_pmu_load_gating_prod(struct gk20a *g,
452 bool prod) 419 bool prod)
453{ 420{
454 u32 i; 421 u32 i;
455 u32 size = sizeof(gp106_slcg_pmu) / sizeof(struct gating_desc); 422 u32 size = (u32)(sizeof(gp106_slcg_pmu) / GATING_DESC_SIZE);
456 423
457 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) 424 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
458 return; 425 for (i = 0; i < size; i++) {
459 426 u32 reg = gp106_slcg_pmu[i].addr;
460 for (i = 0; i < size; i++) { 427 u32 val = prod ? gp106_slcg_pmu[i].prod :
461 if (prod) 428 gp106_slcg_pmu[i].disable;
462 gk20a_writel(g, gp106_slcg_pmu[i].addr, 429 gk20a_writel(g, reg, val);
463 gp106_slcg_pmu[i].prod); 430 }
464 else
465 gk20a_writel(g, gp106_slcg_pmu[i].addr,
466 gp106_slcg_pmu[i].disable);
467 } 431 }
468} 432}
469 433
@@ -471,18 +435,15 @@ void gp106_slcg_therm_load_gating_prod(struct gk20a *g,
471 bool prod) 435 bool prod)
472{ 436{
473 u32 i; 437 u32 i;
474 u32 size = sizeof(gp106_slcg_therm) / sizeof(struct gating_desc); 438 u32 size = (u32)(sizeof(gp106_slcg_therm) / GATING_DESC_SIZE);
475 439
476 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) 440 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
477 return; 441 for (i = 0; i < size; i++) {
478 442 u32 reg = gp106_slcg_therm[i].addr;
479 for (i = 0; i < size; i++) { 443 u32 val = prod ? gp106_slcg_therm[i].prod :
480 if (prod) 444 gp106_slcg_therm[i].disable;
481 gk20a_writel(g, gp106_slcg_therm[i].addr, 445 gk20a_writel(g, reg, val);
482 gp106_slcg_therm[i].prod); 446 }
483 else
484 gk20a_writel(g, gp106_slcg_therm[i].addr,
485 gp106_slcg_therm[i].disable);
486 } 447 }
487} 448}
488 449
@@ -490,18 +451,15 @@ void gp106_slcg_xbar_load_gating_prod(struct gk20a *g,
490 bool prod) 451 bool prod)
491{ 452{
492 u32 i; 453 u32 i;
493 u32 size = sizeof(gp106_slcg_xbar) / sizeof(struct gating_desc); 454 u32 size = (u32)(sizeof(gp106_slcg_xbar) / GATING_DESC_SIZE);
494 455
495 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) 456 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
496 return; 457 for (i = 0; i < size; i++) {
497 458 u32 reg = gp106_slcg_xbar[i].addr;
498 for (i = 0; i < size; i++) { 459 u32 val = prod ? gp106_slcg_xbar[i].prod :
499 if (prod) 460 gp106_slcg_xbar[i].disable;
500 gk20a_writel(g, gp106_slcg_xbar[i].addr, 461 gk20a_writel(g, reg, val);
501 gp106_slcg_xbar[i].prod); 462 }
502 else
503 gk20a_writel(g, gp106_slcg_xbar[i].addr,
504 gp106_slcg_xbar[i].disable);
505 } 463 }
506} 464}
507 465
@@ -509,18 +467,15 @@ void gp106_blcg_bus_load_gating_prod(struct gk20a *g,
509 bool prod) 467 bool prod)
510{ 468{
511 u32 i; 469 u32 i;
512 u32 size = sizeof(gp106_blcg_bus) / sizeof(struct gating_desc); 470 u32 size = (u32)(sizeof(gp106_blcg_bus) / GATING_DESC_SIZE);
513 471
514 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) 472 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
515 return; 473 for (i = 0; i < size; i++) {
516 474 u32 reg = gp106_blcg_bus[i].addr;
517 for (i = 0; i < size; i++) { 475 u32 val = prod ? gp106_blcg_bus[i].prod :
518 if (prod) 476 gp106_blcg_bus[i].disable;
519 gk20a_writel(g, gp106_blcg_bus[i].addr, 477 gk20a_writel(g, reg, val);
520 gp106_blcg_bus[i].prod); 478 }
521 else
522 gk20a_writel(g, gp106_blcg_bus[i].addr,
523 gp106_blcg_bus[i].disable);
524 } 479 }
525} 480}
526 481
@@ -528,18 +483,31 @@ void gp106_blcg_ce_load_gating_prod(struct gk20a *g,
528 bool prod) 483 bool prod)
529{ 484{
530 u32 i; 485 u32 i;
531 u32 size = sizeof(gp106_blcg_ce) / sizeof(struct gating_desc); 486 u32 size = (u32)(sizeof(gp106_blcg_ce) / GATING_DESC_SIZE);
532 487
533 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) 488 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
534 return; 489 for (i = 0; i < size; i++) {
490 u32 reg = gp106_blcg_ce[i].addr;
491 u32 val = prod ? gp106_blcg_ce[i].prod :
492 gp106_blcg_ce[i].disable;
493 gk20a_writel(g, reg, val);
494 }
495 }
496}
535 497
536 for (i = 0; i < size; i++) { 498void gp106_blcg_ctxsw_firmware_load_gating_prod(struct gk20a *g,
537 if (prod) 499 bool prod)
538 gk20a_writel(g, gp106_blcg_ce[i].addr, 500{
539 gp106_blcg_ce[i].prod); 501 u32 i;
540 else 502 u32 size = (u32)(sizeof(gp106_blcg_ctxsw_prog) / GATING_DESC_SIZE);
541 gk20a_writel(g, gp106_blcg_ce[i].addr, 503
542 gp106_blcg_ce[i].disable); 504 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
505 for (i = 0; i < size; i++) {
506 u32 reg = gp106_blcg_ctxsw_prog[i].addr;
507 u32 val = prod ? gp106_blcg_ctxsw_prog[i].prod :
508 gp106_blcg_ctxsw_prog[i].disable;
509 gk20a_writel(g, reg, val);
510 }
543 } 511 }
544} 512}
545 513
@@ -547,18 +515,15 @@ void gp106_blcg_fb_load_gating_prod(struct gk20a *g,
547 bool prod) 515 bool prod)
548{ 516{
549 u32 i; 517 u32 i;
550 u32 size = sizeof(gp106_blcg_fb) / sizeof(struct gating_desc); 518 u32 size = (u32)(sizeof(gp106_blcg_fb) / GATING_DESC_SIZE);
551 519
552 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) 520 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
553 return; 521 for (i = 0; i < size; i++) {
554 522 u32 reg = gp106_blcg_fb[i].addr;
555 for (i = 0; i < size; i++) { 523 u32 val = prod ? gp106_blcg_fb[i].prod :
556 if (prod) 524 gp106_blcg_fb[i].disable;
557 gk20a_writel(g, gp106_blcg_fb[i].addr, 525 gk20a_writel(g, reg, val);
558 gp106_blcg_fb[i].prod); 526 }
559 else
560 gk20a_writel(g, gp106_blcg_fb[i].addr,
561 gp106_blcg_fb[i].disable);
562 } 527 }
563} 528}
564 529
@@ -566,18 +531,15 @@ void gp106_blcg_fifo_load_gating_prod(struct gk20a *g,
566 bool prod) 531 bool prod)
567{ 532{
568 u32 i; 533 u32 i;
569 u32 size = sizeof(gp106_blcg_fifo) / sizeof(struct gating_desc); 534 u32 size = (u32)(sizeof(gp106_blcg_fifo) / GATING_DESC_SIZE);
570
571 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
572 return;
573 535
536 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
574 for (i = 0; i < size; i++) { 537 for (i = 0; i < size; i++) {
575 if (prod) 538 u32 reg = gp106_blcg_fifo[i].addr;
576 gk20a_writel(g, gp106_blcg_fifo[i].addr, 539 u32 val = prod ? gp106_blcg_fifo[i].prod :
577 gp106_blcg_fifo[i].prod); 540 gp106_blcg_fifo[i].disable;
578 else 541 gk20a_writel(g, reg, val);
579 gk20a_writel(g, gp106_blcg_fifo[i].addr, 542 }
580 gp106_blcg_fifo[i].disable);
581 } 543 }
582} 544}
583 545
@@ -585,18 +547,15 @@ void gp106_blcg_gr_load_gating_prod(struct gk20a *g,
585 bool prod) 547 bool prod)
586{ 548{
587 u32 i; 549 u32 i;
588 u32 size = sizeof(gp106_blcg_gr) / sizeof(struct gating_desc); 550 u32 size = (u32)(sizeof(gp106_blcg_gr) / GATING_DESC_SIZE);
589 551
590 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) 552 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
591 return; 553 for (i = 0; i < size; i++) {
592 554 u32 reg = gp106_blcg_gr[i].addr;
593 for (i = 0; i < size; i++) { 555 u32 val = prod ? gp106_blcg_gr[i].prod :
594 if (prod) 556 gp106_blcg_gr[i].disable;
595 gk20a_writel(g, gp106_blcg_gr[i].addr, 557 gk20a_writel(g, reg, val);
596 gp106_blcg_gr[i].prod); 558 }
597 else
598 gk20a_writel(g, gp106_blcg_gr[i].addr,
599 gp106_blcg_gr[i].disable);
600 } 559 }
601} 560}
602 561
@@ -604,18 +563,15 @@ void gp106_blcg_ltc_load_gating_prod(struct gk20a *g,
604 bool prod) 563 bool prod)
605{ 564{
606 u32 i; 565 u32 i;
607 u32 size = sizeof(gp106_blcg_ltc) / sizeof(struct gating_desc); 566 u32 size = (u32)(sizeof(gp106_blcg_ltc) / GATING_DESC_SIZE);
608 567
609 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) 568 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
610 return; 569 for (i = 0; i < size; i++) {
611 570 u32 reg = gp106_blcg_ltc[i].addr;
612 for (i = 0; i < size; i++) { 571 u32 val = prod ? gp106_blcg_ltc[i].prod :
613 if (prod) 572 gp106_blcg_ltc[i].disable;
614 gk20a_writel(g, gp106_blcg_ltc[i].addr, 573 gk20a_writel(g, reg, val);
615 gp106_blcg_ltc[i].prod); 574 }
616 else
617 gk20a_writel(g, gp106_blcg_ltc[i].addr,
618 gp106_blcg_ltc[i].disable);
619 } 575 }
620} 576}
621 577
@@ -623,18 +579,15 @@ void gp106_blcg_pmu_load_gating_prod(struct gk20a *g,
623 bool prod) 579 bool prod)
624{ 580{
625 u32 i; 581 u32 i;
626 u32 size = sizeof(gp106_blcg_pmu) / sizeof(struct gating_desc); 582 u32 size = (u32)(sizeof(gp106_blcg_pmu) / GATING_DESC_SIZE);
627 583
628 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) 584 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
629 return; 585 for (i = 0; i < size; i++) {
630 586 u32 reg = gp106_blcg_pmu[i].addr;
631 for (i = 0; i < size; i++) { 587 u32 val = prod ? gp106_blcg_pmu[i].prod :
632 if (prod) 588 gp106_blcg_pmu[i].disable;
633 gk20a_writel(g, gp106_blcg_pmu[i].addr, 589 gk20a_writel(g, reg, val);
634 gp106_blcg_pmu[i].prod); 590 }
635 else
636 gk20a_writel(g, gp106_blcg_pmu[i].addr,
637 gp106_blcg_pmu[i].disable);
638 } 591 }
639} 592}
640 593
@@ -642,18 +595,15 @@ void gp106_blcg_xbar_load_gating_prod(struct gk20a *g,
642 bool prod) 595 bool prod)
643{ 596{
644 u32 i; 597 u32 i;
645 u32 size = sizeof(gp106_blcg_xbar) / sizeof(struct gating_desc); 598 u32 size = (u32)(sizeof(gp106_blcg_xbar) / GATING_DESC_SIZE);
646 599
647 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) 600 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
648 return; 601 for (i = 0; i < size; i++) {
649 602 u32 reg = gp106_blcg_xbar[i].addr;
650 for (i = 0; i < size; i++) { 603 u32 val = prod ? gp106_blcg_xbar[i].prod :
651 if (prod) 604 gp106_blcg_xbar[i].disable;
652 gk20a_writel(g, gp106_blcg_xbar[i].addr, 605 gk20a_writel(g, reg, val);
653 gp106_blcg_xbar[i].prod); 606 }
654 else
655 gk20a_writel(g, gp106_blcg_xbar[i].addr,
656 gp106_blcg_xbar[i].disable);
657 } 607 }
658} 608}
659 609
@@ -661,19 +611,14 @@ void gr_gp106_pg_gr_load_gating_prod(struct gk20a *g,
661 bool prod) 611 bool prod)
662{ 612{
663 u32 i; 613 u32 i;
664 u32 size = sizeof(gp106_pg_gr) / sizeof(struct gating_desc); 614 u32 size = (u32)(sizeof(gp106_pg_gr) / GATING_DESC_SIZE);
665 615
666 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) 616 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
667 return; 617 for (i = 0; i < size; i++) {
668 618 u32 reg = gp106_pg_gr[i].addr;
669 for (i = 0; i < size; i++) { 619 u32 val = prod ? gp106_pg_gr[i].prod :
670 if (prod) 620 gp106_pg_gr[i].disable;
671 gk20a_writel(g, gp106_pg_gr[i].addr, 621 gk20a_writel(g, reg, val);
672 gp106_pg_gr[i].prod); 622 }
673 else
674 gk20a_writel(g, gp106_pg_gr[i].addr,
675 gp106_pg_gr[i].disable);
676 } 623 }
677} 624}
678
679#endif /* __gp106_gating_reglist_h__ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-07 13:35:52 -0400