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Diffstat (limited to 'drivers/gpu/nvgpu/common/clock_gating/gm20b_gating_reglist.c')
-rw-r--r--drivers/gpu/nvgpu/common/clock_gating/gm20b_gating_reglist.c817
1 files changed, 374 insertions, 443 deletions
diff --git a/drivers/gpu/nvgpu/common/clock_gating/gm20b_gating_reglist.c b/drivers/gpu/nvgpu/common/clock_gating/gm20b_gating_reglist.c
index 0ebb2d0d..4caa343e 100644
--- a/drivers/gpu/nvgpu/common/clock_gating/gm20b_gating_reglist.c
+++ b/drivers/gpu/nvgpu/common/clock_gating/gm20b_gating_reglist.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a 4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"), 5 * copy of this software and associated documentation files (the "Software"),
@@ -22,156 +22,154 @@
22 * This file is autogenerated. Do not edit. 22 * This file is autogenerated. Do not edit.
23 */ 23 */
24 24
25#ifndef __gm20b_gating_reglist_h__ 25#include <nvgpu/types.h>
26#define __gm20b_gating_reglist_h__ 26#include <nvgpu/io.h>
27#include <nvgpu/enabled.h>
27 28
29#include "gating_reglist.h"
28#include "gm20b_gating_reglist.h" 30#include "gm20b_gating_reglist.h"
29#include <nvgpu/enabled.h>
30 31
31struct gating_desc { 32#define GATING_DESC_SIZE (u32)(sizeof(struct gating_desc))
32 u32 addr; 33
33 u32 prod;
34 u32 disable;
35};
36/* slcg bus */ 34/* slcg bus */
37static const struct gating_desc gm20b_slcg_bus[] = { 35static const struct gating_desc gm20b_slcg_bus[] = {
38 {.addr = 0x00001c04, .prod = 0x00000000, .disable = 0x000003fe}, 36 {.addr = 0x00001c04U, .prod = 0x00000000U, .disable = 0x000003feU},
39}; 37};
40 38
41/* slcg ce2 */ 39/* slcg ce2 */
42static const struct gating_desc gm20b_slcg_ce2[] = { 40static const struct gating_desc gm20b_slcg_ce2[] = {
43 {.addr = 0x00106f28, .prod = 0x00000000, .disable = 0x000007fe}, 41 {.addr = 0x00106f28U, .prod = 0x00000000U, .disable = 0x000007feU},
44}; 42};
45 43
46/* slcg chiplet */ 44/* slcg chiplet */
47static const struct gating_desc gm20b_slcg_chiplet[] = { 45static const struct gating_desc gm20b_slcg_chiplet[] = {
48 {.addr = 0x0010c07c, .prod = 0x00000000, .disable = 0x00000007}, 46 {.addr = 0x0010c07cU, .prod = 0x00000000U, .disable = 0x00000007U},
49 {.addr = 0x0010e07c, .prod = 0x00000000, .disable = 0x00000007}, 47 {.addr = 0x0010e07cU, .prod = 0x00000000U, .disable = 0x00000007U},
50 {.addr = 0x0010d07c, .prod = 0x00000000, .disable = 0x00000007}, 48 {.addr = 0x0010d07cU, .prod = 0x00000000U, .disable = 0x00000007U},
51 {.addr = 0x0010e17c, .prod = 0x00000000, .disable = 0x00000007}, 49 {.addr = 0x0010e17cU, .prod = 0x00000000U, .disable = 0x00000007U},
52}; 50};
53 51
54/* slcg fb */ 52/* slcg fb */
55static const struct gating_desc gm20b_slcg_fb[] = { 53static const struct gating_desc gm20b_slcg_fb[] = {
56 {.addr = 0x00100d14, .prod = 0x00000000, .disable = 0xfffffffe}, 54 {.addr = 0x00100d14U, .prod = 0x00000000U, .disable = 0xfffffffeU},
57 {.addr = 0x00100c9c, .prod = 0x00000000, .disable = 0x000001fe}, 55 {.addr = 0x00100c9cU, .prod = 0x00000000U, .disable = 0x000001feU},
58}; 56};
59 57
60/* slcg fifo */ 58/* slcg fifo */
61static const struct gating_desc gm20b_slcg_fifo[] = { 59static const struct gating_desc gm20b_slcg_fifo[] = {
62 {.addr = 0x000026ac, .prod = 0x00000100, .disable = 0x0001fffe}, 60 {.addr = 0x000026acU, .prod = 0x00000100U, .disable = 0x0001fffeU},
63}; 61};
64 62
65/* slcg gr */ 63/* slcg gr */
66static const struct gating_desc gm20b_slcg_gr[] = { 64static const struct gating_desc gm20b_slcg_gr[] = {
67 {.addr = 0x004041f4, .prod = 0x00000002, .disable = 0x03fffffe}, 65 {.addr = 0x004041f4U, .prod = 0x00000000U, .disable = 0x03fffffeU},
68 {.addr = 0x0040917c, .prod = 0x00020008, .disable = 0x0003fffe}, 66 {.addr = 0x0040917cU, .prod = 0x00020008U, .disable = 0x0003fffeU},
69 {.addr = 0x00409894, .prod = 0x00000040, .disable = 0x0003fffe}, 67 {.addr = 0x00409894U, .prod = 0x00000040U, .disable = 0x0003fffeU},
70 {.addr = 0x004078c4, .prod = 0x00000000, .disable = 0x000001fe}, 68 {.addr = 0x004078c4U, .prod = 0x00000000U, .disable = 0x000001feU},
71 {.addr = 0x00406004, .prod = 0x00000000, .disable = 0x0001fffe}, 69 {.addr = 0x00406004U, .prod = 0x00000000U, .disable = 0x0001fffeU},
72 {.addr = 0x00405864, .prod = 0x00000000, .disable = 0x000001fe}, 70 {.addr = 0x00405864U, .prod = 0x00000000U, .disable = 0x000001feU},
73 {.addr = 0x00405910, .prod = 0xfffffff0, .disable = 0xfffffffe}, 71 {.addr = 0x00405910U, .prod = 0xfffffff0U, .disable = 0xfffffffeU},
74 {.addr = 0x00408044, .prod = 0x00000000, .disable = 0x000007fe}, 72 {.addr = 0x00408044U, .prod = 0x00000000U, .disable = 0x000007feU},
75 {.addr = 0x00407004, .prod = 0x00000000, .disable = 0x0000007e}, 73 {.addr = 0x00407004U, .prod = 0x00000000U, .disable = 0x0000007eU},
76 {.addr = 0x0041a17c, .prod = 0x00020008, .disable = 0x0003fffe}, 74 {.addr = 0x0041a17cU, .prod = 0x00020008U, .disable = 0x0003fffeU},
77 {.addr = 0x0041a894, .prod = 0x00000040, .disable = 0x0003fffe}, 75 {.addr = 0x0041a894U, .prod = 0x00000040U, .disable = 0x0003fffeU},
78 {.addr = 0x00418504, .prod = 0x00000000, .disable = 0x0007fffe}, 76 {.addr = 0x00418504U, .prod = 0x00000000U, .disable = 0x0007fffeU},
79 {.addr = 0x0041860c, .prod = 0x00000000, .disable = 0x000001fe}, 77 {.addr = 0x0041860cU, .prod = 0x00000000U, .disable = 0x000001feU},
80 {.addr = 0x0041868c, .prod = 0x00000000, .disable = 0x0000001e}, 78 {.addr = 0x0041868cU, .prod = 0x00000000U, .disable = 0x0000001eU},
81 {.addr = 0x0041871c, .prod = 0x00000000, .disable = 0x0000003e}, 79 {.addr = 0x0041871cU, .prod = 0x00000000U, .disable = 0x0000003eU},
82 {.addr = 0x00418388, .prod = 0x00000000, .disable = 0x00000001}, 80 {.addr = 0x00418388U, .prod = 0x00000000U, .disable = 0x00000001U},
83 {.addr = 0x0041882c, .prod = 0x00000000, .disable = 0x0001fffe}, 81 {.addr = 0x0041882cU, .prod = 0x00000000U, .disable = 0x0001fffeU},
84 {.addr = 0x00418bc0, .prod = 0x00000000, .disable = 0x000001fe}, 82 {.addr = 0x00418bc0U, .prod = 0x00000000U, .disable = 0x000001feU},
85 {.addr = 0x00418974, .prod = 0x00000000, .disable = 0x0001fffe}, 83 {.addr = 0x00418974U, .prod = 0x00000000U, .disable = 0x0001fffeU},
86 {.addr = 0x00418c74, .prod = 0xffffffc0, .disable = 0xfffffffe}, 84 {.addr = 0x00418c74U, .prod = 0xffffffc0U, .disable = 0xfffffffeU},
87 {.addr = 0x00418cf4, .prod = 0xfffffffc, .disable = 0xfffffffe}, 85 {.addr = 0x00418cf4U, .prod = 0xfffffffcU, .disable = 0xfffffffeU},
88 {.addr = 0x00418d74, .prod = 0xffffffe0, .disable = 0xfffffffe}, 86 {.addr = 0x00418d74U, .prod = 0xffffffe0U, .disable = 0xfffffffeU},
89 {.addr = 0x00418f10, .prod = 0xffffffe0, .disable = 0xfffffffe}, 87 {.addr = 0x00418f10U, .prod = 0xffffffe0U, .disable = 0xfffffffeU},
90 {.addr = 0x00418e10, .prod = 0xfffffffe, .disable = 0xfffffffe}, 88 {.addr = 0x00418e10U, .prod = 0xfffffffeU, .disable = 0xfffffffeU},
91 {.addr = 0x00419024, .prod = 0x000001fe, .disable = 0x000001fe}, 89 {.addr = 0x00419024U, .prod = 0x000001feU, .disable = 0x000001feU},
92 {.addr = 0x0041889c, .prod = 0x00000000, .disable = 0x000001fe}, 90 {.addr = 0x0041889cU, .prod = 0x00000000U, .disable = 0x000001feU},
93 {.addr = 0x00419d64, .prod = 0x00000000, .disable = 0x000001ff}, 91 {.addr = 0x00419d64U, .prod = 0x00000000U, .disable = 0x000001ffU},
94 {.addr = 0x00419a44, .prod = 0x00000000, .disable = 0x0000000e}, 92 {.addr = 0x00419a44U, .prod = 0x00000000U, .disable = 0x0000000eU},
95 {.addr = 0x00419a4c, .prod = 0x00000000, .disable = 0x000001fe}, 93 {.addr = 0x00419a4cU, .prod = 0x00000000U, .disable = 0x000001feU},
96 {.addr = 0x00419a54, .prod = 0x00000000, .disable = 0x0000003e}, 94 {.addr = 0x00419a54U, .prod = 0x00000000U, .disable = 0x0000003eU},
97 {.addr = 0x00419a5c, .prod = 0x00000000, .disable = 0x0000000e}, 95 {.addr = 0x00419a5cU, .prod = 0x00000000U, .disable = 0x0000000eU},
98 {.addr = 0x00419a64, .prod = 0x00000000, .disable = 0x000001fe}, 96 {.addr = 0x00419a64U, .prod = 0x00000000U, .disable = 0x000001feU},
99 {.addr = 0x00419a6c, .prod = 0x00000000, .disable = 0x0000000e}, 97 {.addr = 0x00419a6cU, .prod = 0x00000000U, .disable = 0x0000000eU},
100 {.addr = 0x00419a74, .prod = 0x00000000, .disable = 0x0000000e}, 98 {.addr = 0x00419a74U, .prod = 0x00000000U, .disable = 0x0000000eU},
101 {.addr = 0x00419a7c, .prod = 0x00000000, .disable = 0x0000003e}, 99 {.addr = 0x00419a7cU, .prod = 0x00000000U, .disable = 0x0000003eU},
102 {.addr = 0x00419a84, .prod = 0x00000000, .disable = 0x0000000e}, 100 {.addr = 0x00419a84U, .prod = 0x00000000U, .disable = 0x0000000eU},
103 {.addr = 0x0041986c, .prod = 0x00000104, .disable = 0x00fffffe}, 101 {.addr = 0x0041986cU, .prod = 0x00000104U, .disable = 0x00fffffeU},
104 {.addr = 0x00419cd8, .prod = 0x00000000, .disable = 0x001ffffe}, 102 {.addr = 0x00419cd8U, .prod = 0x00000000U, .disable = 0x001ffffeU},
105 {.addr = 0x00419ce0, .prod = 0x00000000, .disable = 0x001ffffe}, 103 {.addr = 0x00419ce0U, .prod = 0x00000000U, .disable = 0x001ffffeU},
106 {.addr = 0x00419c74, .prod = 0x0000001e, .disable = 0x0000001e}, 104 {.addr = 0x00419c74U, .prod = 0x0000001eU, .disable = 0x0000001eU},
107 {.addr = 0x00419fd4, .prod = 0x00000000, .disable = 0x0003fffe}, 105 {.addr = 0x00419fd4U, .prod = 0x00000000U, .disable = 0x0003fffeU},
108 {.addr = 0x00419fdc, .prod = 0xffedff00, .disable = 0xfffffffe}, 106 {.addr = 0x00419fdcU, .prod = 0xffedff00U, .disable = 0xfffffffeU},
109 {.addr = 0x00419fe4, .prod = 0x00001b00, .disable = 0x00001ffe}, 107 {.addr = 0x00419fe4U, .prod = 0x00001b00U, .disable = 0x00001ffeU},
110 {.addr = 0x00419ff4, .prod = 0x00000000, .disable = 0x00003ffe}, 108 {.addr = 0x00419ff4U, .prod = 0x00000000U, .disable = 0x00003ffeU},
111 {.addr = 0x00419ffc, .prod = 0x00000000, .disable = 0x0001fffe}, 109 {.addr = 0x00419ffcU, .prod = 0x00000000U, .disable = 0x0001fffeU},
112 {.addr = 0x0041be2c, .prod = 0x04115fc0, .disable = 0xfffffffe}, 110 {.addr = 0x0041be2cU, .prod = 0x04115fc0U, .disable = 0xfffffffeU},
113 {.addr = 0x0041bfec, .prod = 0xfffffff0, .disable = 0xfffffffe}, 111 {.addr = 0x0041bfecU, .prod = 0xfffffff0U, .disable = 0xfffffffeU},
114 {.addr = 0x0041bed4, .prod = 0xfffffff6, .disable = 0xfffffffe}, 112 {.addr = 0x0041bed4U, .prod = 0xfffffff6U, .disable = 0xfffffffeU},
115 {.addr = 0x00408814, .prod = 0x00000000, .disable = 0x0001fffe}, 113 {.addr = 0x00408814U, .prod = 0x00000000U, .disable = 0x0001fffeU},
116 {.addr = 0x0040881c, .prod = 0x00000000, .disable = 0x0001fffe}, 114 {.addr = 0x0040881cU, .prod = 0x00000000U, .disable = 0x0001fffeU},
117 {.addr = 0x00408a84, .prod = 0x00000000, .disable = 0x0001fffe}, 115 {.addr = 0x00408a84U, .prod = 0x00000000U, .disable = 0x0001fffeU},
118 {.addr = 0x00408a8c, .prod = 0x00000000, .disable = 0x0001fffe}, 116 {.addr = 0x00408a8cU, .prod = 0x00000000U, .disable = 0x0001fffeU},
119 {.addr = 0x00408a94, .prod = 0x00000000, .disable = 0x0001fffe}, 117 {.addr = 0x00408a94U, .prod = 0x00000000U, .disable = 0x0001fffeU},
120 {.addr = 0x00408a9c, .prod = 0x00000000, .disable = 0x0001fffe}, 118 {.addr = 0x00408a9cU, .prod = 0x00000000U, .disable = 0x0001fffeU},
121 {.addr = 0x00408aa4, .prod = 0x00000000, .disable = 0x0001fffe}, 119 {.addr = 0x00408aa4U, .prod = 0x00000000U, .disable = 0x0001fffeU},
122 {.addr = 0x00408aac, .prod = 0x00000000, .disable = 0x0001fffe}, 120 {.addr = 0x00408aacU, .prod = 0x00000000U, .disable = 0x0001fffeU},
123 {.addr = 0x004089ac, .prod = 0x00000000, .disable = 0x0001fffe}, 121 {.addr = 0x004089acU, .prod = 0x00000000U, .disable = 0x0001fffeU},
124 {.addr = 0x00408a24, .prod = 0x00000000, .disable = 0x000001ff}, 122 {.addr = 0x00408a24U, .prod = 0x00000000U, .disable = 0x000001ffU},
125}; 123};
126 124
127/* slcg ltc */ 125/* slcg ltc */
128static const struct gating_desc gm20b_slcg_ltc[] = { 126static const struct gating_desc gm20b_slcg_ltc[] = {
129 {.addr = 0x0017e050, .prod = 0x00000000, .disable = 0xfffffffe}, 127 {.addr = 0x0017e050U, .prod = 0x00000000U, .disable = 0xfffffffeU},
130 {.addr = 0x0017e35c, .prod = 0x00000000, .disable = 0xfffffffe}, 128 {.addr = 0x0017e35cU, .prod = 0x00000000U, .disable = 0xfffffffeU},
131}; 129};
132 130
133/* slcg perf */ 131/* slcg perf */
134static const struct gating_desc gm20b_slcg_perf[] = { 132static const struct gating_desc gm20b_slcg_perf[] = {
135 {.addr = 0x001be018, .prod = 0x000001ff, .disable = 0x00000000}, 133 {.addr = 0x001be018U, .prod = 0x000001ffU, .disable = 0x00000000U},
136 {.addr = 0x001bc018, .prod = 0x000001ff, .disable = 0x00000000}, 134 {.addr = 0x001bc018U, .prod = 0x000001ffU, .disable = 0x00000000U},
137 {.addr = 0x001b8018, .prod = 0x000001ff, .disable = 0x00000000}, 135 {.addr = 0x001b8018U, .prod = 0x000001ffU, .disable = 0x00000000U},
138 {.addr = 0x001b4124, .prod = 0x00000001, .disable = 0x00000000}, 136 {.addr = 0x001b4124U, .prod = 0x00000001U, .disable = 0x00000000U},
139}; 137};
140 138
141/* slcg PriRing */ 139/* slcg PriRing */
142static const struct gating_desc gm20b_slcg_priring[] = { 140static const struct gating_desc gm20b_slcg_priring[] = {
143 {.addr = 0x001200a8, .prod = 0x00000000, .disable = 0x00000001}, 141 {.addr = 0x001200a8U, .prod = 0x00000000U, .disable = 0x00000001U},
144}; 142};
145 143
146/* slcg pwr_csb */ 144/* slcg pwr_csb */
147static const struct gating_desc gm20b_slcg_pwr_csb[] = { 145static const struct gating_desc gm20b_slcg_pwr_csb[] = {
148 {.addr = 0x0000017c, .prod = 0x00020008, .disable = 0x0003fffe}, 146 {.addr = 0x0000017cU, .prod = 0x00020008U, .disable = 0x0003fffeU},
149 {.addr = 0x00000e74, .prod = 0x00000000, .disable = 0x0000000f}, 147 {.addr = 0x00000e74U, .prod = 0x00000000U, .disable = 0x0000000fU},
150 {.addr = 0x00000a74, .prod = 0x00000000, .disable = 0x00007ffe}, 148 {.addr = 0x00000a74U, .prod = 0x00000000U, .disable = 0x00007ffeU},
151 {.addr = 0x000016b8, .prod = 0x00000000, .disable = 0x0000000f}, 149 {.addr = 0x000016b8U, .prod = 0x00000000U, .disable = 0x0000000fU},
152}; 150};
153 151
154/* slcg pmu */ 152/* slcg pmu */
155static const struct gating_desc gm20b_slcg_pmu[] = { 153static const struct gating_desc gm20b_slcg_pmu[] = {
156 {.addr = 0x0010a17c, .prod = 0x00020008, .disable = 0x0003fffe}, 154 {.addr = 0x0010a17cU, .prod = 0x00020008U, .disable = 0x0003fffeU},
157 {.addr = 0x0010aa74, .prod = 0x00000000, .disable = 0x00007ffe}, 155 {.addr = 0x0010aa74U, .prod = 0x00000000U, .disable = 0x00007ffeU},
158 {.addr = 0x0010ae74, .prod = 0x00000000, .disable = 0x0000000f}, 156 {.addr = 0x0010ae74U, .prod = 0x00000000U, .disable = 0x0000000fU},
159}; 157};
160 158
161/* therm gr */ 159/* therm gr */
162static const struct gating_desc gm20b_slcg_therm[] = { 160static const struct gating_desc gm20b_slcg_therm[] = {
163 {.addr = 0x000206b8, .prod = 0x00000000, .disable = 0x0000000f}, 161 {.addr = 0x000206b8U, .prod = 0x00000000U, .disable = 0x0000000fU},
164}; 162};
165 163
166/* slcg Xbar */ 164/* slcg Xbar */
167static const struct gating_desc gm20b_slcg_xbar[] = { 165static const struct gating_desc gm20b_slcg_xbar[] = {
168 {.addr = 0x0013cbe4, .prod = 0x00000000, .disable = 0x1ffffffe}, 166 {.addr = 0x0013cbe4U, .prod = 0x00000000U, .disable = 0x1ffffffeU},
169 {.addr = 0x0013cc04, .prod = 0x00000000, .disable = 0x1ffffffe}, 167 {.addr = 0x0013cc04U, .prod = 0x00000000U, .disable = 0x1ffffffeU},
170}; 168};
171 169
172/* blcg bus */ 170/* blcg bus */
173static const struct gating_desc gm20b_blcg_bus[] = { 171static const struct gating_desc gm20b_blcg_bus[] = {
174 {.addr = 0x00001c00, .prod = 0x00000042, .disable = 0x00000000}, 172 {.addr = 0x00001c00U, .prod = 0x00000042U, .disable = 0x00000000U},
175}; 173};
176 174
177/* blcg ctxsw prog */ 175/* blcg ctxsw prog */
@@ -180,105 +178,107 @@ static const struct gating_desc gm20b_blcg_ctxsw_prog[] = {
180 178
181/* blcg fb */ 179/* blcg fb */
182static const struct gating_desc gm20b_blcg_fb[] = { 180static const struct gating_desc gm20b_blcg_fb[] = {
183 {.addr = 0x00100d10, .prod = 0x0000c242, .disable = 0x00000000}, 181 {.addr = 0x00100d10U, .prod = 0x0000c242U, .disable = 0x00000000U},
184 {.addr = 0x00100d30, .prod = 0x0000c242, .disable = 0x00000000}, 182 {.addr = 0x00100d30U, .prod = 0x0000c242U, .disable = 0x00000000U},
185 {.addr = 0x00100d3c, .prod = 0x00000242, .disable = 0x00000000}, 183 {.addr = 0x00100d3cU, .prod = 0x00000242U, .disable = 0x00000000U},
186 {.addr = 0x00100d48, .prod = 0x0000c242, .disable = 0x00000000}, 184 {.addr = 0x00100d48U, .prod = 0x0000c242U, .disable = 0x00000000U},
187 {.addr = 0x00100c98, .prod = 0x00000242, .disable = 0x00000000}, 185 /* fix priv error */
186 /*{.addr = 0x00100d1cU, .prod = 0x00000042U, .disable = 0x00000000U},*/
187 {.addr = 0x00100c98U, .prod = 0x00000242U, .disable = 0x00000000U},
188}; 188};
189 189
190/* blcg fifo */ 190/* blcg fifo */
191static const struct gating_desc gm20b_blcg_fifo[] = { 191static const struct gating_desc gm20b_blcg_fifo[] = {
192 {.addr = 0x000026a4, .prod = 0x0000c242, .disable = 0x00000000}, 192 {.addr = 0x000026a4U, .prod = 0x0000c242U, .disable = 0x00000000U},
193}; 193};
194 194
195/* blcg gr */ 195/* blcg gr */
196static const struct gating_desc gm20b_blcg_gr[] = { 196static const struct gating_desc gm20b_blcg_gr[] = {
197 {.addr = 0x004041f0, .prod = 0x00004046, .disable = 0x00000000}, 197 {.addr = 0x004041f0U, .prod = 0x00004046U, .disable = 0x00000000U},
198 {.addr = 0x00409890, .prod = 0x0000007f, .disable = 0x00000000}, 198 {.addr = 0x00409890U, .prod = 0x0000007fU, .disable = 0x00000000U},
199 {.addr = 0x004098b0, .prod = 0x0000007f, .disable = 0x00000000}, 199 {.addr = 0x004098b0U, .prod = 0x0000007fU, .disable = 0x00000000U},
200 {.addr = 0x004078c0, .prod = 0x00000042, .disable = 0x00000000}, 200 {.addr = 0x004078c0U, .prod = 0x00000042U, .disable = 0x00000000U},
201 {.addr = 0x00406000, .prod = 0x00004044, .disable = 0x00000000}, 201 {.addr = 0x00406000U, .prod = 0x00004044U, .disable = 0x00000000U},
202 {.addr = 0x00405860, .prod = 0x00004042, .disable = 0x00000000}, 202 {.addr = 0x00405860U, .prod = 0x00004042U, .disable = 0x00000000U},
203 {.addr = 0x0040590c, .prod = 0x00004044, .disable = 0x00000000}, 203 {.addr = 0x0040590cU, .prod = 0x00004044U, .disable = 0x00000000U},
204 {.addr = 0x00408040, .prod = 0x00004044, .disable = 0x00000000}, 204 {.addr = 0x00408040U, .prod = 0x00004044U, .disable = 0x00000000U},
205 {.addr = 0x00407000, .prod = 0x00004041, .disable = 0x00000000}, 205 {.addr = 0x00407000U, .prod = 0x00004041U, .disable = 0x00000000U},
206 {.addr = 0x00405bf0, .prod = 0x00004044, .disable = 0x00000000}, 206 {.addr = 0x00405bf0U, .prod = 0x00004044U, .disable = 0x00000000U},
207 {.addr = 0x0041a890, .prod = 0x0000007f, .disable = 0x00000000}, 207 {.addr = 0x0041a890U, .prod = 0x0000007fU, .disable = 0x00000000U},
208 {.addr = 0x0041a8b0, .prod = 0x0000007f, .disable = 0x00000000}, 208 {.addr = 0x0041a8b0U, .prod = 0x0000007fU, .disable = 0x00000000U},
209 {.addr = 0x00418500, .prod = 0x00004044, .disable = 0x00000000}, 209 {.addr = 0x00418500U, .prod = 0x00004044U, .disable = 0x00000000U},
210 {.addr = 0x00418608, .prod = 0x00004042, .disable = 0x00000000}, 210 {.addr = 0x00418608U, .prod = 0x00004042U, .disable = 0x00000000U},
211 {.addr = 0x00418688, .prod = 0x00004042, .disable = 0x00000000}, 211 {.addr = 0x00418688U, .prod = 0x00004042U, .disable = 0x00000000U},
212 {.addr = 0x00418718, .prod = 0x00000042, .disable = 0x00000000}, 212 {.addr = 0x00418718U, .prod = 0x00000042U, .disable = 0x00000000U},
213 {.addr = 0x00418828, .prod = 0x00000044, .disable = 0x00000000}, 213 {.addr = 0x00418828U, .prod = 0x00000044U, .disable = 0x00000000U},
214 {.addr = 0x00418bbc, .prod = 0x00004042, .disable = 0x00000000}, 214 {.addr = 0x00418bbcU, .prod = 0x00004042U, .disable = 0x00000000U},
215 {.addr = 0x00418970, .prod = 0x00004042, .disable = 0x00000000}, 215 {.addr = 0x00418970U, .prod = 0x00004042U, .disable = 0x00000000U},
216 {.addr = 0x00418c70, .prod = 0x00004044, .disable = 0x00000000}, 216 {.addr = 0x00418c70U, .prod = 0x00004044U, .disable = 0x00000000U},
217 {.addr = 0x00418cf0, .prod = 0x00004044, .disable = 0x00000000}, 217 {.addr = 0x00418cf0U, .prod = 0x00004044U, .disable = 0x00000000U},
218 {.addr = 0x00418d70, .prod = 0x00004044, .disable = 0x00000000}, 218 {.addr = 0x00418d70U, .prod = 0x00004044U, .disable = 0x00000000U},
219 {.addr = 0x00418f0c, .prod = 0x00004044, .disable = 0x00000000}, 219 {.addr = 0x00418f0cU, .prod = 0x00004044U, .disable = 0x00000000U},
220 {.addr = 0x00418e0c, .prod = 0x00004044, .disable = 0x00000000}, 220 {.addr = 0x00418e0cU, .prod = 0x00004044U, .disable = 0x00000000U},
221 {.addr = 0x00419020, .prod = 0x00004042, .disable = 0x00000000}, 221 {.addr = 0x00419020U, .prod = 0x00004042U, .disable = 0x00000000U},
222 {.addr = 0x00419038, .prod = 0x00000042, .disable = 0x00000000}, 222 {.addr = 0x00419038U, .prod = 0x00000042U, .disable = 0x00000000U},
223 {.addr = 0x00418898, .prod = 0x00000042, .disable = 0x00000000}, 223 {.addr = 0x00418898U, .prod = 0x00000042U, .disable = 0x00000000U},
224 {.addr = 0x00419a40, .prod = 0x00000042, .disable = 0x00000000}, 224 {.addr = 0x00419a40U, .prod = 0x00000042U, .disable = 0x00000000U},
225 {.addr = 0x00419a48, .prod = 0x00004042, .disable = 0x00000000}, 225 {.addr = 0x00419a48U, .prod = 0x00004042U, .disable = 0x00000000U},
226 {.addr = 0x00419a50, .prod = 0x00004042, .disable = 0x00000000}, 226 {.addr = 0x00419a50U, .prod = 0x00004042U, .disable = 0x00000000U},
227 {.addr = 0x00419a58, .prod = 0x00004042, .disable = 0x00000000}, 227 {.addr = 0x00419a58U, .prod = 0x00004042U, .disable = 0x00000000U},
228 {.addr = 0x00419a60, .prod = 0x00004042, .disable = 0x00000000}, 228 {.addr = 0x00419a60U, .prod = 0x00004042U, .disable = 0x00000000U},
229 {.addr = 0x00419a68, .prod = 0x00004042, .disable = 0x00000000}, 229 {.addr = 0x00419a68U, .prod = 0x00004042U, .disable = 0x00000000U},
230 {.addr = 0x00419a70, .prod = 0x00004042, .disable = 0x00000000}, 230 {.addr = 0x00419a70U, .prod = 0x00004042U, .disable = 0x00000000U},
231 {.addr = 0x00419a78, .prod = 0x00004042, .disable = 0x00000000}, 231 {.addr = 0x00419a78U, .prod = 0x00004042U, .disable = 0x00000000U},
232 {.addr = 0x00419a80, .prod = 0x00004042, .disable = 0x00000000}, 232 {.addr = 0x00419a80U, .prod = 0x00004042U, .disable = 0x00000000U},
233 {.addr = 0x00419868, .prod = 0x00000042, .disable = 0x00000000}, 233 {.addr = 0x00419868U, .prod = 0x00000042U, .disable = 0x00000000U},
234 {.addr = 0x00419cd4, .prod = 0x00000002, .disable = 0x00000000}, 234 {.addr = 0x00419cd4U, .prod = 0x00000002U, .disable = 0x00000000U},
235 {.addr = 0x00419cdc, .prod = 0x00000002, .disable = 0x00000000}, 235 {.addr = 0x00419cdcU, .prod = 0x00000002U, .disable = 0x00000000U},
236 {.addr = 0x00419c70, .prod = 0x00004044, .disable = 0x00000000}, 236 {.addr = 0x00419c70U, .prod = 0x00004044U, .disable = 0x00000000U},
237 {.addr = 0x00419fd0, .prod = 0x00004044, .disable = 0x00000000}, 237 {.addr = 0x00419fd0U, .prod = 0x00004044U, .disable = 0x00000000U},
238 {.addr = 0x00419fd8, .prod = 0x00004046, .disable = 0x00000000}, 238 {.addr = 0x00419fd8U, .prod = 0x00004046U, .disable = 0x00000000U},
239 {.addr = 0x00419fe0, .prod = 0x00004044, .disable = 0x00000000}, 239 {.addr = 0x00419fe0U, .prod = 0x00004044U, .disable = 0x00000000U},
240 {.addr = 0x00419fe8, .prod = 0x00000042, .disable = 0x00000000}, 240 {.addr = 0x00419fe8U, .prod = 0x00000042U, .disable = 0x00000000U},
241 {.addr = 0x00419ff0, .prod = 0x00004045, .disable = 0x00000000}, 241 {.addr = 0x00419ff0U, .prod = 0x00004045U, .disable = 0x00000000U},
242 {.addr = 0x00419ff8, .prod = 0x00000002, .disable = 0x00000000}, 242 {.addr = 0x00419ff8U, .prod = 0x00000002U, .disable = 0x00000000U},
243 {.addr = 0x00419f90, .prod = 0x00000002, .disable = 0x00000000}, 243 {.addr = 0x00419f90U, .prod = 0x00000002U, .disable = 0x00000000U},
244 {.addr = 0x0041be28, .prod = 0x00000042, .disable = 0x00000000}, 244 {.addr = 0x0041be28U, .prod = 0x00000042U, .disable = 0x00000000U},
245 {.addr = 0x0041bfe8, .prod = 0x00004044, .disable = 0x00000000}, 245 {.addr = 0x0041bfe8U, .prod = 0x00004044U, .disable = 0x00000000U},
246 {.addr = 0x0041bed0, .prod = 0x00004044, .disable = 0x00000000}, 246 {.addr = 0x0041bed0U, .prod = 0x00004044U, .disable = 0x00000000U},
247 {.addr = 0x00408810, .prod = 0x00004042, .disable = 0x00000000}, 247 {.addr = 0x00408810U, .prod = 0x00004042U, .disable = 0x00000000U},
248 {.addr = 0x00408818, .prod = 0x00004042, .disable = 0x00000000}, 248 {.addr = 0x00408818U, .prod = 0x00004042U, .disable = 0x00000000U},
249 {.addr = 0x00408a80, .prod = 0x00004042, .disable = 0x00000000}, 249 {.addr = 0x00408a80U, .prod = 0x00004042U, .disable = 0x00000000U},
250 {.addr = 0x00408a88, .prod = 0x00004042, .disable = 0x00000000}, 250 {.addr = 0x00408a88U, .prod = 0x00004042U, .disable = 0x00000000U},
251 {.addr = 0x00408a90, .prod = 0x00004042, .disable = 0x00000000}, 251 {.addr = 0x00408a90U, .prod = 0x00004042U, .disable = 0x00000000U},
252 {.addr = 0x00408a98, .prod = 0x00004042, .disable = 0x00000000}, 252 {.addr = 0x00408a98U, .prod = 0x00004042U, .disable = 0x00000000U},
253 {.addr = 0x00408aa0, .prod = 0x00004042, .disable = 0x00000000}, 253 {.addr = 0x00408aa0U, .prod = 0x00004042U, .disable = 0x00000000U},
254 {.addr = 0x00408aa8, .prod = 0x00004042, .disable = 0x00000000}, 254 {.addr = 0x00408aa8U, .prod = 0x00004042U, .disable = 0x00000000U},
255 {.addr = 0x004089a8, .prod = 0x00004042, .disable = 0x00000000}, 255 {.addr = 0x004089a8U, .prod = 0x00004042U, .disable = 0x00000000U},
256 {.addr = 0x004089b0, .prod = 0x00000042, .disable = 0x00000000}, 256 {.addr = 0x004089b0U, .prod = 0x00000042U, .disable = 0x00000000U},
257 {.addr = 0x004089b8, .prod = 0x00004042, .disable = 0x00000000}, 257 {.addr = 0x004089b8U, .prod = 0x00004042U, .disable = 0x00000000U},
258}; 258};
259 259
260/* blcg ltc */ 260/* blcg ltc */
261static const struct gating_desc gm20b_blcg_ltc[] = { 261static const struct gating_desc gm20b_blcg_ltc[] = {
262 {.addr = 0x0017e030, .prod = 0x00000044, .disable = 0x00000000}, 262 {.addr = 0x0017e030U, .prod = 0x00000044U, .disable = 0x00000000U},
263 {.addr = 0x0017e040, .prod = 0x00000044, .disable = 0x00000000}, 263 {.addr = 0x0017e040U, .prod = 0x00000044U, .disable = 0x00000000U},
264 {.addr = 0x0017e3e0, .prod = 0x00000044, .disable = 0x00000000}, 264 {.addr = 0x0017e3e0U, .prod = 0x00000044U, .disable = 0x00000000U},
265 {.addr = 0x0017e3c8, .prod = 0x00000044, .disable = 0x00000000}, 265 {.addr = 0x0017e3c8U, .prod = 0x00000044U, .disable = 0x00000000U},
266}; 266};
267 267
268/* blcg pwr_csb */ 268/* blcg pwr_csb */
269static const struct gating_desc gm20b_blcg_pwr_csb[] = { 269static const struct gating_desc gm20b_blcg_pwr_csb[] = {
270 {.addr = 0x00000a70, .prod = 0x00000045, .disable = 0x00000000}, 270 {.addr = 0x00000a70U, .prod = 0x00000045U, .disable = 0x00000000U},
271}; 271};
272 272
273/* blcg pmu */ 273/* blcg pmu */
274static const struct gating_desc gm20b_blcg_pmu[] = { 274static const struct gating_desc gm20b_blcg_pmu[] = {
275 {.addr = 0x0010aa70, .prod = 0x00000045, .disable = 0x00000000}, 275 {.addr = 0x0010aa70U, .prod = 0x00000045U, .disable = 0x00000000U},
276}; 276};
277 277
278/* blcg Xbar */ 278/* blcg Xbar */
279static const struct gating_desc gm20b_blcg_xbar[] = { 279static const struct gating_desc gm20b_blcg_xbar[] = {
280 {.addr = 0x0013cbe0, .prod = 0x00000042, .disable = 0x00000000}, 280 {.addr = 0x0013cbe0U, .prod = 0x00000042U, .disable = 0x00000000U},
281 {.addr = 0x0013cc00, .prod = 0x00000042, .disable = 0x00000000}, 281 {.addr = 0x0013cc00U, .prod = 0x00000042U, .disable = 0x00000000U},
282}; 282};
283 283
284/* pg gr */ 284/* pg gr */
@@ -290,18 +290,15 @@ void gm20b_slcg_bus_load_gating_prod(struct gk20a *g,
290 bool prod) 290 bool prod)
291{ 291{
292 u32 i; 292 u32 i;
293 u32 size = sizeof(gm20b_slcg_bus) / sizeof(struct gating_desc); 293 u32 size = (u32)(sizeof(gm20b_slcg_bus) / GATING_DESC_SIZE);
294 294
295 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) 295 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
296 return; 296 for (i = 0; i < size; i++) {
297 297 u32 reg = gm20b_slcg_bus[i].addr;
298 for (i = 0; i < size; i++) { 298 u32 val = prod ? gm20b_slcg_bus[i].prod :
299 if (prod) 299 gm20b_slcg_bus[i].disable;
300 gk20a_writel(g, gm20b_slcg_bus[i].addr, 300 gk20a_writel(g, reg, val);
301 gm20b_slcg_bus[i].prod); 301 }
302 else
303 gk20a_writel(g, gm20b_slcg_bus[i].addr,
304 gm20b_slcg_bus[i].disable);
305 } 302 }
306} 303}
307 304
@@ -309,18 +306,15 @@ void gm20b_slcg_ce2_load_gating_prod(struct gk20a *g,
309 bool prod) 306 bool prod)
310{ 307{
311 u32 i; 308 u32 i;
312 u32 size = sizeof(gm20b_slcg_ce2) / sizeof(struct gating_desc); 309 u32 size = (u32)(sizeof(gm20b_slcg_ce2) / GATING_DESC_SIZE);
313 310
314 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) 311 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
315 return; 312 for (i = 0; i < size; i++) {
316 313 u32 reg = gm20b_slcg_ce2[i].addr;
317 for (i = 0; i < size; i++) { 314 u32 val = prod ? gm20b_slcg_ce2[i].prod :
318 if (prod) 315 gm20b_slcg_ce2[i].disable;
319 gk20a_writel(g, gm20b_slcg_ce2[i].addr, 316 gk20a_writel(g, reg, val);
320 gm20b_slcg_ce2[i].prod); 317 }
321 else
322 gk20a_writel(g, gm20b_slcg_ce2[i].addr,
323 gm20b_slcg_ce2[i].disable);
324 } 318 }
325} 319}
326 320
@@ -328,42 +322,38 @@ void gm20b_slcg_chiplet_load_gating_prod(struct gk20a *g,
328 bool prod) 322 bool prod)
329{ 323{
330 u32 i; 324 u32 i;
331 u32 size = sizeof(gm20b_slcg_chiplet) / sizeof(struct gating_desc); 325 u32 size = (u32)(sizeof(gm20b_slcg_chiplet) / GATING_DESC_SIZE);
332 326
333 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) 327 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
334 return; 328 for (i = 0; i < size; i++) {
335 329 u32 reg = gm20b_slcg_chiplet[i].addr;
336 for (i = 0; i < size; i++) { 330 u32 val = prod ? gm20b_slcg_chiplet[i].prod :
337 if (prod) 331 gm20b_slcg_chiplet[i].disable;
338 gk20a_writel(g, gm20b_slcg_chiplet[i].addr, 332 gk20a_writel(g, reg, val);
339 gm20b_slcg_chiplet[i].prod); 333 }
340 else
341 gk20a_writel(g, gm20b_slcg_chiplet[i].addr,
342 gm20b_slcg_chiplet[i].disable);
343 } 334 }
344} 335}
345 336
346void gm20b_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, 337void gm20b_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g,
347 bool prod) 338 bool prod)
348{ 339{
340 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
341 }
349} 342}
350 343
351void gm20b_slcg_fb_load_gating_prod(struct gk20a *g, 344void gm20b_slcg_fb_load_gating_prod(struct gk20a *g,
352 bool prod) 345 bool prod)
353{ 346{
354 u32 i; 347 u32 i;
355 u32 size = sizeof(gm20b_slcg_fb) / sizeof(struct gating_desc); 348 u32 size = (u32)(sizeof(gm20b_slcg_fb) / GATING_DESC_SIZE);
356 349
357 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) 350 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
358 return; 351 for (i = 0; i < size; i++) {
359 352 u32 reg = gm20b_slcg_fb[i].addr;
360 for (i = 0; i < size; i++) { 353 u32 val = prod ? gm20b_slcg_fb[i].prod :
361 if (prod) 354 gm20b_slcg_fb[i].disable;
362 gk20a_writel(g, gm20b_slcg_fb[i].addr, 355 gk20a_writel(g, reg, val);
363 gm20b_slcg_fb[i].prod); 356 }
364 else
365 gk20a_writel(g, gm20b_slcg_fb[i].addr,
366 gm20b_slcg_fb[i].disable);
367 } 357 }
368} 358}
369 359
@@ -371,18 +361,15 @@ void gm20b_slcg_fifo_load_gating_prod(struct gk20a *g,
371 bool prod) 361 bool prod)
372{ 362{
373 u32 i; 363 u32 i;
374 u32 size = sizeof(gm20b_slcg_fifo) / sizeof(struct gating_desc); 364 u32 size = (u32)(sizeof(gm20b_slcg_fifo) / GATING_DESC_SIZE);
375 365
376 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) 366 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
377 return; 367 for (i = 0; i < size; i++) {
378 368 u32 reg = gm20b_slcg_fifo[i].addr;
379 for (i = 0; i < size; i++) { 369 u32 val = prod ? gm20b_slcg_fifo[i].prod :
380 if (prod) 370 gm20b_slcg_fifo[i].disable;
381 gk20a_writel(g, gm20b_slcg_fifo[i].addr, 371 gk20a_writel(g, reg, val);
382 gm20b_slcg_fifo[i].prod); 372 }
383 else
384 gk20a_writel(g, gm20b_slcg_fifo[i].addr,
385 gm20b_slcg_fifo[i].disable);
386 } 373 }
387} 374}
388 375
@@ -390,18 +377,15 @@ void gr_gm20b_slcg_gr_load_gating_prod(struct gk20a *g,
390 bool prod) 377 bool prod)
391{ 378{
392 u32 i; 379 u32 i;
393 u32 size = sizeof(gm20b_slcg_gr) / sizeof(struct gating_desc); 380 u32 size = (u32)(sizeof(gm20b_slcg_gr) / GATING_DESC_SIZE);
394 381
395 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) 382 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
396 return; 383 for (i = 0; i < size; i++) {
397 384 u32 reg = gm20b_slcg_gr[i].addr;
398 for (i = 0; i < size; i++) { 385 u32 val = prod ? gm20b_slcg_gr[i].prod :
399 if (prod) 386 gm20b_slcg_gr[i].disable;
400 gk20a_writel(g, gm20b_slcg_gr[i].addr, 387 gk20a_writel(g, reg, val);
401 gm20b_slcg_gr[i].prod); 388 }
402 else
403 gk20a_writel(g, gm20b_slcg_gr[i].addr,
404 gm20b_slcg_gr[i].disable);
405 } 389 }
406} 390}
407 391
@@ -409,18 +393,15 @@ void ltc_gm20b_slcg_ltc_load_gating_prod(struct gk20a *g,
409 bool prod) 393 bool prod)
410{ 394{
411 u32 i; 395 u32 i;
412 u32 size = sizeof(gm20b_slcg_ltc) / sizeof(struct gating_desc); 396 u32 size = (u32)(sizeof(gm20b_slcg_ltc) / GATING_DESC_SIZE);
413
414 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
415 return;
416 397
398 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
417 for (i = 0; i < size; i++) { 399 for (i = 0; i < size; i++) {
418 if (prod) 400 u32 reg = gm20b_slcg_ltc[i].addr;
419 gk20a_writel(g, gm20b_slcg_ltc[i].addr, 401 u32 val = prod ? gm20b_slcg_ltc[i].prod :
420 gm20b_slcg_ltc[i].prod); 402 gm20b_slcg_ltc[i].disable;
421 else 403 gk20a_writel(g, reg, val);
422 gk20a_writel(g, gm20b_slcg_ltc[i].addr, 404 }
423 gm20b_slcg_ltc[i].disable);
424 } 405 }
425} 406}
426 407
@@ -428,18 +409,15 @@ void gm20b_slcg_perf_load_gating_prod(struct gk20a *g,
428 bool prod) 409 bool prod)
429{ 410{
430 u32 i; 411 u32 i;
431 u32 size = sizeof(gm20b_slcg_perf) / sizeof(struct gating_desc); 412 u32 size = (u32)(sizeof(gm20b_slcg_perf) / GATING_DESC_SIZE);
432 413
433 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) 414 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
434 return; 415 for (i = 0; i < size; i++) {
435 416 u32 reg = gm20b_slcg_perf[i].addr;
436 for (i = 0; i < size; i++) { 417 u32 val = prod ? gm20b_slcg_perf[i].prod :
437 if (prod) 418 gm20b_slcg_perf[i].disable;
438 gk20a_writel(g, gm20b_slcg_perf[i].addr, 419 gk20a_writel(g, reg, val);
439 gm20b_slcg_perf[i].prod); 420 }
440 else
441 gk20a_writel(g, gm20b_slcg_perf[i].addr,
442 gm20b_slcg_perf[i].disable);
443 } 421 }
444} 422}
445 423
@@ -447,18 +425,15 @@ void gm20b_slcg_priring_load_gating_prod(struct gk20a *g,
447 bool prod) 425 bool prod)
448{ 426{
449 u32 i; 427 u32 i;
450 u32 size = sizeof(gm20b_slcg_priring) / sizeof(struct gating_desc); 428 u32 size = (u32)(sizeof(gm20b_slcg_priring) / GATING_DESC_SIZE);
451 429
452 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) 430 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
453 return; 431 for (i = 0; i < size; i++) {
454 432 u32 reg = gm20b_slcg_priring[i].addr;
455 for (i = 0; i < size; i++) { 433 u32 val = prod ? gm20b_slcg_priring[i].prod :
456 if (prod) 434 gm20b_slcg_priring[i].disable;
457 gk20a_writel(g, gm20b_slcg_priring[i].addr, 435 gk20a_writel(g, reg, val);
458 gm20b_slcg_priring[i].prod); 436 }
459 else
460 gk20a_writel(g, gm20b_slcg_priring[i].addr,
461 gm20b_slcg_priring[i].disable);
462 } 437 }
463} 438}
464 439
@@ -466,18 +441,15 @@ void gm20b_slcg_pwr_csb_load_gating_prod(struct gk20a *g,
466 bool prod) 441 bool prod)
467{ 442{
468 u32 i; 443 u32 i;
469 u32 size = sizeof(gm20b_slcg_pwr_csb) / sizeof(struct gating_desc); 444 u32 size = (u32)(sizeof(gm20b_slcg_pwr_csb) / GATING_DESC_SIZE);
470 445
471 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) 446 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
472 return; 447 for (i = 0; i < size; i++) {
473 448 u32 reg = gm20b_slcg_pwr_csb[i].addr;
474 for (i = 0; i < size; i++) { 449 u32 val = prod ? gm20b_slcg_pwr_csb[i].prod :
475 if (prod) 450 gm20b_slcg_pwr_csb[i].disable;
476 gk20a_writel(g, gm20b_slcg_pwr_csb[i].addr, 451 gk20a_writel(g, reg, val);
477 gm20b_slcg_pwr_csb[i].prod); 452 }
478 else
479 gk20a_writel(g, gm20b_slcg_pwr_csb[i].addr,
480 gm20b_slcg_pwr_csb[i].disable);
481 } 453 }
482} 454}
483 455
@@ -485,18 +457,15 @@ void gm20b_slcg_pmu_load_gating_prod(struct gk20a *g,
485 bool prod) 457 bool prod)
486{ 458{
487 u32 i; 459 u32 i;
488 u32 size = sizeof(gm20b_slcg_pmu) / sizeof(struct gating_desc); 460 u32 size = (u32)(sizeof(gm20b_slcg_pmu) / GATING_DESC_SIZE);
489 461
490 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) 462 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
491 return; 463 for (i = 0; i < size; i++) {
492 464 u32 reg = gm20b_slcg_pmu[i].addr;
493 for (i = 0; i < size; i++) { 465 u32 val = prod ? gm20b_slcg_pmu[i].prod :
494 if (prod) 466 gm20b_slcg_pmu[i].disable;
495 gk20a_writel(g, gm20b_slcg_pmu[i].addr, 467 gk20a_writel(g, reg, val);
496 gm20b_slcg_pmu[i].prod); 468 }
497 else
498 gk20a_writel(g, gm20b_slcg_pmu[i].addr,
499 gm20b_slcg_pmu[i].disable);
500 } 469 }
501} 470}
502 471
@@ -504,18 +473,15 @@ void gm20b_slcg_therm_load_gating_prod(struct gk20a *g,
504 bool prod) 473 bool prod)
505{ 474{
506 u32 i; 475 u32 i;
507 u32 size = sizeof(gm20b_slcg_therm) / sizeof(struct gating_desc); 476 u32 size = (u32)(sizeof(gm20b_slcg_therm) / GATING_DESC_SIZE);
508 477
509 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) 478 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
510 return; 479 for (i = 0; i < size; i++) {
511 480 u32 reg = gm20b_slcg_therm[i].addr;
512 for (i = 0; i < size; i++) { 481 u32 val = prod ? gm20b_slcg_therm[i].prod :
513 if (prod) 482 gm20b_slcg_therm[i].disable;
514 gk20a_writel(g, gm20b_slcg_therm[i].addr, 483 gk20a_writel(g, reg, val);
515 gm20b_slcg_therm[i].prod); 484 }
516 else
517 gk20a_writel(g, gm20b_slcg_therm[i].addr,
518 gm20b_slcg_therm[i].disable);
519 } 485 }
520} 486}
521 487
@@ -523,18 +489,15 @@ void gm20b_slcg_xbar_load_gating_prod(struct gk20a *g,
523 bool prod) 489 bool prod)
524{ 490{
525 u32 i; 491 u32 i;
526 u32 size = sizeof(gm20b_slcg_xbar) / sizeof(struct gating_desc); 492 u32 size = (u32)(sizeof(gm20b_slcg_xbar) / GATING_DESC_SIZE);
527 493
528 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) 494 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
529 return; 495 for (i = 0; i < size; i++) {
530 496 u32 reg = gm20b_slcg_xbar[i].addr;
531 for (i = 0; i < size; i++) { 497 u32 val = prod ? gm20b_slcg_xbar[i].prod :
532 if (prod) 498 gm20b_slcg_xbar[i].disable;
533 gk20a_writel(g, gm20b_slcg_xbar[i].addr, 499 gk20a_writel(g, reg, val);
534 gm20b_slcg_xbar[i].prod); 500 }
535 else
536 gk20a_writel(g, gm20b_slcg_xbar[i].addr,
537 gm20b_slcg_xbar[i].disable);
538 } 501 }
539} 502}
540 503
@@ -542,18 +505,15 @@ void gm20b_blcg_bus_load_gating_prod(struct gk20a *g,
542 bool prod) 505 bool prod)
543{ 506{
544 u32 i; 507 u32 i;
545 u32 size = sizeof(gm20b_blcg_bus) / sizeof(struct gating_desc); 508 u32 size = (u32)(sizeof(gm20b_blcg_bus) / GATING_DESC_SIZE);
546 509
547 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) 510 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
548 return; 511 for (i = 0; i < size; i++) {
549 512 u32 reg = gm20b_blcg_bus[i].addr;
550 for (i = 0; i < size; i++) { 513 u32 val = prod ? gm20b_blcg_bus[i].prod :
551 if (prod) 514 gm20b_blcg_bus[i].disable;
552 gk20a_writel(g, gm20b_blcg_bus[i].addr, 515 gk20a_writel(g, reg, val);
553 gm20b_blcg_bus[i].prod); 516 }
554 else
555 gk20a_writel(g, gm20b_blcg_bus[i].addr,
556 gm20b_blcg_bus[i].disable);
557 } 517 }
558} 518}
559 519
@@ -561,18 +521,15 @@ void gm20b_blcg_ctxsw_firmware_load_gating_prod(struct gk20a *g,
561 bool prod) 521 bool prod)
562{ 522{
563 u32 i; 523 u32 i;
564 u32 size = sizeof(gm20b_blcg_ctxsw_prog) / sizeof(struct gating_desc); 524 u32 size = (u32)(sizeof(gm20b_blcg_ctxsw_prog) / GATING_DESC_SIZE);
565 525
566 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) 526 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
567 return; 527 for (i = 0; i < size; i++) {
568 528 u32 reg = gm20b_blcg_ctxsw_prog[i].addr;
569 for (i = 0; i < size; i++) { 529 u32 val = prod ? gm20b_blcg_ctxsw_prog[i].prod :
570 if (prod) 530 gm20b_blcg_ctxsw_prog[i].disable;
571 gk20a_writel(g, gm20b_blcg_ctxsw_prog[i].addr, 531 gk20a_writel(g, reg, val);
572 gm20b_blcg_ctxsw_prog[i].prod); 532 }
573 else
574 gk20a_writel(g, gm20b_blcg_ctxsw_prog[i].addr,
575 gm20b_blcg_ctxsw_prog[i].disable);
576 } 533 }
577} 534}
578 535
@@ -580,18 +537,15 @@ void gm20b_blcg_fb_load_gating_prod(struct gk20a *g,
580 bool prod) 537 bool prod)
581{ 538{
582 u32 i; 539 u32 i;
583 u32 size = sizeof(gm20b_blcg_fb) / sizeof(struct gating_desc); 540 u32 size = (u32)(sizeof(gm20b_blcg_fb) / GATING_DESC_SIZE);
584 541
585 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) 542 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
586 return; 543 for (i = 0; i < size; i++) {
587 544 u32 reg = gm20b_blcg_fb[i].addr;
588 for (i = 0; i < size; i++) { 545 u32 val = prod ? gm20b_blcg_fb[i].prod :
589 if (prod) 546 gm20b_blcg_fb[i].disable;
590 gk20a_writel(g, gm20b_blcg_fb[i].addr, 547 gk20a_writel(g, reg, val);
591 gm20b_blcg_fb[i].prod); 548 }
592 else
593 gk20a_writel(g, gm20b_blcg_fb[i].addr,
594 gm20b_blcg_fb[i].disable);
595 } 549 }
596} 550}
597 551
@@ -599,18 +553,15 @@ void gm20b_blcg_fifo_load_gating_prod(struct gk20a *g,
599 bool prod) 553 bool prod)
600{ 554{
601 u32 i; 555 u32 i;
602 u32 size = sizeof(gm20b_blcg_fifo) / sizeof(struct gating_desc); 556 u32 size = (u32)(sizeof(gm20b_blcg_fifo) / GATING_DESC_SIZE);
603
604 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
605 return;
606 557
558 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
607 for (i = 0; i < size; i++) { 559 for (i = 0; i < size; i++) {
608 if (prod) 560 u32 reg = gm20b_blcg_fifo[i].addr;
609 gk20a_writel(g, gm20b_blcg_fifo[i].addr, 561 u32 val = prod ? gm20b_blcg_fifo[i].prod :
610 gm20b_blcg_fifo[i].prod); 562 gm20b_blcg_fifo[i].disable;
611 else 563 gk20a_writel(g, reg, val);
612 gk20a_writel(g, gm20b_blcg_fifo[i].addr, 564 }
613 gm20b_blcg_fifo[i].disable);
614 } 565 }
615} 566}
616 567
@@ -618,18 +569,15 @@ void gm20b_blcg_gr_load_gating_prod(struct gk20a *g,
618 bool prod) 569 bool prod)
619{ 570{
620 u32 i; 571 u32 i;
621 u32 size = sizeof(gm20b_blcg_gr) / sizeof(struct gating_desc); 572 u32 size = (u32)(sizeof(gm20b_blcg_gr) / GATING_DESC_SIZE);
622 573
623 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) 574 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
624 return; 575 for (i = 0; i < size; i++) {
625 576 u32 reg = gm20b_blcg_gr[i].addr;
626 for (i = 0; i < size; i++) { 577 u32 val = prod ? gm20b_blcg_gr[i].prod :
627 if (prod) 578 gm20b_blcg_gr[i].disable;
628 gk20a_writel(g, gm20b_blcg_gr[i].addr, 579 gk20a_writel(g, reg, val);
629 gm20b_blcg_gr[i].prod); 580 }
630 else
631 gk20a_writel(g, gm20b_blcg_gr[i].addr,
632 gm20b_blcg_gr[i].disable);
633 } 581 }
634} 582}
635 583
@@ -637,18 +585,15 @@ void gm20b_blcg_ltc_load_gating_prod(struct gk20a *g,
637 bool prod) 585 bool prod)
638{ 586{
639 u32 i; 587 u32 i;
640 u32 size = sizeof(gm20b_blcg_ltc) / sizeof(struct gating_desc); 588 u32 size = (u32)(sizeof(gm20b_blcg_ltc) / GATING_DESC_SIZE);
641 589
642 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) 590 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
643 return; 591 for (i = 0; i < size; i++) {
644 592 u32 reg = gm20b_blcg_ltc[i].addr;
645 for (i = 0; i < size; i++) { 593 u32 val = prod ? gm20b_blcg_ltc[i].prod :
646 if (prod) 594 gm20b_blcg_ltc[i].disable;
647 gk20a_writel(g, gm20b_blcg_ltc[i].addr, 595 gk20a_writel(g, reg, val);
648 gm20b_blcg_ltc[i].prod); 596 }
649 else
650 gk20a_writel(g, gm20b_blcg_ltc[i].addr,
651 gm20b_blcg_ltc[i].disable);
652 } 597 }
653} 598}
654 599
@@ -656,18 +601,15 @@ void gm20b_blcg_pwr_csb_load_gating_prod(struct gk20a *g,
656 bool prod) 601 bool prod)
657{ 602{
658 u32 i; 603 u32 i;
659 u32 size = sizeof(gm20b_blcg_pwr_csb) / sizeof(struct gating_desc); 604 u32 size = (u32)(sizeof(gm20b_blcg_pwr_csb) / GATING_DESC_SIZE);
660 605
661 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) 606 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
662 return; 607 for (i = 0; i < size; i++) {
663 608 u32 reg = gm20b_blcg_pwr_csb[i].addr;
664 for (i = 0; i < size; i++) { 609 u32 val = prod ? gm20b_blcg_pwr_csb[i].prod :
665 if (prod) 610 gm20b_blcg_pwr_csb[i].disable;
666 gk20a_writel(g, gm20b_blcg_pwr_csb[i].addr, 611 gk20a_writel(g, reg, val);
667 gm20b_blcg_pwr_csb[i].prod); 612 }
668 else
669 gk20a_writel(g, gm20b_blcg_pwr_csb[i].addr,
670 gm20b_blcg_pwr_csb[i].disable);
671 } 613 }
672} 614}
673 615
@@ -675,18 +617,15 @@ void gm20b_blcg_pmu_load_gating_prod(struct gk20a *g,
675 bool prod) 617 bool prod)
676{ 618{
677 u32 i; 619 u32 i;
678 u32 size = sizeof(gm20b_blcg_pmu) / sizeof(struct gating_desc); 620 u32 size = (u32)(sizeof(gm20b_blcg_pmu) / GATING_DESC_SIZE);
679 621
680 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) 622 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
681 return; 623 for (i = 0; i < size; i++) {
682 624 u32 reg = gm20b_blcg_pmu[i].addr;
683 for (i = 0; i < size; i++) { 625 u32 val = prod ? gm20b_blcg_pmu[i].prod :
684 if (prod) 626 gm20b_blcg_pmu[i].disable;
685 gk20a_writel(g, gm20b_blcg_pmu[i].addr, 627 gk20a_writel(g, reg, val);
686 gm20b_blcg_pmu[i].prod); 628 }
687 else
688 gk20a_writel(g, gm20b_blcg_pmu[i].addr,
689 gm20b_blcg_pmu[i].disable);
690 } 629 }
691} 630}
692 631
@@ -694,18 +633,15 @@ void gm20b_blcg_xbar_load_gating_prod(struct gk20a *g,
694 bool prod) 633 bool prod)
695{ 634{
696 u32 i; 635 u32 i;
697 u32 size = sizeof(gm20b_blcg_xbar) / sizeof(struct gating_desc); 636 u32 size = (u32)(sizeof(gm20b_blcg_xbar) / GATING_DESC_SIZE);
698 637
699 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) 638 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
700 return; 639 for (i = 0; i < size; i++) {
701 640 u32 reg = gm20b_blcg_xbar[i].addr;
702 for (i = 0; i < size; i++) { 641 u32 val = prod ? gm20b_blcg_xbar[i].prod :
703 if (prod) 642 gm20b_blcg_xbar[i].disable;
704 gk20a_writel(g, gm20b_blcg_xbar[i].addr, 643 gk20a_writel(g, reg, val);
705 gm20b_blcg_xbar[i].prod); 644 }
706 else
707 gk20a_writel(g, gm20b_blcg_xbar[i].addr,
708 gm20b_blcg_xbar[i].disable);
709 } 645 }
710} 646}
711 647
@@ -713,19 +649,14 @@ void gr_gm20b_pg_gr_load_gating_prod(struct gk20a *g,
713 bool prod) 649 bool prod)
714{ 650{
715 u32 i; 651 u32 i;
716 u32 size = sizeof(gm20b_pg_gr) / sizeof(struct gating_desc); 652 u32 size = (u32)(sizeof(gm20b_pg_gr) / GATING_DESC_SIZE);
717 653
718 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) 654 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
719 return; 655 for (i = 0; i < size; i++) {
720 656 u32 reg = gm20b_pg_gr[i].addr;
721 for (i = 0; i < size; i++) { 657 u32 val = prod ? gm20b_pg_gr[i].prod :
722 if (prod) 658 gm20b_pg_gr[i].disable;
723 gk20a_writel(g, gm20b_pg_gr[i].addr, 659 gk20a_writel(g, reg, val);
724 gm20b_pg_gr[i].prod); 660 }
725 else
726 gk20a_writel(g, gm20b_pg_gr[i].addr,
727 gm20b_pg_gr[i].disable);
728 } 661 }
729} 662}
730
731#endif /* __gm20b_gating_reglist_h__ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-07 13:27:32 -0400