diff options
Diffstat (limited to 'drivers/gpu/nvgpu/clk')
-rw-r--r-- | drivers/gpu/nvgpu/clk/clk.c | 107 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/clk/clk_domain.c | 143 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/clk/clk_fll.c | 63 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/clk/clk_freq_controller.c | 30 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/clk/clk_prog.c | 133 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/clk/clk_vf_point.c | 36 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/clk/clk_vin.c | 45 |
7 files changed, 365 insertions, 192 deletions
diff --git a/drivers/gpu/nvgpu/clk/clk.c b/drivers/gpu/nvgpu/clk/clk.c index 731124f7..392fc9b4 100644 --- a/drivers/gpu/nvgpu/clk/clk.c +++ b/drivers/gpu/nvgpu/clk/clk.c | |||
@@ -51,8 +51,9 @@ static void clkrpc_pmucmdhandler(struct gk20a *g, struct pmu_msg *msg, | |||
51 | return; | 51 | return; |
52 | } | 52 | } |
53 | 53 | ||
54 | if (phandlerparams->prpccall->b_supported) | 54 | if (phandlerparams->prpccall->b_supported) { |
55 | phandlerparams->success = 1; | 55 | phandlerparams->success = 1; |
56 | } | ||
56 | } | 57 | } |
57 | 58 | ||
58 | 59 | ||
@@ -226,16 +227,17 @@ int clk_pmu_freq_controller_load(struct gk20a *g, bool bload, u8 bit_idx) | |||
226 | status = boardobjgrpmask_export(&isolate_cfc_mask.super, | 227 | status = boardobjgrpmask_export(&isolate_cfc_mask.super, |
227 | isolate_cfc_mask.super.bitcount, | 228 | isolate_cfc_mask.super.bitcount, |
228 | &load_mask->super); | 229 | &load_mask->super); |
229 | if (bload) | 230 | if (bload) { |
230 | status = boardobjgrpmask_bitset( | 231 | status = boardobjgrpmask_bitset( |
231 | &pclk_freq_controllers-> | 232 | &pclk_freq_controllers-> |
232 | freq_ctrl_load_mask.super, | 233 | freq_ctrl_load_mask.super, |
233 | bit_idx); | 234 | bit_idx); |
234 | else | 235 | } else { |
235 | status = boardobjgrpmask_bitclr( | 236 | status = boardobjgrpmask_bitclr( |
236 | &pclk_freq_controllers-> | 237 | &pclk_freq_controllers-> |
237 | freq_ctrl_load_mask.super, | 238 | freq_ctrl_load_mask.super, |
238 | bit_idx); | 239 | bit_idx); |
240 | } | ||
239 | } | 241 | } |
240 | 242 | ||
241 | if (status) { | 243 | if (status) { |
@@ -436,13 +438,15 @@ static u32 clk_pmu_vf_inject(struct gk20a *g, struct set_fll_clk *setfllclk) | |||
436 | memset(&handler, 0, sizeof(struct clkrpc_pmucmdhandler_params)); | 438 | memset(&handler, 0, sizeof(struct clkrpc_pmucmdhandler_params)); |
437 | 439 | ||
438 | if ((setfllclk->gpc2clkmhz == 0) || (setfllclk->xbar2clkmhz == 0) || | 440 | if ((setfllclk->gpc2clkmhz == 0) || (setfllclk->xbar2clkmhz == 0) || |
439 | (setfllclk->sys2clkmhz == 0) || (setfllclk->voltuv == 0)) | 441 | (setfllclk->sys2clkmhz == 0) || (setfllclk->voltuv == 0)) { |
440 | return -EINVAL; | 442 | return -EINVAL; |
443 | } | ||
441 | 444 | ||
442 | if ((setfllclk->target_regime_id_gpc > CTRL_CLK_FLL_REGIME_ID_FR) || | 445 | if ((setfllclk->target_regime_id_gpc > CTRL_CLK_FLL_REGIME_ID_FR) || |
443 | (setfllclk->target_regime_id_sys > CTRL_CLK_FLL_REGIME_ID_FR) || | 446 | (setfllclk->target_regime_id_sys > CTRL_CLK_FLL_REGIME_ID_FR) || |
444 | (setfllclk->target_regime_id_xbar > CTRL_CLK_FLL_REGIME_ID_FR)) | 447 | (setfllclk->target_regime_id_xbar > CTRL_CLK_FLL_REGIME_ID_FR)) { |
445 | return -EINVAL; | 448 | return -EINVAL; |
449 | } | ||
446 | 450 | ||
447 | rpccall.function = NV_PMU_CLK_RPC_ID_CLK_VF_CHANGE_INJECT; | 451 | rpccall.function = NV_PMU_CLK_RPC_ID_CLK_VF_CHANGE_INJECT; |
448 | 452 | ||
@@ -501,10 +505,11 @@ static u32 find_regime_id(struct gk20a *g, u32 domain, u16 clkmhz) | |||
501 | struct fll_device *, pflldev, j) { | 505 | struct fll_device *, pflldev, j) { |
502 | if (pflldev->clk_domain == domain) { | 506 | if (pflldev->clk_domain == domain) { |
503 | if (pflldev->regime_desc.fixed_freq_regime_limit_mhz >= | 507 | if (pflldev->regime_desc.fixed_freq_regime_limit_mhz >= |
504 | clkmhz) | 508 | clkmhz) { |
505 | return CTRL_CLK_FLL_REGIME_ID_FFR; | 509 | return CTRL_CLK_FLL_REGIME_ID_FFR; |
506 | else | 510 | } else { |
507 | return CTRL_CLK_FLL_REGIME_ID_FR; | 511 | return CTRL_CLK_FLL_REGIME_ID_FR; |
512 | } | ||
508 | } | 513 | } |
509 | } | 514 | } |
510 | return CTRL_CLK_FLL_REGIME_ID_INVALID; | 515 | return CTRL_CLK_FLL_REGIME_ID_INVALID; |
@@ -549,48 +554,55 @@ int clk_set_fll_clks(struct gk20a *g, struct set_fll_clk *setfllclk) | |||
549 | /*set regime ids */ | 554 | /*set regime ids */ |
550 | status = get_regime_id(g, CTRL_CLK_DOMAIN_GPC2CLK, | 555 | status = get_regime_id(g, CTRL_CLK_DOMAIN_GPC2CLK, |
551 | &setfllclk->current_regime_id_gpc); | 556 | &setfllclk->current_regime_id_gpc); |
552 | if (status) | 557 | if (status) { |
553 | goto done; | 558 | goto done; |
559 | } | ||
554 | 560 | ||
555 | setfllclk->target_regime_id_gpc = find_regime_id(g, | 561 | setfllclk->target_regime_id_gpc = find_regime_id(g, |
556 | CTRL_CLK_DOMAIN_GPC2CLK, setfllclk->gpc2clkmhz); | 562 | CTRL_CLK_DOMAIN_GPC2CLK, setfllclk->gpc2clkmhz); |
557 | 563 | ||
558 | status = get_regime_id(g, CTRL_CLK_DOMAIN_SYS2CLK, | 564 | status = get_regime_id(g, CTRL_CLK_DOMAIN_SYS2CLK, |
559 | &setfllclk->current_regime_id_sys); | 565 | &setfllclk->current_regime_id_sys); |
560 | if (status) | 566 | if (status) { |
561 | goto done; | 567 | goto done; |
568 | } | ||
562 | 569 | ||
563 | setfllclk->target_regime_id_sys = find_regime_id(g, | 570 | setfllclk->target_regime_id_sys = find_regime_id(g, |
564 | CTRL_CLK_DOMAIN_SYS2CLK, setfllclk->sys2clkmhz); | 571 | CTRL_CLK_DOMAIN_SYS2CLK, setfllclk->sys2clkmhz); |
565 | 572 | ||
566 | status = get_regime_id(g, CTRL_CLK_DOMAIN_XBAR2CLK, | 573 | status = get_regime_id(g, CTRL_CLK_DOMAIN_XBAR2CLK, |
567 | &setfllclk->current_regime_id_xbar); | 574 | &setfllclk->current_regime_id_xbar); |
568 | if (status) | 575 | if (status) { |
569 | goto done; | 576 | goto done; |
577 | } | ||
570 | 578 | ||
571 | setfllclk->target_regime_id_xbar = find_regime_id(g, | 579 | setfllclk->target_regime_id_xbar = find_regime_id(g, |
572 | CTRL_CLK_DOMAIN_XBAR2CLK, setfllclk->xbar2clkmhz); | 580 | CTRL_CLK_DOMAIN_XBAR2CLK, setfllclk->xbar2clkmhz); |
573 | 581 | ||
574 | status = clk_pmu_vf_inject(g, setfllclk); | 582 | status = clk_pmu_vf_inject(g, setfllclk); |
575 | 583 | ||
576 | if (status) | 584 | if (status) { |
577 | nvgpu_err(g, "vf inject to change clk failed"); | 585 | nvgpu_err(g, "vf inject to change clk failed"); |
586 | } | ||
578 | 587 | ||
579 | /* save regime ids */ | 588 | /* save regime ids */ |
580 | status = set_regime_id(g, CTRL_CLK_DOMAIN_XBAR2CLK, | 589 | status = set_regime_id(g, CTRL_CLK_DOMAIN_XBAR2CLK, |
581 | setfllclk->target_regime_id_xbar); | 590 | setfllclk->target_regime_id_xbar); |
582 | if (status) | 591 | if (status) { |
583 | goto done; | 592 | goto done; |
593 | } | ||
584 | 594 | ||
585 | status = set_regime_id(g, CTRL_CLK_DOMAIN_GPC2CLK, | 595 | status = set_regime_id(g, CTRL_CLK_DOMAIN_GPC2CLK, |
586 | setfllclk->target_regime_id_gpc); | 596 | setfllclk->target_regime_id_gpc); |
587 | if (status) | 597 | if (status) { |
588 | goto done; | 598 | goto done; |
599 | } | ||
589 | 600 | ||
590 | status = set_regime_id(g, CTRL_CLK_DOMAIN_SYS2CLK, | 601 | status = set_regime_id(g, CTRL_CLK_DOMAIN_SYS2CLK, |
591 | setfllclk->target_regime_id_sys); | 602 | setfllclk->target_regime_id_sys); |
592 | if (status) | 603 | if (status) { |
593 | goto done; | 604 | goto done; |
605 | } | ||
594 | done: | 606 | done: |
595 | return status; | 607 | return status; |
596 | } | 608 | } |
@@ -606,8 +618,9 @@ int clk_get_fll_clks(struct gk20a *g, struct set_fll_clk *setfllclk) | |||
606 | struct clk_domain_3x_slave *p3xslave; | 618 | struct clk_domain_3x_slave *p3xslave; |
607 | unsigned long slaveidxmask; | 619 | unsigned long slaveidxmask; |
608 | 620 | ||
609 | if (setfllclk->gpc2clkmhz == 0) | 621 | if (setfllclk->gpc2clkmhz == 0) { |
610 | return -EINVAL; | 622 | return -EINVAL; |
623 | } | ||
611 | 624 | ||
612 | BOARDOBJGRP_FOR_EACH(&(pclk->clk_domainobjs.super.super), | 625 | BOARDOBJGRP_FOR_EACH(&(pclk->clk_domainobjs.super.super), |
613 | struct clk_domain *, pdomain, i) { | 626 | struct clk_domain *, pdomain, i) { |
@@ -627,8 +640,9 @@ int clk_get_fll_clks(struct gk20a *g, struct set_fll_clk *setfllclk) | |||
627 | if ((p3xslave->super.super.super.api_domain != | 640 | if ((p3xslave->super.super.super.api_domain != |
628 | CTRL_CLK_DOMAIN_XBAR2CLK) && | 641 | CTRL_CLK_DOMAIN_XBAR2CLK) && |
629 | (p3xslave->super.super.super.api_domain != | 642 | (p3xslave->super.super.super.api_domain != |
630 | CTRL_CLK_DOMAIN_SYS2CLK)) | 643 | CTRL_CLK_DOMAIN_SYS2CLK)) { |
631 | continue; | 644 | continue; |
645 | } | ||
632 | clkmhz = 0; | 646 | clkmhz = 0; |
633 | status = p3xslave->clkdomainclkgetslaveclk(g, | 647 | status = p3xslave->clkdomainclkgetslaveclk(g, |
634 | pclk, | 648 | pclk, |
@@ -640,11 +654,13 @@ int clk_get_fll_clks(struct gk20a *g, struct set_fll_clk *setfllclk) | |||
640 | goto done; | 654 | goto done; |
641 | } | 655 | } |
642 | if (p3xslave->super.super.super.api_domain == | 656 | if (p3xslave->super.super.super.api_domain == |
643 | CTRL_CLK_DOMAIN_XBAR2CLK) | 657 | CTRL_CLK_DOMAIN_XBAR2CLK) { |
644 | setfllclk->xbar2clkmhz = clkmhz; | 658 | setfllclk->xbar2clkmhz = clkmhz; |
659 | } | ||
645 | if (p3xslave->super.super.super.api_domain == | 660 | if (p3xslave->super.super.super.api_domain == |
646 | CTRL_CLK_DOMAIN_SYS2CLK) | 661 | CTRL_CLK_DOMAIN_SYS2CLK) { |
647 | setfllclk->sys2clkmhz = clkmhz; | 662 | setfllclk->sys2clkmhz = clkmhz; |
663 | } | ||
648 | } | 664 | } |
649 | } | 665 | } |
650 | } | 666 | } |
@@ -687,12 +703,15 @@ static int clk_program_fllclks(struct gk20a *g, struct change_fll_clk *fllclk) | |||
687 | unsigned long slaveidxmask; | 703 | unsigned long slaveidxmask; |
688 | struct set_fll_clk setfllclk; | 704 | struct set_fll_clk setfllclk; |
689 | 705 | ||
690 | if (fllclk->api_clk_domain != CTRL_CLK_DOMAIN_GPCCLK) | 706 | if (fllclk->api_clk_domain != CTRL_CLK_DOMAIN_GPCCLK) { |
691 | return -EINVAL; | 707 | return -EINVAL; |
692 | if (fllclk->voltuv == 0) | 708 | } |
709 | if (fllclk->voltuv == 0) { | ||
693 | return -EINVAL; | 710 | return -EINVAL; |
694 | if (fllclk->clkmhz == 0) | 711 | } |
712 | if (fllclk->clkmhz == 0) { | ||
695 | return -EINVAL; | 713 | return -EINVAL; |
714 | } | ||
696 | 715 | ||
697 | setfllclk.voltuv = fllclk->voltuv; | 716 | setfllclk.voltuv = fllclk->voltuv; |
698 | setfllclk.gpc2clkmhz = fllclk->clkmhz; | 717 | setfllclk.gpc2clkmhz = fllclk->clkmhz; |
@@ -715,8 +734,9 @@ static int clk_program_fllclks(struct gk20a *g, struct change_fll_clk *fllclk) | |||
715 | if ((p3xslave->super.super.super.api_domain != | 734 | if ((p3xslave->super.super.super.api_domain != |
716 | CTRL_CLK_DOMAIN_XBARCLK) && | 735 | CTRL_CLK_DOMAIN_XBARCLK) && |
717 | (p3xslave->super.super.super.api_domain != | 736 | (p3xslave->super.super.super.api_domain != |
718 | CTRL_CLK_DOMAIN_SYSCLK)) | 737 | CTRL_CLK_DOMAIN_SYSCLK)) { |
719 | continue; | 738 | continue; |
739 | } | ||
720 | clkmhz = 0; | 740 | clkmhz = 0; |
721 | status = p3xslave->clkdomainclkgetslaveclk(g, | 741 | status = p3xslave->clkdomainclkgetslaveclk(g, |
722 | pclk, | 742 | pclk, |
@@ -728,60 +748,69 @@ static int clk_program_fllclks(struct gk20a *g, struct change_fll_clk *fllclk) | |||
728 | goto done; | 748 | goto done; |
729 | } | 749 | } |
730 | if (p3xslave->super.super.super.api_domain == | 750 | if (p3xslave->super.super.super.api_domain == |
731 | CTRL_CLK_DOMAIN_XBARCLK) | 751 | CTRL_CLK_DOMAIN_XBARCLK) { |
732 | setfllclk.xbar2clkmhz = clkmhz; | 752 | setfllclk.xbar2clkmhz = clkmhz; |
753 | } | ||
733 | if (p3xslave->super.super.super.api_domain == | 754 | if (p3xslave->super.super.super.api_domain == |
734 | CTRL_CLK_DOMAIN_SYSCLK) | 755 | CTRL_CLK_DOMAIN_SYSCLK) { |
735 | setfllclk.sys2clkmhz = clkmhz; | 756 | setfllclk.sys2clkmhz = clkmhz; |
757 | } | ||
736 | } | 758 | } |
737 | } | 759 | } |
738 | } | 760 | } |
739 | /*set regime ids */ | 761 | /*set regime ids */ |
740 | status = get_regime_id(g, CTRL_CLK_DOMAIN_GPCCLK, | 762 | status = get_regime_id(g, CTRL_CLK_DOMAIN_GPCCLK, |
741 | &setfllclk.current_regime_id_gpc); | 763 | &setfllclk.current_regime_id_gpc); |
742 | if (status) | 764 | if (status) { |
743 | goto done; | 765 | goto done; |
766 | } | ||
744 | 767 | ||
745 | setfllclk.target_regime_id_gpc = find_regime_id(g, | 768 | setfllclk.target_regime_id_gpc = find_regime_id(g, |
746 | CTRL_CLK_DOMAIN_GPCCLK, setfllclk.gpc2clkmhz); | 769 | CTRL_CLK_DOMAIN_GPCCLK, setfllclk.gpc2clkmhz); |
747 | 770 | ||
748 | status = get_regime_id(g, CTRL_CLK_DOMAIN_SYSCLK, | 771 | status = get_regime_id(g, CTRL_CLK_DOMAIN_SYSCLK, |
749 | &setfllclk.current_regime_id_sys); | 772 | &setfllclk.current_regime_id_sys); |
750 | if (status) | 773 | if (status) { |
751 | goto done; | 774 | goto done; |
775 | } | ||
752 | 776 | ||
753 | setfllclk.target_regime_id_sys = find_regime_id(g, | 777 | setfllclk.target_regime_id_sys = find_regime_id(g, |
754 | CTRL_CLK_DOMAIN_SYSCLK, setfllclk.sys2clkmhz); | 778 | CTRL_CLK_DOMAIN_SYSCLK, setfllclk.sys2clkmhz); |
755 | 779 | ||
756 | status = get_regime_id(g, CTRL_CLK_DOMAIN_XBARCLK, | 780 | status = get_regime_id(g, CTRL_CLK_DOMAIN_XBARCLK, |
757 | &setfllclk.current_regime_id_xbar); | 781 | &setfllclk.current_regime_id_xbar); |
758 | if (status) | 782 | if (status) { |
759 | goto done; | 783 | goto done; |
784 | } | ||
760 | 785 | ||
761 | setfllclk.target_regime_id_xbar = find_regime_id(g, | 786 | setfllclk.target_regime_id_xbar = find_regime_id(g, |
762 | CTRL_CLK_DOMAIN_XBARCLK, setfllclk.xbar2clkmhz); | 787 | CTRL_CLK_DOMAIN_XBARCLK, setfllclk.xbar2clkmhz); |
763 | 788 | ||
764 | status = clk_pmu_vf_inject(g, &setfllclk); | 789 | status = clk_pmu_vf_inject(g, &setfllclk); |
765 | 790 | ||
766 | if (status) | 791 | if (status) { |
767 | nvgpu_err(g, | 792 | nvgpu_err(g, |
768 | "vf inject to change clk failed"); | 793 | "vf inject to change clk failed"); |
794 | } | ||
769 | 795 | ||
770 | /* save regime ids */ | 796 | /* save regime ids */ |
771 | status = set_regime_id(g, CTRL_CLK_DOMAIN_XBARCLK, | 797 | status = set_regime_id(g, CTRL_CLK_DOMAIN_XBARCLK, |
772 | setfllclk.target_regime_id_xbar); | 798 | setfllclk.target_regime_id_xbar); |
773 | if (status) | 799 | if (status) { |
774 | goto done; | 800 | goto done; |
801 | } | ||
775 | 802 | ||
776 | status = set_regime_id(g, CTRL_CLK_DOMAIN_GPCCLK, | 803 | status = set_regime_id(g, CTRL_CLK_DOMAIN_GPCCLK, |
777 | setfllclk.target_regime_id_gpc); | 804 | setfllclk.target_regime_id_gpc); |
778 | if (status) | 805 | if (status) { |
779 | goto done; | 806 | goto done; |
807 | } | ||
780 | 808 | ||
781 | status = set_regime_id(g, CTRL_CLK_DOMAIN_SYSCLK, | 809 | status = set_regime_id(g, CTRL_CLK_DOMAIN_SYSCLK, |
782 | setfllclk.target_regime_id_sys); | 810 | setfllclk.target_regime_id_sys); |
783 | if (status) | 811 | if (status) { |
784 | goto done; | 812 | goto done; |
813 | } | ||
785 | done: | 814 | done: |
786 | return status; | 815 | return status; |
787 | } | 816 | } |
@@ -809,17 +838,19 @@ u32 nvgpu_clk_set_boot_fll_clk_gv10x(struct gk20a *g) | |||
809 | voltuv = gpcclk_voltuv; | 838 | voltuv = gpcclk_voltuv; |
810 | 839 | ||
811 | status = volt_set_voltage(g, voltuv, 0); | 840 | status = volt_set_voltage(g, voltuv, 0); |
812 | if (status) | 841 | if (status) { |
813 | nvgpu_err(g, | 842 | nvgpu_err(g, |
814 | "attempt to set boot voltage failed %d", | 843 | "attempt to set boot voltage failed %d", |
815 | voltuv); | 844 | voltuv); |
845 | } | ||
816 | 846 | ||
817 | bootfllclk.api_clk_domain = CTRL_CLK_DOMAIN_GPCCLK; | 847 | bootfllclk.api_clk_domain = CTRL_CLK_DOMAIN_GPCCLK; |
818 | bootfllclk.clkmhz = gpcclk_clkmhz; | 848 | bootfllclk.clkmhz = gpcclk_clkmhz; |
819 | bootfllclk.voltuv = voltuv; | 849 | bootfllclk.voltuv = voltuv; |
820 | status = clk_program_fllclks(g, &bootfllclk); | 850 | status = clk_program_fllclks(g, &bootfllclk); |
821 | if (status) | 851 | if (status) { |
822 | nvgpu_err(g, "attempt to set boot gpcclk failed"); | 852 | nvgpu_err(g, "attempt to set boot gpcclk failed"); |
853 | } | ||
823 | 854 | ||
824 | status = clk_pmu_freq_effective_avg_load(g, true); | 855 | status = clk_pmu_freq_effective_avg_load(g, true); |
825 | 856 | ||
@@ -849,15 +880,17 @@ u32 clk_domain_get_f_or_v( | |||
849 | struct clk_pmupstate *pclk = &g->clk_pmu; | 880 | struct clk_pmupstate *pclk = &g->clk_pmu; |
850 | u8 rail; | 881 | u8 rail; |
851 | 882 | ||
852 | if ((pclkmhz == NULL) || (pvoltuv == NULL)) | 883 | if ((pclkmhz == NULL) || (pvoltuv == NULL)) { |
853 | return -EINVAL; | 884 | return -EINVAL; |
885 | } | ||
854 | 886 | ||
855 | if (railidx == CTRL_VOLT_DOMAIN_LOGIC) | 887 | if (railidx == CTRL_VOLT_DOMAIN_LOGIC) { |
856 | rail = CLK_PROG_VFE_ENTRY_LOGIC; | 888 | rail = CLK_PROG_VFE_ENTRY_LOGIC; |
857 | else if (railidx == CTRL_VOLT_DOMAIN_SRAM) | 889 | } else if (railidx == CTRL_VOLT_DOMAIN_SRAM) { |
858 | rail = CLK_PROG_VFE_ENTRY_SRAM; | 890 | rail = CLK_PROG_VFE_ENTRY_SRAM; |
859 | else | 891 | } else { |
860 | return -EINVAL; | 892 | return -EINVAL; |
893 | } | ||
861 | 894 | ||
862 | BOARDOBJGRP_FOR_EACH(&(pclk->clk_domainobjs.super.super), | 895 | BOARDOBJGRP_FOR_EACH(&(pclk->clk_domainobjs.super.super), |
863 | struct clk_domain *, pdomain, i) { | 896 | struct clk_domain *, pdomain, i) { |
diff --git a/drivers/gpu/nvgpu/clk/clk_domain.c b/drivers/gpu/nvgpu/clk/clk_domain.c index 822bba2c..9f17d199 100644 --- a/drivers/gpu/nvgpu/clk/clk_domain.c +++ b/drivers/gpu/nvgpu/clk/clk_domain.c | |||
@@ -74,34 +74,48 @@ static u32 clktranslatehalmumsettoapinumset(u32 clkhaldomains) | |||
74 | { | 74 | { |
75 | u32 clkapidomains = 0; | 75 | u32 clkapidomains = 0; |
76 | 76 | ||
77 | if (clkhaldomains & BIT(clkwhich_gpcclk)) | 77 | if (clkhaldomains & BIT(clkwhich_gpcclk)) { |
78 | clkapidomains |= CTRL_CLK_DOMAIN_GPCCLK; | 78 | clkapidomains |= CTRL_CLK_DOMAIN_GPCCLK; |
79 | if (clkhaldomains & BIT(clkwhich_xbarclk)) | 79 | } |
80 | if (clkhaldomains & BIT(clkwhich_xbarclk)) { | ||
80 | clkapidomains |= CTRL_CLK_DOMAIN_XBARCLK; | 81 | clkapidomains |= CTRL_CLK_DOMAIN_XBARCLK; |
81 | if (clkhaldomains & BIT(clkwhich_sysclk)) | 82 | } |
83 | if (clkhaldomains & BIT(clkwhich_sysclk)) { | ||
82 | clkapidomains |= CTRL_CLK_DOMAIN_SYSCLK; | 84 | clkapidomains |= CTRL_CLK_DOMAIN_SYSCLK; |
83 | if (clkhaldomains & BIT(clkwhich_hubclk)) | 85 | } |
86 | if (clkhaldomains & BIT(clkwhich_hubclk)) { | ||
84 | clkapidomains |= CTRL_CLK_DOMAIN_HUBCLK; | 87 | clkapidomains |= CTRL_CLK_DOMAIN_HUBCLK; |
85 | if (clkhaldomains & BIT(clkwhich_hostclk)) | 88 | } |
89 | if (clkhaldomains & BIT(clkwhich_hostclk)) { | ||
86 | clkapidomains |= CTRL_CLK_DOMAIN_HOSTCLK; | 90 | clkapidomains |= CTRL_CLK_DOMAIN_HOSTCLK; |
87 | if (clkhaldomains & BIT(clkwhich_gpc2clk)) | 91 | } |
92 | if (clkhaldomains & BIT(clkwhich_gpc2clk)) { | ||
88 | clkapidomains |= CTRL_CLK_DOMAIN_GPC2CLK; | 93 | clkapidomains |= CTRL_CLK_DOMAIN_GPC2CLK; |
89 | if (clkhaldomains & BIT(clkwhich_xbar2clk)) | 94 | } |
95 | if (clkhaldomains & BIT(clkwhich_xbar2clk)) { | ||
90 | clkapidomains |= CTRL_CLK_DOMAIN_XBAR2CLK; | 96 | clkapidomains |= CTRL_CLK_DOMAIN_XBAR2CLK; |
91 | if (clkhaldomains & BIT(clkwhich_sys2clk)) | 97 | } |
98 | if (clkhaldomains & BIT(clkwhich_sys2clk)) { | ||
92 | clkapidomains |= CTRL_CLK_DOMAIN_SYS2CLK; | 99 | clkapidomains |= CTRL_CLK_DOMAIN_SYS2CLK; |
93 | if (clkhaldomains & BIT(clkwhich_hub2clk)) | 100 | } |
101 | if (clkhaldomains & BIT(clkwhich_hub2clk)) { | ||
94 | clkapidomains |= CTRL_CLK_DOMAIN_HUB2CLK; | 102 | clkapidomains |= CTRL_CLK_DOMAIN_HUB2CLK; |
95 | if (clkhaldomains & BIT(clkwhich_pwrclk)) | 103 | } |
104 | if (clkhaldomains & BIT(clkwhich_pwrclk)) { | ||
96 | clkapidomains |= CTRL_CLK_DOMAIN_PWRCLK; | 105 | clkapidomains |= CTRL_CLK_DOMAIN_PWRCLK; |
97 | if (clkhaldomains & BIT(clkwhich_pciegenclk)) | 106 | } |
107 | if (clkhaldomains & BIT(clkwhich_pciegenclk)) { | ||
98 | clkapidomains |= CTRL_CLK_DOMAIN_PCIEGENCLK; | 108 | clkapidomains |= CTRL_CLK_DOMAIN_PCIEGENCLK; |
99 | if (clkhaldomains & BIT(clkwhich_mclk)) | 109 | } |
110 | if (clkhaldomains & BIT(clkwhich_mclk)) { | ||
100 | clkapidomains |= CTRL_CLK_DOMAIN_MCLK; | 111 | clkapidomains |= CTRL_CLK_DOMAIN_MCLK; |
101 | if (clkhaldomains & BIT(clkwhich_nvdclk)) | 112 | } |
113 | if (clkhaldomains & BIT(clkwhich_nvdclk)) { | ||
102 | clkapidomains |= CTRL_CLK_DOMAIN_NVDCLK; | 114 | clkapidomains |= CTRL_CLK_DOMAIN_NVDCLK; |
103 | if (clkhaldomains & BIT(clkwhich_dispclk)) | 115 | } |
116 | if (clkhaldomains & BIT(clkwhich_dispclk)) { | ||
104 | clkapidomains |= CTRL_CLK_DOMAIN_DISPCLK; | 117 | clkapidomains |= CTRL_CLK_DOMAIN_DISPCLK; |
118 | } | ||
105 | 119 | ||
106 | return clkapidomains; | 120 | return clkapidomains; |
107 | } | 121 | } |
@@ -131,10 +145,11 @@ static u32 _clk_domains_pmudatainit_3x(struct gk20a *g, | |||
131 | pset->b_debug_mode = false; | 145 | pset->b_debug_mode = false; |
132 | pset->b_enforce_vf_monotonicity = pdomains->b_enforce_vf_monotonicity; | 146 | pset->b_enforce_vf_monotonicity = pdomains->b_enforce_vf_monotonicity; |
133 | pset->b_enforce_vf_smoothening = pdomains->b_enforce_vf_smoothening; | 147 | pset->b_enforce_vf_smoothening = pdomains->b_enforce_vf_smoothening; |
134 | if (g->ops.clk.split_rail_support) | 148 | if (g->ops.clk.split_rail_support) { |
135 | pset->volt_rails_max = 2; | 149 | pset->volt_rails_max = 2; |
136 | else | 150 | } else { |
137 | pset->volt_rails_max = 1; | 151 | pset->volt_rails_max = 1; |
152 | } | ||
138 | status = boardobjgrpmask_export( | 153 | status = boardobjgrpmask_export( |
139 | &pdomains->master_domains_mask.super, | 154 | &pdomains->master_domains_mask.super, |
140 | pdomains->master_domains_mask.super.bitcount, | 155 | pdomains->master_domains_mask.super.bitcount, |
@@ -160,8 +175,9 @@ static u32 _clk_domains_pmudata_instget(struct gk20a *g, | |||
160 | 175 | ||
161 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ | 176 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ |
162 | if (((u32)BIT(idx) & | 177 | if (((u32)BIT(idx) & |
163 | pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0) | 178 | pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0) { |
164 | return -EINVAL; | 179 | return -EINVAL; |
180 | } | ||
165 | 181 | ||
166 | *ppboardobjpmudata = (struct nv_pmu_boardobj *) | 182 | *ppboardobjpmudata = (struct nv_pmu_boardobj *) |
167 | &pgrp_set->objects[idx].data.board_obj; | 183 | &pgrp_set->objects[idx].data.board_obj; |
@@ -222,8 +238,9 @@ u32 clk_domain_sw_setup(struct gk20a *g) | |||
222 | sizeof(struct ctrl_clk_clk_delta)); | 238 | sizeof(struct ctrl_clk_clk_delta)); |
223 | 239 | ||
224 | status = devinit_get_clocks_table(g, pclkdomainobjs); | 240 | status = devinit_get_clocks_table(g, pclkdomainobjs); |
225 | if (status) | 241 | if (status) { |
226 | goto done; | 242 | goto done; |
243 | } | ||
227 | 244 | ||
228 | BOARDOBJGRP_FOR_EACH(&(pclkdomainobjs->super.super), | 245 | BOARDOBJGRP_FOR_EACH(&(pclkdomainobjs->super.super), |
229 | struct clk_domain *, pdomain, i) { | 246 | struct clk_domain *, pdomain, i) { |
@@ -232,16 +249,18 @@ u32 clk_domain_sw_setup(struct gk20a *g) | |||
232 | CTRL_CLK_CLK_DOMAIN_TYPE_3X_PROG)) { | 249 | CTRL_CLK_CLK_DOMAIN_TYPE_3X_PROG)) { |
233 | status = boardobjgrpmask_bitset( | 250 | status = boardobjgrpmask_bitset( |
234 | &pclkdomainobjs->prog_domains_mask.super, i); | 251 | &pclkdomainobjs->prog_domains_mask.super, i); |
235 | if (status) | 252 | if (status) { |
236 | goto done; | 253 | goto done; |
254 | } | ||
237 | } | 255 | } |
238 | 256 | ||
239 | if (pdomain->super.implements(g, &pdomain->super, | 257 | if (pdomain->super.implements(g, &pdomain->super, |
240 | CTRL_CLK_CLK_DOMAIN_TYPE_3X_MASTER)) { | 258 | CTRL_CLK_CLK_DOMAIN_TYPE_3X_MASTER)) { |
241 | status = boardobjgrpmask_bitset( | 259 | status = boardobjgrpmask_bitset( |
242 | &pclkdomainobjs->master_domains_mask.super, i); | 260 | &pclkdomainobjs->master_domains_mask.super, i); |
243 | if (status) | 261 | if (status) { |
244 | goto done; | 262 | goto done; |
263 | } | ||
245 | } | 264 | } |
246 | 265 | ||
247 | if (pdomain->super.implements(g, &pdomain->super, | 266 | if (pdomain->super.implements(g, &pdomain->super, |
@@ -271,8 +290,9 @@ u32 clk_domain_pmu_setup(struct gk20a *g) | |||
271 | 290 | ||
272 | pboardobjgrp = &g->clk_pmu.clk_domainobjs.super.super; | 291 | pboardobjgrp = &g->clk_pmu.clk_domainobjs.super.super; |
273 | 292 | ||
274 | if (!pboardobjgrp->bconstructed) | 293 | if (!pboardobjgrp->bconstructed) { |
275 | return -EINVAL; | 294 | return -EINVAL; |
295 | } | ||
276 | 296 | ||
277 | status = pboardobjgrp->pmuinithandle(g, pboardobjgrp); | 297 | status = pboardobjgrp->pmuinithandle(g, pboardobjgrp); |
278 | 298 | ||
@@ -511,8 +531,9 @@ static u32 clk_domain_construct_super(struct gk20a *g, | |||
511 | status = boardobj_construct_super(g, ppboardobj, | 531 | status = boardobj_construct_super(g, ppboardobj, |
512 | size, pargs); | 532 | size, pargs); |
513 | 533 | ||
514 | if (status) | 534 | if (status) { |
515 | return -EINVAL; | 535 | return -EINVAL; |
536 | } | ||
516 | 537 | ||
517 | pdomain = (struct clk_domain *)*ppboardobj; | 538 | pdomain = (struct clk_domain *)*ppboardobj; |
518 | 539 | ||
@@ -547,8 +568,9 @@ static u32 _clk_domain_pmudatainit_3x(struct gk20a *g, | |||
547 | nvgpu_log_info(g, " "); | 568 | nvgpu_log_info(g, " "); |
548 | 569 | ||
549 | status = clk_domain_pmudatainit_super(g, board_obj_ptr, ppmudata); | 570 | status = clk_domain_pmudatainit_super(g, board_obj_ptr, ppmudata); |
550 | if (status != 0) | 571 | if (status != 0) { |
551 | return status; | 572 | return status; |
573 | } | ||
552 | 574 | ||
553 | pclk_domain_3x = (struct clk_domain_3x *)board_obj_ptr; | 575 | pclk_domain_3x = (struct clk_domain_3x *)board_obj_ptr; |
554 | 576 | ||
@@ -572,8 +594,9 @@ static u32 clk_domain_construct_3x(struct gk20a *g, | |||
572 | ptmpobj->type_mask = BIT(CTRL_CLK_CLK_DOMAIN_TYPE_3X); | 594 | ptmpobj->type_mask = BIT(CTRL_CLK_CLK_DOMAIN_TYPE_3X); |
573 | status = clk_domain_construct_super(g, ppboardobj, | 595 | status = clk_domain_construct_super(g, ppboardobj, |
574 | size, pargs); | 596 | size, pargs); |
575 | if (status) | 597 | if (status) { |
576 | return -EINVAL; | 598 | return -EINVAL; |
599 | } | ||
577 | 600 | ||
578 | pdomain = (struct clk_domain_3x *)*ppboardobj; | 601 | pdomain = (struct clk_domain_3x *)*ppboardobj; |
579 | 602 | ||
@@ -601,8 +624,9 @@ static u32 clkdomainclkproglink_3x_prog(struct gk20a *g, | |||
601 | i <= p3xprog->clk_prog_idx_last; | 624 | i <= p3xprog->clk_prog_idx_last; |
602 | i++) { | 625 | i++) { |
603 | pprog = CLK_CLK_PROG_GET(pclk, i); | 626 | pprog = CLK_CLK_PROG_GET(pclk, i); |
604 | if (pprog == NULL) | 627 | if (pprog == NULL) { |
605 | status = -EINVAL; | 628 | status = -EINVAL; |
629 | } | ||
606 | } | 630 | } |
607 | return status; | 631 | return status; |
608 | } | 632 | } |
@@ -621,11 +645,13 @@ static int clkdomaingetslaveclk(struct gk20a *g, | |||
621 | 645 | ||
622 | nvgpu_log_info(g, " "); | 646 | nvgpu_log_info(g, " "); |
623 | 647 | ||
624 | if (pclkmhz == NULL) | 648 | if (pclkmhz == NULL) { |
625 | return -EINVAL; | 649 | return -EINVAL; |
650 | } | ||
626 | 651 | ||
627 | if (masterclkmhz == 0) | 652 | if (masterclkmhz == 0) { |
628 | return -EINVAL; | 653 | return -EINVAL; |
654 | } | ||
629 | 655 | ||
630 | slaveidx = BOARDOBJ_GET_IDX(pdomain); | 656 | slaveidx = BOARDOBJ_GET_IDX(pdomain); |
631 | p3xmaster = (struct clk_domain_3x_master *) | 657 | p3xmaster = (struct clk_domain_3x_master *) |
@@ -662,11 +688,13 @@ static int clkdomainvfsearch(struct gk20a *g, | |||
662 | 688 | ||
663 | nvgpu_log_info(g, " "); | 689 | nvgpu_log_info(g, " "); |
664 | 690 | ||
665 | if ((pclkmhz == NULL) || (pvoltuv == NULL)) | 691 | if ((pclkmhz == NULL) || (pvoltuv == NULL)) { |
666 | return -EINVAL; | 692 | return -EINVAL; |
693 | } | ||
667 | 694 | ||
668 | if ((*pclkmhz != 0) && (*pvoltuv != 0)) | 695 | if ((*pclkmhz != 0) && (*pvoltuv != 0)) { |
669 | return -EINVAL; | 696 | return -EINVAL; |
697 | } | ||
670 | 698 | ||
671 | bestclkmhz = *pclkmhz; | 699 | bestclkmhz = *pclkmhz; |
672 | bestvoltuv = *pvoltuv; | 700 | bestvoltuv = *pvoltuv; |
@@ -749,15 +777,18 @@ static u32 clkdomaingetfpoints | |||
749 | 777 | ||
750 | nvgpu_log_info(g, " "); | 778 | nvgpu_log_info(g, " "); |
751 | 779 | ||
752 | if (pfpointscount == NULL) | 780 | if (pfpointscount == NULL) { |
753 | return -EINVAL; | 781 | return -EINVAL; |
782 | } | ||
754 | 783 | ||
755 | if ((pfreqpointsinmhz == NULL) && (*pfpointscount != 0)) | 784 | if ((pfreqpointsinmhz == NULL) && (*pfpointscount != 0)) { |
756 | return -EINVAL; | 785 | return -EINVAL; |
786 | } | ||
757 | 787 | ||
758 | if (pdomain->super.implements(g, &pdomain->super, | 788 | if (pdomain->super.implements(g, &pdomain->super, |
759 | CTRL_CLK_CLK_DOMAIN_TYPE_3X_SLAVE)) | 789 | CTRL_CLK_CLK_DOMAIN_TYPE_3X_SLAVE)) { |
760 | return -EINVAL; | 790 | return -EINVAL; |
791 | } | ||
761 | 792 | ||
762 | freqpointsdata = pfreqpointsinmhz; | 793 | freqpointsdata = pfreqpointsinmhz; |
763 | totalcount = 0; | 794 | totalcount = 0; |
@@ -779,8 +810,9 @@ static u32 clkdomaingetfpoints | |||
779 | if (*pfpointscount) { | 810 | if (*pfpointscount) { |
780 | remainingcount -= fpointscount; | 811 | remainingcount -= fpointscount; |
781 | fpointscount = remainingcount; | 812 | fpointscount = remainingcount; |
782 | } else | 813 | } else { |
783 | fpointscount = 0; | 814 | fpointscount = 0; |
815 | } | ||
784 | 816 | ||
785 | } | 817 | } |
786 | 818 | ||
@@ -802,8 +834,9 @@ static u32 _clk_domain_pmudatainit_3x_prog(struct gk20a *g, | |||
802 | nvgpu_log_info(g, " "); | 834 | nvgpu_log_info(g, " "); |
803 | 835 | ||
804 | status = _clk_domain_pmudatainit_3x(g, board_obj_ptr, ppmudata); | 836 | status = _clk_domain_pmudatainit_3x(g, board_obj_ptr, ppmudata); |
805 | if (status != 0) | 837 | if (status != 0) { |
806 | return status; | 838 | return status; |
839 | } | ||
807 | 840 | ||
808 | pclk_domain_3x_prog = (struct clk_domain_3x_prog *)board_obj_ptr; | 841 | pclk_domain_3x_prog = (struct clk_domain_3x_prog *)board_obj_ptr; |
809 | 842 | ||
@@ -839,8 +872,9 @@ static u32 clk_domain_construct_3x_prog(struct gk20a *g, | |||
839 | 872 | ||
840 | ptmpobj->type_mask |= BIT(CTRL_CLK_CLK_DOMAIN_TYPE_3X_PROG); | 873 | ptmpobj->type_mask |= BIT(CTRL_CLK_CLK_DOMAIN_TYPE_3X_PROG); |
841 | status = clk_domain_construct_3x(g, ppboardobj, size, pargs); | 874 | status = clk_domain_construct_3x(g, ppboardobj, size, pargs); |
842 | if (status) | 875 | if (status) { |
843 | return -EINVAL; | 876 | return -EINVAL; |
877 | } | ||
844 | 878 | ||
845 | pdomain = (struct clk_domain_3x_prog *)*ppboardobj; | 879 | pdomain = (struct clk_domain_3x_prog *)*ppboardobj; |
846 | 880 | ||
@@ -882,8 +916,9 @@ static u32 _clk_domain_pmudatainit_3x_slave(struct gk20a *g, | |||
882 | nvgpu_log_info(g, " "); | 916 | nvgpu_log_info(g, " "); |
883 | 917 | ||
884 | status = _clk_domain_pmudatainit_3x_prog(g, board_obj_ptr, ppmudata); | 918 | status = _clk_domain_pmudatainit_3x_prog(g, board_obj_ptr, ppmudata); |
885 | if (status != 0) | 919 | if (status != 0) { |
886 | return status; | 920 | return status; |
921 | } | ||
887 | 922 | ||
888 | pclk_domain_3x_slave = (struct clk_domain_3x_slave *)board_obj_ptr; | 923 | pclk_domain_3x_slave = (struct clk_domain_3x_slave *)board_obj_ptr; |
889 | 924 | ||
@@ -905,13 +940,15 @@ static u32 clk_domain_construct_3x_slave(struct gk20a *g, | |||
905 | (struct clk_domain_3x_slave *)pargs; | 940 | (struct clk_domain_3x_slave *)pargs; |
906 | u32 status = 0; | 941 | u32 status = 0; |
907 | 942 | ||
908 | if (BOARDOBJ_GET_TYPE(pargs) != CTRL_CLK_CLK_DOMAIN_TYPE_3X_SLAVE) | 943 | if (BOARDOBJ_GET_TYPE(pargs) != CTRL_CLK_CLK_DOMAIN_TYPE_3X_SLAVE) { |
909 | return -EINVAL; | 944 | return -EINVAL; |
945 | } | ||
910 | 946 | ||
911 | ptmpobj->type_mask |= BIT(CTRL_CLK_CLK_DOMAIN_TYPE_3X_SLAVE); | 947 | ptmpobj->type_mask |= BIT(CTRL_CLK_CLK_DOMAIN_TYPE_3X_SLAVE); |
912 | status = clk_domain_construct_3x_prog(g, ppboardobj, size, pargs); | 948 | status = clk_domain_construct_3x_prog(g, ppboardobj, size, pargs); |
913 | if (status) | 949 | if (status) { |
914 | return -EINVAL; | 950 | return -EINVAL; |
951 | } | ||
915 | 952 | ||
916 | pdomain = (struct clk_domain_3x_slave *)*ppboardobj; | 953 | pdomain = (struct clk_domain_3x_slave *)*ppboardobj; |
917 | 954 | ||
@@ -941,8 +978,9 @@ static u32 clkdomainclkproglink_3x_master(struct gk20a *g, | |||
941 | nvgpu_log_info(g, " "); | 978 | nvgpu_log_info(g, " "); |
942 | 979 | ||
943 | status = clkdomainclkproglink_3x_prog(g, pclk, pdomain); | 980 | status = clkdomainclkproglink_3x_prog(g, pclk, pdomain); |
944 | if (status) | 981 | if (status) { |
945 | goto done; | 982 | goto done; |
983 | } | ||
946 | 984 | ||
947 | /* Iterate over the set of CLK_PROGs pointed at by this domain.*/ | 985 | /* Iterate over the set of CLK_PROGs pointed at by this domain.*/ |
948 | for (i = p3xmaster->super.clk_prog_idx_first; | 986 | for (i = p3xmaster->super.clk_prog_idx_first; |
@@ -960,8 +998,9 @@ static u32 clkdomainclkproglink_3x_master(struct gk20a *g, | |||
960 | pprog1xmaster = (struct clk_prog_1x_master *)pprog; | 998 | pprog1xmaster = (struct clk_prog_1x_master *)pprog; |
961 | status = pprog1xmaster->vfflatten(g, pclk, pprog1xmaster, | 999 | status = pprog1xmaster->vfflatten(g, pclk, pprog1xmaster, |
962 | BOARDOBJ_GET_IDX(p3xmaster), &freq_max_last_mhz); | 1000 | BOARDOBJ_GET_IDX(p3xmaster), &freq_max_last_mhz); |
963 | if (status) | 1001 | if (status) { |
964 | goto done; | 1002 | goto done; |
1003 | } | ||
965 | } | 1004 | } |
966 | done: | 1005 | done: |
967 | nvgpu_log_info(g, "done status %x", status); | 1006 | nvgpu_log_info(g, "done status %x", status); |
@@ -979,8 +1018,9 @@ static u32 _clk_domain_pmudatainit_3x_master(struct gk20a *g, | |||
979 | nvgpu_log_info(g, " "); | 1018 | nvgpu_log_info(g, " "); |
980 | 1019 | ||
981 | status = _clk_domain_pmudatainit_3x_prog(g, board_obj_ptr, ppmudata); | 1020 | status = _clk_domain_pmudatainit_3x_prog(g, board_obj_ptr, ppmudata); |
982 | if (status != 0) | 1021 | if (status != 0) { |
983 | return status; | 1022 | return status; |
1023 | } | ||
984 | 1024 | ||
985 | pclk_domain_3x_master = (struct clk_domain_3x_master *)board_obj_ptr; | 1025 | pclk_domain_3x_master = (struct clk_domain_3x_master *)board_obj_ptr; |
986 | 1026 | ||
@@ -1000,13 +1040,15 @@ static u32 clk_domain_construct_3x_master(struct gk20a *g, | |||
1000 | struct clk_domain_3x_master *pdomain; | 1040 | struct clk_domain_3x_master *pdomain; |
1001 | u32 status = 0; | 1041 | u32 status = 0; |
1002 | 1042 | ||
1003 | if (BOARDOBJ_GET_TYPE(pargs) != CTRL_CLK_CLK_DOMAIN_TYPE_3X_MASTER) | 1043 | if (BOARDOBJ_GET_TYPE(pargs) != CTRL_CLK_CLK_DOMAIN_TYPE_3X_MASTER) { |
1004 | return -EINVAL; | 1044 | return -EINVAL; |
1045 | } | ||
1005 | 1046 | ||
1006 | ptmpobj->type_mask |= BIT(CTRL_CLK_CLK_DOMAIN_TYPE_3X_MASTER); | 1047 | ptmpobj->type_mask |= BIT(CTRL_CLK_CLK_DOMAIN_TYPE_3X_MASTER); |
1007 | status = clk_domain_construct_3x_prog(g, ppboardobj, size, pargs); | 1048 | status = clk_domain_construct_3x_prog(g, ppboardobj, size, pargs); |
1008 | if (status) | 1049 | if (status) { |
1009 | return -EINVAL; | 1050 | return -EINVAL; |
1051 | } | ||
1010 | 1052 | ||
1011 | pdomain = (struct clk_domain_3x_master *)*ppboardobj; | 1053 | pdomain = (struct clk_domain_3x_master *)*ppboardobj; |
1012 | 1054 | ||
@@ -1039,8 +1081,9 @@ static u32 _clk_domain_pmudatainit_3x_fixed(struct gk20a *g, | |||
1039 | nvgpu_log_info(g, " "); | 1081 | nvgpu_log_info(g, " "); |
1040 | 1082 | ||
1041 | status = _clk_domain_pmudatainit_3x(g, board_obj_ptr, ppmudata); | 1083 | status = _clk_domain_pmudatainit_3x(g, board_obj_ptr, ppmudata); |
1042 | if (status != 0) | 1084 | if (status != 0) { |
1043 | return status; | 1085 | return status; |
1086 | } | ||
1044 | 1087 | ||
1045 | pclk_domain_3x_fixed = (struct clk_domain_3x_fixed *)board_obj_ptr; | 1088 | pclk_domain_3x_fixed = (struct clk_domain_3x_fixed *)board_obj_ptr; |
1046 | 1089 | ||
@@ -1062,13 +1105,15 @@ static u32 clk_domain_construct_3x_fixed(struct gk20a *g, | |||
1062 | (struct clk_domain_3x_fixed *)pargs; | 1105 | (struct clk_domain_3x_fixed *)pargs; |
1063 | u32 status = 0; | 1106 | u32 status = 0; |
1064 | 1107 | ||
1065 | if (BOARDOBJ_GET_TYPE(pargs) != CTRL_CLK_CLK_DOMAIN_TYPE_3X_FIXED) | 1108 | if (BOARDOBJ_GET_TYPE(pargs) != CTRL_CLK_CLK_DOMAIN_TYPE_3X_FIXED) { |
1066 | return -EINVAL; | 1109 | return -EINVAL; |
1110 | } | ||
1067 | 1111 | ||
1068 | ptmpobj->type_mask |= BIT(CTRL_CLK_CLK_DOMAIN_TYPE_3X_FIXED); | 1112 | ptmpobj->type_mask |= BIT(CTRL_CLK_CLK_DOMAIN_TYPE_3X_FIXED); |
1069 | status = clk_domain_construct_3x(g, ppboardobj, size, pargs); | 1113 | status = clk_domain_construct_3x(g, ppboardobj, size, pargs); |
1070 | if (status) | 1114 | if (status) { |
1071 | return -EINVAL; | 1115 | return -EINVAL; |
1116 | } | ||
1072 | 1117 | ||
1073 | pdomain = (struct clk_domain_3x_fixed *)*ppboardobj; | 1118 | pdomain = (struct clk_domain_3x_fixed *)*ppboardobj; |
1074 | 1119 | ||
@@ -1109,8 +1154,9 @@ static struct clk_domain *construct_clk_domain(struct gk20a *g, void *pargs) | |||
1109 | return NULL; | 1154 | return NULL; |
1110 | } | 1155 | } |
1111 | 1156 | ||
1112 | if (status) | 1157 | if (status) { |
1113 | return NULL; | 1158 | return NULL; |
1159 | } | ||
1114 | 1160 | ||
1115 | nvgpu_log_info(g, " Done"); | 1161 | nvgpu_log_info(g, " Done"); |
1116 | 1162 | ||
@@ -1128,8 +1174,9 @@ static u32 clk_domain_pmudatainit_super(struct gk20a *g, | |||
1128 | nvgpu_log_info(g, " "); | 1174 | nvgpu_log_info(g, " "); |
1129 | 1175 | ||
1130 | status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata); | 1176 | status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata); |
1131 | if (status != 0) | 1177 | if (status != 0) { |
1132 | return status; | 1178 | return status; |
1179 | } | ||
1133 | 1180 | ||
1134 | pclk_domain = (struct clk_domain *)board_obj_ptr; | 1181 | pclk_domain = (struct clk_domain *)board_obj_ptr; |
1135 | 1182 | ||
diff --git a/drivers/gpu/nvgpu/clk/clk_fll.c b/drivers/gpu/nvgpu/clk/clk_fll.c index a05fdf22..0fd9c33f 100644 --- a/drivers/gpu/nvgpu/clk/clk_fll.c +++ b/drivers/gpu/nvgpu/clk/clk_fll.c | |||
@@ -84,8 +84,9 @@ static u32 _clk_fll_devgrp_pmudata_instget(struct gk20a *g, | |||
84 | 84 | ||
85 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ | 85 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ |
86 | if (((u32)BIT(idx) & | 86 | if (((u32)BIT(idx) & |
87 | pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0) | 87 | pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0) { |
88 | return -EINVAL; | 88 | return -EINVAL; |
89 | } | ||
89 | 90 | ||
90 | *ppboardobjpmudata = (struct nv_pmu_boardobj *) | 91 | *ppboardobjpmudata = (struct nv_pmu_boardobj *) |
91 | &pgrp_set->objects[idx].data.board_obj; | 92 | &pgrp_set->objects[idx].data.board_obj; |
@@ -104,8 +105,9 @@ static u32 _clk_fll_devgrp_pmustatus_instget(struct gk20a *g, | |||
104 | 105 | ||
105 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ | 106 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ |
106 | if (((u32)BIT(idx) & | 107 | if (((u32)BIT(idx) & |
107 | pgrp_get_status->hdr.data.super.obj_mask.super.data[0]) == 0) | 108 | pgrp_get_status->hdr.data.super.obj_mask.super.data[0]) == 0) { |
108 | return -EINVAL; | 109 | return -EINVAL; |
110 | } | ||
109 | 111 | ||
110 | *ppboardobjpmustatus = (struct nv_pmu_boardobj_query *) | 112 | *ppboardobjpmustatus = (struct nv_pmu_boardobj_query *) |
111 | &pgrp_get_status->objects[idx].data.board_obj; | 113 | &pgrp_get_status->objects[idx].data.board_obj; |
@@ -157,8 +159,9 @@ u32 clk_fll_sw_setup(struct gk20a *g) | |||
157 | boardobjgrpmask_e32_init(&pfllobjs->lut_prog_master_mask, NULL); | 159 | boardobjgrpmask_e32_init(&pfllobjs->lut_prog_master_mask, NULL); |
158 | 160 | ||
159 | status = devinit_get_fll_device_table(g, pfllobjs); | 161 | status = devinit_get_fll_device_table(g, pfllobjs); |
160 | if (status) | 162 | if (status) { |
161 | goto done; | 163 | goto done; |
164 | } | ||
162 | 165 | ||
163 | status = BOARDOBJGRP_PMU_CMD_GRP_GET_STATUS_CONSTRUCT(g, | 166 | status = BOARDOBJGRP_PMU_CMD_GRP_GET_STATUS_CONSTRUCT(g, |
164 | &g->clk_pmu.avfs_fllobjs.super.super, | 167 | &g->clk_pmu.avfs_fllobjs.super.super, |
@@ -215,8 +218,9 @@ u32 clk_fll_pmu_setup(struct gk20a *g) | |||
215 | 218 | ||
216 | pboardobjgrp = &g->clk_pmu.avfs_fllobjs.super.super; | 219 | pboardobjgrp = &g->clk_pmu.avfs_fllobjs.super.super; |
217 | 220 | ||
218 | if (!pboardobjgrp->bconstructed) | 221 | if (!pboardobjgrp->bconstructed) { |
219 | return -EINVAL; | 222 | return -EINVAL; |
223 | } | ||
220 | 224 | ||
221 | status = pboardobjgrp->pmuinithandle(g, pboardobjgrp); | 225 | status = pboardobjgrp->pmuinithandle(g, pboardobjgrp); |
222 | 226 | ||
@@ -252,18 +256,20 @@ static u32 devinit_get_fll_device_table(struct gk20a *g, | |||
252 | 256 | ||
253 | memcpy(&fll_desc_table_header_sz, fll_table_ptr, | 257 | memcpy(&fll_desc_table_header_sz, fll_table_ptr, |
254 | sizeof(struct fll_descriptor_header)); | 258 | sizeof(struct fll_descriptor_header)); |
255 | if (fll_desc_table_header_sz.size >= FLL_DESCRIPTOR_HEADER_10_SIZE_6) | 259 | if (fll_desc_table_header_sz.size >= FLL_DESCRIPTOR_HEADER_10_SIZE_6) { |
256 | desctablesize = FLL_DESCRIPTOR_HEADER_10_SIZE_6; | 260 | desctablesize = FLL_DESCRIPTOR_HEADER_10_SIZE_6; |
257 | else | 261 | } else { |
258 | desctablesize = FLL_DESCRIPTOR_HEADER_10_SIZE_4; | 262 | desctablesize = FLL_DESCRIPTOR_HEADER_10_SIZE_4; |
263 | } | ||
259 | 264 | ||
260 | memcpy(&fll_desc_table_header, fll_table_ptr, desctablesize); | 265 | memcpy(&fll_desc_table_header, fll_table_ptr, desctablesize); |
261 | 266 | ||
262 | if (desctablesize == FLL_DESCRIPTOR_HEADER_10_SIZE_6) | 267 | if (desctablesize == FLL_DESCRIPTOR_HEADER_10_SIZE_6) { |
263 | pfllobjs->max_min_freq_mhz = | 268 | pfllobjs->max_min_freq_mhz = |
264 | fll_desc_table_header.max_min_freq_mhz; | 269 | fll_desc_table_header.max_min_freq_mhz; |
265 | else | 270 | } else { |
266 | pfllobjs->max_min_freq_mhz = 0; | 271 | pfllobjs->max_min_freq_mhz = 0; |
272 | } | ||
267 | 273 | ||
268 | /* Read table entries*/ | 274 | /* Read table entries*/ |
269 | fll_tbl_entry_ptr = fll_table_ptr + desctablesize; | 275 | fll_tbl_entry_ptr = fll_table_ptr + desctablesize; |
@@ -273,18 +279,20 @@ static u32 devinit_get_fll_device_table(struct gk20a *g, | |||
273 | memcpy(&fll_desc_table_entry, fll_tbl_entry_ptr, | 279 | memcpy(&fll_desc_table_entry, fll_tbl_entry_ptr, |
274 | sizeof(struct fll_descriptor_entry_10)); | 280 | sizeof(struct fll_descriptor_entry_10)); |
275 | 281 | ||
276 | if (fll_desc_table_entry.fll_device_type == CTRL_CLK_FLL_TYPE_DISABLED) | 282 | if (fll_desc_table_entry.fll_device_type == CTRL_CLK_FLL_TYPE_DISABLED) { |
277 | continue; | 283 | continue; |
284 | } | ||
278 | 285 | ||
279 | fll_id = fll_desc_table_entry.fll_device_id; | 286 | fll_id = fll_desc_table_entry.fll_device_id; |
280 | 287 | ||
281 | if ( (u8)fll_desc_table_entry.vin_idx_logic != CTRL_CLK_VIN_ID_UNDEFINED) { | 288 | if ( (u8)fll_desc_table_entry.vin_idx_logic != CTRL_CLK_VIN_ID_UNDEFINED) { |
282 | pvin_dev = CLK_GET_VIN_DEVICE(pvinobjs, | 289 | pvin_dev = CLK_GET_VIN_DEVICE(pvinobjs, |
283 | (u8)fll_desc_table_entry.vin_idx_logic); | 290 | (u8)fll_desc_table_entry.vin_idx_logic); |
284 | if (pvin_dev == NULL) | 291 | if (pvin_dev == NULL) { |
285 | return -EINVAL; | 292 | return -EINVAL; |
286 | else | 293 | } else { |
287 | pvin_dev->flls_shared_mask |= BIT(fll_id); | 294 | pvin_dev->flls_shared_mask |= BIT(fll_id); |
295 | } | ||
288 | } else { | 296 | } else { |
289 | /* Return if Logic ADC device index is invalid*/ | 297 | /* Return if Logic ADC device index is invalid*/ |
290 | nvgpu_err(g, "Invalid Logic ADC specified for Nafll ID"); | 298 | nvgpu_err(g, "Invalid Logic ADC specified for Nafll ID"); |
@@ -298,14 +306,16 @@ static u32 devinit_get_fll_device_table(struct gk20a *g, | |||
298 | if ( (u8)fll_desc_table_entry.vin_idx_sram != CTRL_CLK_VIN_ID_UNDEFINED) { | 306 | if ( (u8)fll_desc_table_entry.vin_idx_sram != CTRL_CLK_VIN_ID_UNDEFINED) { |
299 | pvin_dev = CLK_GET_VIN_DEVICE(pvinobjs, | 307 | pvin_dev = CLK_GET_VIN_DEVICE(pvinobjs, |
300 | (u8)fll_desc_table_entry.vin_idx_sram); | 308 | (u8)fll_desc_table_entry.vin_idx_sram); |
301 | if (pvin_dev == NULL) | 309 | if (pvin_dev == NULL) { |
302 | return -EINVAL; | 310 | return -EINVAL; |
303 | else | 311 | } else { |
304 | pvin_dev->flls_shared_mask |= BIT(fll_id); | 312 | pvin_dev->flls_shared_mask |= BIT(fll_id); |
313 | } | ||
305 | } else { | 314 | } else { |
306 | /* Make sure VSELECT mode is set correctly to _LOGIC*/ | 315 | /* Make sure VSELECT mode is set correctly to _LOGIC*/ |
307 | if (fll_dev_data.lut_device.vselect_mode != CTRL_CLK_FLL_LUT_VSELECT_LOGIC) | 316 | if (fll_dev_data.lut_device.vselect_mode != CTRL_CLK_FLL_LUT_VSELECT_LOGIC) { |
308 | return -EINVAL; | 317 | return -EINVAL; |
318 | } | ||
309 | } | 319 | } |
310 | 320 | ||
311 | fll_dev_data.super.type = | 321 | fll_dev_data.super.type = |
@@ -357,25 +367,27 @@ done: | |||
357 | 367 | ||
358 | u32 nvgpu_clk_get_vbios_clk_domain_gv10x( u32 vbios_domain) | 368 | u32 nvgpu_clk_get_vbios_clk_domain_gv10x( u32 vbios_domain) |
359 | { | 369 | { |
360 | if (vbios_domain == 0) | 370 | if (vbios_domain == 0) { |
361 | return CTRL_CLK_DOMAIN_GPCCLK; | 371 | return CTRL_CLK_DOMAIN_GPCCLK; |
362 | else if (vbios_domain == 1) | 372 | } else if (vbios_domain == 1) { |
363 | return CTRL_CLK_DOMAIN_XBARCLK; | 373 | return CTRL_CLK_DOMAIN_XBARCLK; |
364 | else if (vbios_domain == 3) | 374 | } else if (vbios_domain == 3) { |
365 | return CTRL_CLK_DOMAIN_SYSCLK; | 375 | return CTRL_CLK_DOMAIN_SYSCLK; |
366 | else if (vbios_domain == 5) | 376 | } else if (vbios_domain == 5) { |
367 | return CTRL_CLK_DOMAIN_NVDCLK; | 377 | return CTRL_CLK_DOMAIN_NVDCLK; |
378 | } | ||
368 | return 0; | 379 | return 0; |
369 | } | 380 | } |
370 | 381 | ||
371 | u32 nvgpu_clk_get_vbios_clk_domain_gp10x( u32 vbios_domain) | 382 | u32 nvgpu_clk_get_vbios_clk_domain_gp10x( u32 vbios_domain) |
372 | { | 383 | { |
373 | if (vbios_domain == 0) | 384 | if (vbios_domain == 0) { |
374 | return CTRL_CLK_DOMAIN_GPC2CLK; | 385 | return CTRL_CLK_DOMAIN_GPC2CLK; |
375 | else if (vbios_domain == 1) | 386 | } else if (vbios_domain == 1) { |
376 | return CTRL_CLK_DOMAIN_XBAR2CLK; | 387 | return CTRL_CLK_DOMAIN_XBAR2CLK; |
377 | else if (vbios_domain == 3) | 388 | } else if (vbios_domain == 3) { |
378 | return CTRL_CLK_DOMAIN_SYS2CLK; | 389 | return CTRL_CLK_DOMAIN_SYS2CLK; |
390 | } | ||
379 | return 0; | 391 | return 0; |
380 | } | 392 | } |
381 | 393 | ||
@@ -384,8 +396,9 @@ static u32 lutbroadcastslaveregister(struct gk20a *g, | |||
384 | struct fll_device *pfll, | 396 | struct fll_device *pfll, |
385 | struct fll_device *pfll_slave) | 397 | struct fll_device *pfll_slave) |
386 | { | 398 | { |
387 | if (pfll->clk_domain != pfll_slave->clk_domain) | 399 | if (pfll->clk_domain != pfll_slave->clk_domain) { |
388 | return -EINVAL; | 400 | return -EINVAL; |
401 | } | ||
389 | 402 | ||
390 | return boardobjgrpmask_bitset(&pfll-> | 403 | return boardobjgrpmask_bitset(&pfll-> |
391 | lut_prog_broadcast_slave_mask.super, | 404 | lut_prog_broadcast_slave_mask.super, |
@@ -403,8 +416,9 @@ static struct fll_device *construct_fll_device(struct gk20a *g, | |||
403 | nvgpu_log_info(g, " "); | 416 | nvgpu_log_info(g, " "); |
404 | status = boardobj_construct_super(g, &board_obj_ptr, | 417 | status = boardobj_construct_super(g, &board_obj_ptr, |
405 | sizeof(struct fll_device), pargs); | 418 | sizeof(struct fll_device), pargs); |
406 | if (status) | 419 | if (status) { |
407 | return NULL; | 420 | return NULL; |
421 | } | ||
408 | 422 | ||
409 | pfll_dev = (struct fll_device *)pargs; | 423 | pfll_dev = (struct fll_device *)pargs; |
410 | board_obj_fll_ptr = (struct fll_device *)board_obj_ptr; | 424 | board_obj_fll_ptr = (struct fll_device *)board_obj_ptr; |
@@ -446,8 +460,9 @@ static u32 fll_device_init_pmudata_super(struct gk20a *g, | |||
446 | nvgpu_log_info(g, " "); | 460 | nvgpu_log_info(g, " "); |
447 | 461 | ||
448 | status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata); | 462 | status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata); |
449 | if (status != 0) | 463 | if (status != 0) { |
450 | return status; | 464 | return status; |
465 | } | ||
451 | 466 | ||
452 | pfll_dev = (struct fll_device *)board_obj_ptr; | 467 | pfll_dev = (struct fll_device *)board_obj_ptr; |
453 | perf_pmu_data = (struct nv_pmu_clk_clk_fll_device_boardobj_set *) | 468 | perf_pmu_data = (struct nv_pmu_clk_clk_fll_device_boardobj_set *) |
diff --git a/drivers/gpu/nvgpu/clk/clk_freq_controller.c b/drivers/gpu/nvgpu/clk/clk_freq_controller.c index 9091f71b..aa2a3a54 100644 --- a/drivers/gpu/nvgpu/clk/clk_freq_controller.c +++ b/drivers/gpu/nvgpu/clk/clk_freq_controller.c | |||
@@ -41,8 +41,9 @@ static u32 clk_freq_controller_pmudatainit_super(struct gk20a *g, | |||
41 | u32 status = 0; | 41 | u32 status = 0; |
42 | 42 | ||
43 | status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata); | 43 | status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata); |
44 | if (status) | 44 | if (status) { |
45 | return status; | 45 | return status; |
46 | } | ||
46 | 47 | ||
47 | pfreq_cntlr_set = | 48 | pfreq_cntlr_set = |
48 | (struct nv_pmu_clk_clk_freq_controller_boardobj_set *)ppmudata; | 49 | (struct nv_pmu_clk_clk_freq_controller_boardobj_set *)ppmudata; |
@@ -73,8 +74,9 @@ static u32 clk_freq_controller_pmudatainit_pi(struct gk20a *g, | |||
73 | 74 | ||
74 | status = clk_freq_controller_pmudatainit_super(g, | 75 | status = clk_freq_controller_pmudatainit_super(g, |
75 | board_obj_ptr, ppmudata); | 76 | board_obj_ptr, ppmudata); |
76 | if (status) | 77 | if (status) { |
77 | return -1; | 78 | return -1; |
79 | } | ||
78 | 80 | ||
79 | pfreq_cntlr_pi_set = | 81 | pfreq_cntlr_pi_set = |
80 | (struct nv_pmu_clk_clk_freq_controller_pi_boardobj_set *) | 82 | (struct nv_pmu_clk_clk_freq_controller_pi_boardobj_set *) |
@@ -101,8 +103,9 @@ static u32 clk_freq_controller_construct_super(struct gk20a *g, | |||
101 | u32 status = 0; | 103 | u32 status = 0; |
102 | 104 | ||
103 | status = boardobj_construct_super(g, ppboardobj, size, pargs); | 105 | status = boardobj_construct_super(g, ppboardobj, size, pargs); |
104 | if (status) | 106 | if (status) { |
105 | return -EINVAL; | 107 | return -EINVAL; |
108 | } | ||
106 | 109 | ||
107 | pfreq_cntlr_tmp = (struct clk_freq_controller *)pargs; | 110 | pfreq_cntlr_tmp = (struct clk_freq_controller *)pargs; |
108 | pfreq_cntlr = (struct clk_freq_controller *)*ppboardobj; | 111 | pfreq_cntlr = (struct clk_freq_controller *)*ppboardobj; |
@@ -132,8 +135,9 @@ static u32 clk_freq_controller_construct_pi(struct gk20a *g, | |||
132 | 135 | ||
133 | status = clk_freq_controller_construct_super(g, ppboardobj, | 136 | status = clk_freq_controller_construct_super(g, ppboardobj, |
134 | size, pargs); | 137 | size, pargs); |
135 | if (status) | 138 | if (status) { |
136 | return -EINVAL; | 139 | return -EINVAL; |
140 | } | ||
137 | 141 | ||
138 | pfreq_cntlr_pi = (struct clk_freq_controller_pi *)*ppboardobj; | 142 | pfreq_cntlr_pi = (struct clk_freq_controller_pi *)*ppboardobj; |
139 | pfreq_cntlr_pi_tmp = (struct clk_freq_controller_pi *)pargs; | 143 | pfreq_cntlr_pi_tmp = (struct clk_freq_controller_pi *)pargs; |
@@ -159,13 +163,15 @@ static struct clk_freq_controller *clk_clk_freq_controller_construct( | |||
159 | struct boardobj *board_obj_ptr = NULL; | 163 | struct boardobj *board_obj_ptr = NULL; |
160 | u32 status = 0; | 164 | u32 status = 0; |
161 | 165 | ||
162 | if (BOARDOBJ_GET_TYPE(pargs) != CTRL_CLK_CLK_FREQ_CONTROLLER_TYPE_PI) | 166 | if (BOARDOBJ_GET_TYPE(pargs) != CTRL_CLK_CLK_FREQ_CONTROLLER_TYPE_PI) { |
163 | return NULL; | 167 | return NULL; |
168 | } | ||
164 | 169 | ||
165 | status = clk_freq_controller_construct_pi(g, &board_obj_ptr, | 170 | status = clk_freq_controller_construct_pi(g, &board_obj_ptr, |
166 | sizeof(struct clk_freq_controller_pi), pargs); | 171 | sizeof(struct clk_freq_controller_pi), pargs); |
167 | if (status) | 172 | if (status) { |
168 | return NULL; | 173 | return NULL; |
174 | } | ||
169 | 175 | ||
170 | return (struct clk_freq_controller *)board_obj_ptr; | 176 | return (struct clk_freq_controller *)board_obj_ptr; |
171 | } | 177 | } |
@@ -222,8 +228,9 @@ static u32 clk_get_freq_controller_table(struct gk20a *g, | |||
222 | sizeof(struct vbios_fct_1x_entry)); | 228 | sizeof(struct vbios_fct_1x_entry)); |
223 | 229 | ||
224 | if (!BIOS_GET_FIELD(entry.flags0, | 230 | if (!BIOS_GET_FIELD(entry.flags0, |
225 | NV_VBIOS_FCT_1X_ENTRY_FLAGS0_TYPE)) | 231 | NV_VBIOS_FCT_1X_ENTRY_FLAGS0_TYPE)) { |
226 | continue; | 232 | continue; |
233 | } | ||
227 | 234 | ||
228 | freq_controller_data.board_obj.type = (u8)BIOS_GET_FIELD( | 235 | freq_controller_data.board_obj.type = (u8)BIOS_GET_FIELD( |
229 | entry.flags0, NV_VBIOS_FCT_1X_ENTRY_FLAGS0_TYPE); | 236 | entry.flags0, NV_VBIOS_FCT_1X_ENTRY_FLAGS0_TYPE); |
@@ -286,8 +293,9 @@ static u32 clk_get_freq_controller_table(struct gk20a *g, | |||
286 | NV_VBIOS_FCT_1X_ENTRY_PARAM8_FREQ_HYST_NEG); | 293 | NV_VBIOS_FCT_1X_ENTRY_PARAM8_FREQ_HYST_NEG); |
287 | 294 | ||
288 | if (ptmp_freq_cntr_pi->volt_delta_max < | 295 | if (ptmp_freq_cntr_pi->volt_delta_max < |
289 | ptmp_freq_cntr_pi->volt_delta_min) | 296 | ptmp_freq_cntr_pi->volt_delta_min) { |
290 | goto done; | 297 | goto done; |
298 | } | ||
291 | 299 | ||
292 | pclk_freq_cntr = clk_clk_freq_controller_construct(g, | 300 | pclk_freq_cntr = clk_clk_freq_controller_construct(g, |
293 | (void *)&freq_controller_data); | 301 | (void *)&freq_controller_data); |
@@ -325,8 +333,9 @@ u32 clk_freq_controller_pmu_setup(struct gk20a *g) | |||
325 | 333 | ||
326 | pboardobjgrp = &g->clk_pmu.clk_freq_controllers.super.super; | 334 | pboardobjgrp = &g->clk_pmu.clk_freq_controllers.super.super; |
327 | 335 | ||
328 | if (!pboardobjgrp->bconstructed) | 336 | if (!pboardobjgrp->bconstructed) { |
329 | return -EINVAL; | 337 | return -EINVAL; |
338 | } | ||
330 | 339 | ||
331 | status = pboardobjgrp->pmuinithandle(g, pboardobjgrp); | 340 | status = pboardobjgrp->pmuinithandle(g, pboardobjgrp); |
332 | 341 | ||
@@ -347,8 +356,9 @@ static u32 _clk_freq_controller_devgrp_pmudata_instget(struct gk20a *g, | |||
347 | 356 | ||
348 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ | 357 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ |
349 | if (((u32)BIT(idx) & | 358 | if (((u32)BIT(idx) & |
350 | pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0) | 359 | pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0) { |
351 | return -EINVAL; | 360 | return -EINVAL; |
361 | } | ||
352 | 362 | ||
353 | *ppboardobjpmudata = (struct nv_pmu_boardobj *) | 363 | *ppboardobjpmudata = (struct nv_pmu_boardobj *) |
354 | &pgrp_set->objects[idx].data.board_obj; | 364 | &pgrp_set->objects[idx].data.board_obj; |
diff --git a/drivers/gpu/nvgpu/clk/clk_prog.c b/drivers/gpu/nvgpu/clk/clk_prog.c index 8926b9f5..5966d64a 100644 --- a/drivers/gpu/nvgpu/clk/clk_prog.c +++ b/drivers/gpu/nvgpu/clk/clk_prog.c | |||
@@ -76,8 +76,9 @@ static u32 _clk_progs_pmudata_instget(struct gk20a *g, | |||
76 | 76 | ||
77 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ | 77 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ |
78 | if (((u32)BIT(idx) & | 78 | if (((u32)BIT(idx) & |
79 | pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0) | 79 | pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0) { |
80 | return -EINVAL; | 80 | return -EINVAL; |
81 | } | ||
81 | 82 | ||
82 | *ppboardobjpmudata = (struct nv_pmu_boardobj *) | 83 | *ppboardobjpmudata = (struct nv_pmu_boardobj *) |
83 | &pgrp_set->objects[idx].data.board_obj; | 84 | &pgrp_set->objects[idx].data.board_obj; |
@@ -119,8 +120,9 @@ u32 clk_prog_sw_setup(struct gk20a *g) | |||
119 | pboardobjgrp->pmudatainstget = _clk_progs_pmudata_instget; | 120 | pboardobjgrp->pmudatainstget = _clk_progs_pmudata_instget; |
120 | 121 | ||
121 | status = devinit_get_clk_prog_table(g, pclkprogobjs); | 122 | status = devinit_get_clk_prog_table(g, pclkprogobjs); |
122 | if (status) | 123 | if (status) { |
123 | goto done; | 124 | goto done; |
125 | } | ||
124 | 126 | ||
125 | status = clk_domain_clk_prog_link(g, &g->clk_pmu); | 127 | status = clk_domain_clk_prog_link(g, &g->clk_pmu); |
126 | if (status) { | 128 | if (status) { |
@@ -143,8 +145,9 @@ u32 clk_prog_pmu_setup(struct gk20a *g) | |||
143 | 145 | ||
144 | pboardobjgrp = &g->clk_pmu.clk_progobjs.super.super; | 146 | pboardobjgrp = &g->clk_pmu.clk_progobjs.super.super; |
145 | 147 | ||
146 | if (!pboardobjgrp->bconstructed) | 148 | if (!pboardobjgrp->bconstructed) { |
147 | return -EINVAL; | 149 | return -EINVAL; |
150 | } | ||
148 | 151 | ||
149 | status = pboardobjgrp->pmuinithandle(g, pboardobjgrp); | 152 | status = pboardobjgrp->pmuinithandle(g, pboardobjgrp); |
150 | 153 | ||
@@ -202,11 +205,11 @@ static u32 devinit_get_clk_prog_table(struct gk20a *g, | |||
202 | } | 205 | } |
203 | hszfmt = header.header_size; | 206 | hszfmt = header.header_size; |
204 | 207 | ||
205 | if (header.entry_size <= VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_SIZE_05) | 208 | if (header.entry_size <= VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_SIZE_05) { |
206 | szfmt = header.entry_size; | 209 | szfmt = header.entry_size; |
207 | else if (header.entry_size <= VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_SIZE_0D) | 210 | } else if (header.entry_size <= VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_SIZE_0D) { |
208 | szfmt = header.entry_size; | 211 | szfmt = header.entry_size; |
209 | else { | 212 | } else { |
210 | status = -EINVAL; | 213 | status = -EINVAL; |
211 | goto done; | 214 | goto done; |
212 | } | 215 | } |
@@ -399,8 +402,9 @@ static u32 _clk_prog_pmudatainit_1x(struct gk20a *g, | |||
399 | nvgpu_log_info(g, " "); | 402 | nvgpu_log_info(g, " "); |
400 | 403 | ||
401 | status = _clk_prog_pmudatainit_super(g, board_obj_ptr, ppmudata); | 404 | status = _clk_prog_pmudatainit_super(g, board_obj_ptr, ppmudata); |
402 | if (status != 0) | 405 | if (status != 0) { |
403 | return status; | 406 | return status; |
407 | } | ||
404 | 408 | ||
405 | pclk_prog_1x = (struct clk_prog_1x *)board_obj_ptr; | 409 | pclk_prog_1x = (struct clk_prog_1x *)board_obj_ptr; |
406 | 410 | ||
@@ -458,8 +462,9 @@ static u32 _clk_prog_pmudatainit_1x_master_ratio(struct gk20a *g, | |||
458 | nvgpu_log_info(g, " "); | 462 | nvgpu_log_info(g, " "); |
459 | 463 | ||
460 | status = _clk_prog_pmudatainit_1x_master(g, board_obj_ptr, ppmudata); | 464 | status = _clk_prog_pmudatainit_1x_master(g, board_obj_ptr, ppmudata); |
461 | if (status != 0) | 465 | if (status != 0) { |
462 | return status; | 466 | return status; |
467 | } | ||
463 | 468 | ||
464 | pclk_prog_1x_master_ratio = | 469 | pclk_prog_1x_master_ratio = |
465 | (struct clk_prog_1x_master_ratio *)board_obj_ptr; | 470 | (struct clk_prog_1x_master_ratio *)board_obj_ptr; |
@@ -486,8 +491,9 @@ static u32 _clk_prog_pmudatainit_1x_master_table(struct gk20a *g, | |||
486 | nvgpu_log_info(g, " "); | 491 | nvgpu_log_info(g, " "); |
487 | 492 | ||
488 | status = _clk_prog_pmudatainit_1x_master(g, board_obj_ptr, ppmudata); | 493 | status = _clk_prog_pmudatainit_1x_master(g, board_obj_ptr, ppmudata); |
489 | if (status != 0) | 494 | if (status != 0) { |
490 | return status; | 495 | return status; |
496 | } | ||
491 | 497 | ||
492 | pclk_prog_1x_master_table = | 498 | pclk_prog_1x_master_table = |
493 | (struct clk_prog_1x_master_table *)board_obj_ptr; | 499 | (struct clk_prog_1x_master_table *)board_obj_ptr; |
@@ -521,8 +527,9 @@ static u32 _clk_prog_1x_master_rail_construct_vf_point(struct gk20a *g, | |||
521 | &pclk->clk_vf_pointobjs.super.super, | 527 | &pclk->clk_vf_pointobjs.super.super, |
522 | &p_vf_point->super, | 528 | &p_vf_point->super, |
523 | *p_vf_point_idx); | 529 | *p_vf_point_idx); |
524 | if (status) | 530 | if (status) { |
525 | goto done; | 531 | goto done; |
532 | } | ||
526 | 533 | ||
527 | p_vf_rail->vf_point_idx_last = (*p_vf_point_idx)++; | 534 | p_vf_rail->vf_point_idx_last = (*p_vf_point_idx)++; |
528 | 535 | ||
@@ -540,8 +547,9 @@ static u32 clk_prog_construct_super(struct gk20a *g, | |||
540 | 547 | ||
541 | status = boardobj_construct_super(g, ppboardobj, | 548 | status = boardobj_construct_super(g, ppboardobj, |
542 | size, pargs); | 549 | size, pargs); |
543 | if (status) | 550 | if (status) { |
544 | return -EINVAL; | 551 | return -EINVAL; |
552 | } | ||
545 | 553 | ||
546 | pclkprog = (struct clk_prog *)*ppboardobj; | 554 | pclkprog = (struct clk_prog *)*ppboardobj; |
547 | 555 | ||
@@ -564,8 +572,9 @@ static u32 clk_prog_construct_1x(struct gk20a *g, | |||
564 | nvgpu_log_info(g, " "); | 572 | nvgpu_log_info(g, " "); |
565 | ptmpobj->type_mask |= BIT(CTRL_CLK_CLK_PROG_TYPE_1X); | 573 | ptmpobj->type_mask |= BIT(CTRL_CLK_CLK_PROG_TYPE_1X); |
566 | status = clk_prog_construct_super(g, ppboardobj, size, pargs); | 574 | status = clk_prog_construct_super(g, ppboardobj, size, pargs); |
567 | if (status) | 575 | if (status) { |
568 | return -EINVAL; | 576 | return -EINVAL; |
577 | } | ||
569 | 578 | ||
570 | pclkprog = (struct clk_prog_1x *)*ppboardobj; | 579 | pclkprog = (struct clk_prog_1x *)*ppboardobj; |
571 | 580 | ||
@@ -596,8 +605,9 @@ static u32 clk_prog_construct_1x_master(struct gk20a *g, | |||
596 | 605 | ||
597 | ptmpobj->type_mask |= BIT(CTRL_CLK_CLK_PROG_TYPE_1X_MASTER); | 606 | ptmpobj->type_mask |= BIT(CTRL_CLK_CLK_PROG_TYPE_1X_MASTER); |
598 | status = clk_prog_construct_1x(g, ppboardobj, size, pargs); | 607 | status = clk_prog_construct_1x(g, ppboardobj, size, pargs); |
599 | if (status) | 608 | if (status) { |
600 | return -EINVAL; | 609 | return -EINVAL; |
610 | } | ||
601 | 611 | ||
602 | pclkprog = (struct clk_prog_1x_master *)*ppboardobj; | 612 | pclkprog = (struct clk_prog_1x_master *)*ppboardobj; |
603 | 613 | ||
@@ -647,13 +657,15 @@ static u32 clk_prog_construct_1x_master_ratio(struct gk20a *g, | |||
647 | u32 slavesize = sizeof(struct ctrl_clk_clk_prog_1x_master_ratio_slave_entry) * | 657 | u32 slavesize = sizeof(struct ctrl_clk_clk_prog_1x_master_ratio_slave_entry) * |
648 | g->clk_pmu.clk_progobjs.slave_entry_count; | 658 | g->clk_pmu.clk_progobjs.slave_entry_count; |
649 | 659 | ||
650 | if (BOARDOBJ_GET_TYPE(pargs) != CTRL_CLK_CLK_PROG_TYPE_1X_MASTER_RATIO) | 660 | if (BOARDOBJ_GET_TYPE(pargs) != CTRL_CLK_CLK_PROG_TYPE_1X_MASTER_RATIO) { |
651 | return -EINVAL; | 661 | return -EINVAL; |
662 | } | ||
652 | 663 | ||
653 | ptmpobj->type_mask |= BIT(CTRL_CLK_CLK_PROG_TYPE_1X_MASTER_RATIO); | 664 | ptmpobj->type_mask |= BIT(CTRL_CLK_CLK_PROG_TYPE_1X_MASTER_RATIO); |
654 | status = clk_prog_construct_1x_master(g, ppboardobj, size, pargs); | 665 | status = clk_prog_construct_1x_master(g, ppboardobj, size, pargs); |
655 | if (status) | 666 | if (status) { |
656 | return -EINVAL; | 667 | return -EINVAL; |
668 | } | ||
657 | 669 | ||
658 | pclkprog = (struct clk_prog_1x_master_ratio *)*ppboardobj; | 670 | pclkprog = (struct clk_prog_1x_master_ratio *)*ppboardobj; |
659 | 671 | ||
@@ -663,8 +675,9 @@ static u32 clk_prog_construct_1x_master_ratio(struct gk20a *g, | |||
663 | pclkprog->p_slave_entries = | 675 | pclkprog->p_slave_entries = |
664 | (struct ctrl_clk_clk_prog_1x_master_ratio_slave_entry *) | 676 | (struct ctrl_clk_clk_prog_1x_master_ratio_slave_entry *) |
665 | nvgpu_kzalloc(g, slavesize); | 677 | nvgpu_kzalloc(g, slavesize); |
666 | if (!pclkprog->p_slave_entries) | 678 | if (!pclkprog->p_slave_entries) { |
667 | return -ENOMEM; | 679 | return -ENOMEM; |
680 | } | ||
668 | 681 | ||
669 | memset(pclkprog->p_slave_entries, CTRL_CLK_CLK_DOMAIN_INDEX_INVALID, | 682 | memset(pclkprog->p_slave_entries, CTRL_CLK_CLK_DOMAIN_INDEX_INVALID, |
670 | slavesize); | 683 | slavesize); |
@@ -688,13 +701,15 @@ static u32 clk_prog_construct_1x_master_table(struct gk20a *g, | |||
688 | 701 | ||
689 | nvgpu_log_info(g, "type - %x", BOARDOBJ_GET_TYPE(pargs)); | 702 | nvgpu_log_info(g, "type - %x", BOARDOBJ_GET_TYPE(pargs)); |
690 | 703 | ||
691 | if (BOARDOBJ_GET_TYPE(pargs) != CTRL_CLK_CLK_PROG_TYPE_1X_MASTER_TABLE) | 704 | if (BOARDOBJ_GET_TYPE(pargs) != CTRL_CLK_CLK_PROG_TYPE_1X_MASTER_TABLE) { |
692 | return -EINVAL; | 705 | return -EINVAL; |
706 | } | ||
693 | 707 | ||
694 | ptmpobj->type_mask |= BIT(CTRL_CLK_CLK_PROG_TYPE_1X_MASTER_TABLE); | 708 | ptmpobj->type_mask |= BIT(CTRL_CLK_CLK_PROG_TYPE_1X_MASTER_TABLE); |
695 | status = clk_prog_construct_1x_master(g, ppboardobj, size, pargs); | 709 | status = clk_prog_construct_1x_master(g, ppboardobj, size, pargs); |
696 | if (status) | 710 | if (status) { |
697 | return -EINVAL; | 711 | return -EINVAL; |
712 | } | ||
698 | 713 | ||
699 | pclkprog = (struct clk_prog_1x_master_table *)*ppboardobj; | 714 | pclkprog = (struct clk_prog_1x_master_table *)*ppboardobj; |
700 | 715 | ||
@@ -716,8 +731,9 @@ static u32 clk_prog_construct_1x_master_table(struct gk20a *g, | |||
716 | memcpy(pclkprog->p_slave_entries, ptmpprog->p_slave_entries, slavesize); | 731 | memcpy(pclkprog->p_slave_entries, ptmpprog->p_slave_entries, slavesize); |
717 | 732 | ||
718 | exit: | 733 | exit: |
719 | if (status) | 734 | if (status) { |
720 | (*ppboardobj)->destruct(*ppboardobj); | 735 | (*ppboardobj)->destruct(*ppboardobj); |
736 | } | ||
721 | 737 | ||
722 | return status; | 738 | return status; |
723 | } | 739 | } |
@@ -749,8 +765,9 @@ static struct clk_prog *construct_clk_prog(struct gk20a *g, void *pargs) | |||
749 | } | 765 | } |
750 | 766 | ||
751 | if (status) { | 767 | if (status) { |
752 | if (board_obj_ptr) | 768 | if (board_obj_ptr) { |
753 | board_obj_ptr->destruct(board_obj_ptr); | 769 | board_obj_ptr->destruct(board_obj_ptr); |
770 | } | ||
754 | return NULL; | 771 | return NULL; |
755 | } | 772 | } |
756 | 773 | ||
@@ -791,8 +808,9 @@ static u32 vfflatten_prog_1x_master(struct gk20a *g, | |||
791 | u8 i; | 808 | u8 i; |
792 | 809 | ||
793 | p_vf_rail = &p1xmaster->p_vf_entries[vf_rail_idx]; | 810 | p_vf_rail = &p1xmaster->p_vf_entries[vf_rail_idx]; |
794 | if (p_vf_rail->vfe_idx == CTRL_BOARDOBJ_IDX_INVALID) | 811 | if (p_vf_rail->vfe_idx == CTRL_BOARDOBJ_IDX_INVALID) { |
795 | continue; | 812 | continue; |
813 | } | ||
796 | 814 | ||
797 | p_vf_rail->vf_point_idx_first = vf_point_idx; | 815 | p_vf_rail->vf_point_idx_first = vf_point_idx; |
798 | 816 | ||
@@ -821,8 +839,9 @@ static u32 vfflatten_prog_1x_master(struct gk20a *g, | |||
821 | status = _clk_prog_1x_master_rail_construct_vf_point(g, pclk, | 839 | status = _clk_prog_1x_master_rail_construct_vf_point(g, pclk, |
822 | p1xmaster, p_vf_rail, | 840 | p1xmaster, p_vf_rail, |
823 | &vf_point_data.vf_point, &vf_point_idx); | 841 | &vf_point_data.vf_point, &vf_point_idx); |
824 | if (status) | 842 | if (status) { |
825 | goto done; | 843 | goto done; |
844 | } | ||
826 | } while (step_count-- > 0); | 845 | } while (step_count-- > 0); |
827 | break; | 846 | break; |
828 | 847 | ||
@@ -841,8 +860,9 @@ static u32 vfflatten_prog_1x_master(struct gk20a *g, | |||
841 | status = _clk_prog_1x_master_rail_construct_vf_point(g, pclk, | 860 | status = _clk_prog_1x_master_rail_construct_vf_point(g, pclk, |
842 | p1xmaster, p_vf_rail, | 861 | p1xmaster, p_vf_rail, |
843 | &vf_point_data.vf_point, &vf_point_idx); | 862 | &vf_point_data.vf_point, &vf_point_idx); |
844 | if (status) | 863 | if (status) { |
845 | goto done; | 864 | goto done; |
865 | } | ||
846 | } | 866 | } |
847 | break; | 867 | break; |
848 | } | 868 | } |
@@ -878,19 +898,22 @@ static u32 vflookup_prog_1x_master | |||
878 | int i; | 898 | int i; |
879 | struct ctrl_clk_clk_prog_1x_master_ratio_slave_entry *pslaveents; | 899 | struct ctrl_clk_clk_prog_1x_master_ratio_slave_entry *pslaveents; |
880 | 900 | ||
881 | if ((*pclkmhz != 0) && (*pvoltuv != 0)) | 901 | if ((*pclkmhz != 0) && (*pvoltuv != 0)) { |
882 | return -EINVAL; | 902 | return -EINVAL; |
903 | } | ||
883 | 904 | ||
884 | pclkprogobjs = &(pclk->clk_progobjs); | 905 | pclkprogobjs = &(pclk->clk_progobjs); |
885 | 906 | ||
886 | slaveentrycount = pclkprogobjs->slave_entry_count; | 907 | slaveentrycount = pclkprogobjs->slave_entry_count; |
887 | 908 | ||
888 | if (pclkprogobjs->vf_entry_count > | 909 | if (pclkprogobjs->vf_entry_count > |
889 | CTRL_CLK_CLK_PROG_1X_MASTER_VF_ENTRY_MAX_ENTRIES) | 910 | CTRL_CLK_CLK_PROG_1X_MASTER_VF_ENTRY_MAX_ENTRIES) { |
890 | return -EINVAL; | 911 | return -EINVAL; |
912 | } | ||
891 | 913 | ||
892 | if (rail >= pclkprogobjs->vf_entry_count) | 914 | if (rail >= pclkprogobjs->vf_entry_count) { |
893 | return -EINVAL; | 915 | return -EINVAL; |
916 | } | ||
894 | 917 | ||
895 | pvfentry = p1xmaster->p_vf_entries; | 918 | pvfentry = p1xmaster->p_vf_entries; |
896 | 919 | ||
@@ -914,12 +937,14 @@ static u32 vflookup_prog_1x_master | |||
914 | pslaveents = p1xmasterratio->p_slave_entries; | 937 | pslaveents = p1xmasterratio->p_slave_entries; |
915 | for (i = 0; i < slaveentrycount; i++) { | 938 | for (i = 0; i < slaveentrycount; i++) { |
916 | if (pslaveents->clk_dom_idx == | 939 | if (pslaveents->clk_dom_idx == |
917 | *slave_clk_domain) | 940 | *slave_clk_domain) { |
918 | break; | 941 | break; |
942 | } | ||
919 | pslaveents++; | 943 | pslaveents++; |
920 | } | 944 | } |
921 | if (i == slaveentrycount) | 945 | if (i == slaveentrycount) { |
922 | return -EINVAL; | 946 | return -EINVAL; |
947 | } | ||
923 | clkmhz = (clkmhz * 100)/pslaveents->ratio; | 948 | clkmhz = (clkmhz * 100)/pslaveents->ratio; |
924 | } else { | 949 | } else { |
925 | /* only support ratio for now */ | 950 | /* only support ratio for now */ |
@@ -944,32 +969,36 @@ static u32 vflookup_prog_1x_master | |||
944 | pvfpoint = CLK_CLK_VF_POINT_GET(pclk, | 969 | pvfpoint = CLK_CLK_VF_POINT_GET(pclk, |
945 | pvfentry->vf_point_idx_last); | 970 | pvfentry->vf_point_idx_last); |
946 | /* above range? */ | 971 | /* above range? */ |
947 | if (clkmhz > clkvfpointfreqmhzget(g, pvfpoint)) | 972 | if (clkmhz > clkvfpointfreqmhzget(g, pvfpoint)) { |
948 | return -EINVAL; | 973 | return -EINVAL; |
974 | } | ||
949 | 975 | ||
950 | for (j = pvfentry->vf_point_idx_last; | 976 | for (j = pvfentry->vf_point_idx_last; |
951 | j >= pvfentry->vf_point_idx_first; j--) { | 977 | j >= pvfentry->vf_point_idx_first; j--) { |
952 | pvfpoint = CLK_CLK_VF_POINT_GET(pclk, j); | 978 | pvfpoint = CLK_CLK_VF_POINT_GET(pclk, j); |
953 | if (clkmhz <= clkvfpointfreqmhzget(g, pvfpoint)) | 979 | if (clkmhz <= clkvfpointfreqmhzget(g, pvfpoint)) { |
954 | voltuv = clkvfpointvoltageuvget(g, pvfpoint); | 980 | voltuv = clkvfpointvoltageuvget(g, pvfpoint); |
955 | else | 981 | } else { |
956 | break; | 982 | break; |
983 | } | ||
957 | } | 984 | } |
958 | } else { /* looking for clk? */ | 985 | } else { /* looking for clk? */ |
959 | 986 | ||
960 | pvfpoint = CLK_CLK_VF_POINT_GET(pclk, | 987 | pvfpoint = CLK_CLK_VF_POINT_GET(pclk, |
961 | pvfentry->vf_point_idx_first); | 988 | pvfentry->vf_point_idx_first); |
962 | /* below range? */ | 989 | /* below range? */ |
963 | if (voltuv < clkvfpointvoltageuvget(g, pvfpoint)) | 990 | if (voltuv < clkvfpointvoltageuvget(g, pvfpoint)) { |
964 | return -EINVAL; | 991 | return -EINVAL; |
992 | } | ||
965 | 993 | ||
966 | for (j = pvfentry->vf_point_idx_first; | 994 | for (j = pvfentry->vf_point_idx_first; |
967 | j <= pvfentry->vf_point_idx_last; j++) { | 995 | j <= pvfentry->vf_point_idx_last; j++) { |
968 | pvfpoint = CLK_CLK_VF_POINT_GET(pclk, j); | 996 | pvfpoint = CLK_CLK_VF_POINT_GET(pclk, j); |
969 | if (voltuv >= clkvfpointvoltageuvget(g, pvfpoint)) | 997 | if (voltuv >= clkvfpointvoltageuvget(g, pvfpoint)) { |
970 | clkmhz = clkvfpointfreqmhzget(g, pvfpoint); | 998 | clkmhz = clkvfpointfreqmhzget(g, pvfpoint); |
971 | else | 999 | } else { |
972 | break; | 1000 | break; |
1001 | } | ||
973 | } | 1002 | } |
974 | } | 1003 | } |
975 | 1004 | ||
@@ -985,12 +1014,14 @@ static u32 vflookup_prog_1x_master | |||
985 | pslaveents = p1xmasterratio->p_slave_entries; | 1014 | pslaveents = p1xmasterratio->p_slave_entries; |
986 | for (i = 0; i < slaveentrycount; i++) { | 1015 | for (i = 0; i < slaveentrycount; i++) { |
987 | if (pslaveents->clk_dom_idx == | 1016 | if (pslaveents->clk_dom_idx == |
988 | *slave_clk_domain) | 1017 | *slave_clk_domain) { |
989 | break; | 1018 | break; |
1019 | } | ||
990 | pslaveents++; | 1020 | pslaveents++; |
991 | } | 1021 | } |
992 | if (i == slaveentrycount) | 1022 | if (i == slaveentrycount) { |
993 | return -EINVAL; | 1023 | return -EINVAL; |
1024 | } | ||
994 | clkmhz = (clkmhz * pslaveents->ratio)/100; | 1025 | clkmhz = (clkmhz * pslaveents->ratio)/100; |
995 | } else { | 1026 | } else { |
996 | /* only support ratio for now */ | 1027 | /* only support ratio for now */ |
@@ -999,8 +1030,9 @@ static u32 vflookup_prog_1x_master | |||
999 | } | 1030 | } |
1000 | *pclkmhz = clkmhz; | 1031 | *pclkmhz = clkmhz; |
1001 | *pvoltuv = voltuv; | 1032 | *pvoltuv = voltuv; |
1002 | if ((clkmhz == 0) || (voltuv == 0)) | 1033 | if ((clkmhz == 0) || (voltuv == 0)) { |
1003 | return -EINVAL; | 1034 | return -EINVAL; |
1035 | } | ||
1004 | return 0; | 1036 | return 0; |
1005 | } | 1037 | } |
1006 | 1038 | ||
@@ -1022,17 +1054,20 @@ static u32 getfpoints_prog_1x_master | |||
1022 | u8 j; | 1054 | u8 j; |
1023 | u32 fpointscount = 0; | 1055 | u32 fpointscount = 0; |
1024 | 1056 | ||
1025 | if (pfpointscount == NULL) | 1057 | if (pfpointscount == NULL) { |
1026 | return -EINVAL; | 1058 | return -EINVAL; |
1059 | } | ||
1027 | 1060 | ||
1028 | pclkprogobjs = &(pclk->clk_progobjs); | 1061 | pclkprogobjs = &(pclk->clk_progobjs); |
1029 | 1062 | ||
1030 | if (pclkprogobjs->vf_entry_count > | 1063 | if (pclkprogobjs->vf_entry_count > |
1031 | CTRL_CLK_CLK_PROG_1X_MASTER_VF_ENTRY_MAX_ENTRIES) | 1064 | CTRL_CLK_CLK_PROG_1X_MASTER_VF_ENTRY_MAX_ENTRIES) { |
1032 | return -EINVAL; | 1065 | return -EINVAL; |
1066 | } | ||
1033 | 1067 | ||
1034 | if (rail >= pclkprogobjs->vf_entry_count) | 1068 | if (rail >= pclkprogobjs->vf_entry_count) { |
1035 | return -EINVAL; | 1069 | return -EINVAL; |
1070 | } | ||
1036 | 1071 | ||
1037 | pvfentry = p1xmaster->p_vf_entries; | 1072 | pvfentry = p1xmaster->p_vf_entries; |
1038 | 1073 | ||
@@ -1045,11 +1080,13 @@ static u32 getfpoints_prog_1x_master | |||
1045 | pvfentry->vf_point_idx_first + 1; | 1080 | pvfentry->vf_point_idx_first + 1; |
1046 | 1081 | ||
1047 | /* if pointer for freq data is NULL simply return count */ | 1082 | /* if pointer for freq data is NULL simply return count */ |
1048 | if (*ppfreqpointsinmhz == NULL) | 1083 | if (*ppfreqpointsinmhz == NULL) { |
1049 | goto done; | 1084 | goto done; |
1085 | } | ||
1050 | 1086 | ||
1051 | if (fpointscount > *pfpointscount) | 1087 | if (fpointscount > *pfpointscount) { |
1052 | return -ENOMEM; | 1088 | return -ENOMEM; |
1089 | } | ||
1053 | for (j = pvfentry->vf_point_idx_first; | 1090 | for (j = pvfentry->vf_point_idx_first; |
1054 | j <= pvfentry->vf_point_idx_last; j++) { | 1091 | j <= pvfentry->vf_point_idx_last; j++) { |
1055 | pvfpoint = CLK_CLK_VF_POINT_GET(pclk, j); | 1092 | pvfpoint = CLK_CLK_VF_POINT_GET(pclk, j); |
@@ -1075,11 +1112,13 @@ static int getslaveclk_prog_1x_master(struct gk20a *g, | |||
1075 | u8 i; | 1112 | u8 i; |
1076 | struct ctrl_clk_clk_prog_1x_master_ratio_slave_entry *pslaveents; | 1113 | struct ctrl_clk_clk_prog_1x_master_ratio_slave_entry *pslaveents; |
1077 | 1114 | ||
1078 | if (pclkmhz == NULL) | 1115 | if (pclkmhz == NULL) { |
1079 | return -EINVAL; | 1116 | return -EINVAL; |
1117 | } | ||
1080 | 1118 | ||
1081 | if (masterclkmhz == 0) | 1119 | if (masterclkmhz == 0) { |
1082 | return -EINVAL; | 1120 | return -EINVAL; |
1121 | } | ||
1083 | 1122 | ||
1084 | *pclkmhz = 0; | 1123 | *pclkmhz = 0; |
1085 | pclkprogobjs = &(pclk->clk_progobjs); | 1124 | pclkprogobjs = &(pclk->clk_progobjs); |
@@ -1094,12 +1133,14 @@ static int getslaveclk_prog_1x_master(struct gk20a *g, | |||
1094 | pslaveents = p1xmasterratio->p_slave_entries; | 1133 | pslaveents = p1xmasterratio->p_slave_entries; |
1095 | for (i = 0; i < slaveentrycount; i++) { | 1134 | for (i = 0; i < slaveentrycount; i++) { |
1096 | if (pslaveents->clk_dom_idx == | 1135 | if (pslaveents->clk_dom_idx == |
1097 | slave_clk_domain) | 1136 | slave_clk_domain) { |
1098 | break; | 1137 | break; |
1138 | } | ||
1099 | pslaveents++; | 1139 | pslaveents++; |
1100 | } | 1140 | } |
1101 | if (i == slaveentrycount) | 1141 | if (i == slaveentrycount) { |
1102 | return -EINVAL; | 1142 | return -EINVAL; |
1143 | } | ||
1103 | *pclkmhz = (masterclkmhz * pslaveents->ratio)/100; | 1144 | *pclkmhz = (masterclkmhz * pslaveents->ratio)/100; |
1104 | } else { | 1145 | } else { |
1105 | /* only support ratio for now */ | 1146 | /* only support ratio for now */ |
diff --git a/drivers/gpu/nvgpu/clk/clk_vf_point.c b/drivers/gpu/nvgpu/clk/clk_vf_point.c index b459c012..5fc1d8e5 100644 --- a/drivers/gpu/nvgpu/clk/clk_vf_point.c +++ b/drivers/gpu/nvgpu/clk/clk_vf_point.c | |||
@@ -62,8 +62,9 @@ static u32 _clk_vf_points_pmudata_instget(struct gk20a *g, | |||
62 | nvgpu_log_info(g, " "); | 62 | nvgpu_log_info(g, " "); |
63 | 63 | ||
64 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ | 64 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ |
65 | if (idx >= CTRL_BOARDOBJGRP_E255_MAX_OBJECTS) | 65 | if (idx >= CTRL_BOARDOBJGRP_E255_MAX_OBJECTS) { |
66 | return -EINVAL; | 66 | return -EINVAL; |
67 | } | ||
67 | 68 | ||
68 | *ppboardobjpmudata = (struct nv_pmu_boardobj *) | 69 | *ppboardobjpmudata = (struct nv_pmu_boardobj *) |
69 | &pgrp_set->objects[idx].data.board_obj; | 70 | &pgrp_set->objects[idx].data.board_obj; |
@@ -81,8 +82,9 @@ static u32 _clk_vf_points_pmustatus_instget(struct gk20a *g, | |||
81 | pboardobjgrppmu; | 82 | pboardobjgrppmu; |
82 | 83 | ||
83 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ | 84 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ |
84 | if (idx >= CTRL_BOARDOBJGRP_E255_MAX_OBJECTS) | 85 | if (idx >= CTRL_BOARDOBJGRP_E255_MAX_OBJECTS) { |
85 | return -EINVAL; | 86 | return -EINVAL; |
87 | } | ||
86 | 88 | ||
87 | *ppboardobjpmustatus = (struct nv_pmu_boardobj_query *) | 89 | *ppboardobjpmustatus = (struct nv_pmu_boardobj_query *) |
88 | &pgrp_get_status->objects[idx].data.board_obj; | 90 | &pgrp_get_status->objects[idx].data.board_obj; |
@@ -145,8 +147,9 @@ u32 clk_vf_point_pmu_setup(struct gk20a *g) | |||
145 | 147 | ||
146 | pboardobjgrp = &g->clk_pmu.clk_vf_pointobjs.super.super; | 148 | pboardobjgrp = &g->clk_pmu.clk_vf_pointobjs.super.super; |
147 | 149 | ||
148 | if (!pboardobjgrp->bconstructed) | 150 | if (!pboardobjgrp->bconstructed) { |
149 | return -EINVAL; | 151 | return -EINVAL; |
152 | } | ||
150 | 153 | ||
151 | status = pboardobjgrp->pmuinithandle(g, pboardobjgrp); | 154 | status = pboardobjgrp->pmuinithandle(g, pboardobjgrp); |
152 | 155 | ||
@@ -165,8 +168,9 @@ static u32 clk_vf_point_construct_super(struct gk20a *g, | |||
165 | 168 | ||
166 | status = boardobj_construct_super(g, ppboardobj, | 169 | status = boardobj_construct_super(g, ppboardobj, |
167 | size, pargs); | 170 | size, pargs); |
168 | if (status) | 171 | if (status) { |
169 | return -EINVAL; | 172 | return -EINVAL; |
173 | } | ||
170 | 174 | ||
171 | pclkvfpoint = (struct clk_vf_point *)*ppboardobj; | 175 | pclkvfpoint = (struct clk_vf_point *)*ppboardobj; |
172 | 176 | ||
@@ -190,8 +194,9 @@ static u32 _clk_vf_point_pmudatainit_volt(struct gk20a *g, | |||
190 | nvgpu_log_info(g, " "); | 194 | nvgpu_log_info(g, " "); |
191 | 195 | ||
192 | status = _clk_vf_point_pmudatainit_super(g, board_obj_ptr, ppmudata); | 196 | status = _clk_vf_point_pmudatainit_super(g, board_obj_ptr, ppmudata); |
193 | if (status != 0) | 197 | if (status != 0) { |
194 | return status; | 198 | return status; |
199 | } | ||
195 | 200 | ||
196 | pclk_vf_point_volt = | 201 | pclk_vf_point_volt = |
197 | (struct clk_vf_point_volt *)board_obj_ptr; | 202 | (struct clk_vf_point_volt *)board_obj_ptr; |
@@ -217,8 +222,9 @@ static u32 _clk_vf_point_pmudatainit_freq(struct gk20a *g, | |||
217 | nvgpu_log_info(g, " "); | 222 | nvgpu_log_info(g, " "); |
218 | 223 | ||
219 | status = _clk_vf_point_pmudatainit_super(g, board_obj_ptr, ppmudata); | 224 | status = _clk_vf_point_pmudatainit_super(g, board_obj_ptr, ppmudata); |
220 | if (status != 0) | 225 | if (status != 0) { |
221 | return status; | 226 | return status; |
227 | } | ||
222 | 228 | ||
223 | pclk_vf_point_freq = | 229 | pclk_vf_point_freq = |
224 | (struct clk_vf_point_freq *)board_obj_ptr; | 230 | (struct clk_vf_point_freq *)board_obj_ptr; |
@@ -244,13 +250,15 @@ static u32 clk_vf_point_construct_volt(struct gk20a *g, | |||
244 | (struct clk_vf_point_volt *)pargs; | 250 | (struct clk_vf_point_volt *)pargs; |
245 | u32 status = 0; | 251 | u32 status = 0; |
246 | 252 | ||
247 | if (BOARDOBJ_GET_TYPE(pargs) != CTRL_CLK_CLK_VF_POINT_TYPE_VOLT) | 253 | if (BOARDOBJ_GET_TYPE(pargs) != CTRL_CLK_CLK_VF_POINT_TYPE_VOLT) { |
248 | return -EINVAL; | 254 | return -EINVAL; |
255 | } | ||
249 | 256 | ||
250 | ptmpobj->type_mask = BIT(CTRL_CLK_CLK_VF_POINT_TYPE_VOLT); | 257 | ptmpobj->type_mask = BIT(CTRL_CLK_CLK_VF_POINT_TYPE_VOLT); |
251 | status = clk_vf_point_construct_super(g, ppboardobj, size, pargs); | 258 | status = clk_vf_point_construct_super(g, ppboardobj, size, pargs); |
252 | if (status) | 259 | if (status) { |
253 | return -EINVAL; | 260 | return -EINVAL; |
261 | } | ||
254 | 262 | ||
255 | pclkvfpoint = (struct clk_vf_point_volt *)*ppboardobj; | 263 | pclkvfpoint = (struct clk_vf_point_volt *)*ppboardobj; |
256 | 264 | ||
@@ -273,13 +281,15 @@ static u32 clk_vf_point_construct_freq(struct gk20a *g, | |||
273 | (struct clk_vf_point_freq *)pargs; | 281 | (struct clk_vf_point_freq *)pargs; |
274 | u32 status = 0; | 282 | u32 status = 0; |
275 | 283 | ||
276 | if (BOARDOBJ_GET_TYPE(pargs) != CTRL_CLK_CLK_VF_POINT_TYPE_FREQ) | 284 | if (BOARDOBJ_GET_TYPE(pargs) != CTRL_CLK_CLK_VF_POINT_TYPE_FREQ) { |
277 | return -EINVAL; | 285 | return -EINVAL; |
286 | } | ||
278 | 287 | ||
279 | ptmpobj->type_mask = BIT(CTRL_CLK_CLK_VF_POINT_TYPE_FREQ); | 288 | ptmpobj->type_mask = BIT(CTRL_CLK_CLK_VF_POINT_TYPE_FREQ); |
280 | status = clk_vf_point_construct_super(g, ppboardobj, size, pargs); | 289 | status = clk_vf_point_construct_super(g, ppboardobj, size, pargs); |
281 | if (status) | 290 | if (status) { |
282 | return -EINVAL; | 291 | return -EINVAL; |
292 | } | ||
283 | 293 | ||
284 | pclkvfpoint = (struct clk_vf_point_freq *)*ppboardobj; | 294 | pclkvfpoint = (struct clk_vf_point_freq *)*ppboardobj; |
285 | 295 | ||
@@ -313,8 +323,9 @@ struct clk_vf_point *construct_clk_vf_point(struct gk20a *g, void *pargs) | |||
313 | return NULL; | 323 | return NULL; |
314 | } | 324 | } |
315 | 325 | ||
316 | if (status) | 326 | if (status) { |
317 | return NULL; | 327 | return NULL; |
328 | } | ||
318 | 329 | ||
319 | nvgpu_log_info(g, " Done"); | 330 | nvgpu_log_info(g, " Done"); |
320 | 331 | ||
@@ -332,8 +343,9 @@ static u32 _clk_vf_point_pmudatainit_super(struct gk20a *g, | |||
332 | nvgpu_log_info(g, " "); | 343 | nvgpu_log_info(g, " "); |
333 | 344 | ||
334 | status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata); | 345 | status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata); |
335 | if (status != 0) | 346 | if (status != 0) { |
336 | return status; | 347 | return status; |
348 | } | ||
337 | 349 | ||
338 | pclk_vf_point = | 350 | pclk_vf_point = |
339 | (struct clk_vf_point *)board_obj_ptr; | 351 | (struct clk_vf_point *)board_obj_ptr; |
diff --git a/drivers/gpu/nvgpu/clk/clk_vin.c b/drivers/gpu/nvgpu/clk/clk_vin.c index d57522af..1c18b662 100644 --- a/drivers/gpu/nvgpu/clk/clk_vin.c +++ b/drivers/gpu/nvgpu/clk/clk_vin.c | |||
@@ -155,8 +155,9 @@ static u32 _clk_vin_devgrp_pmudata_instget(struct gk20a *g, | |||
155 | 155 | ||
156 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ | 156 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ |
157 | if (((u32)BIT(idx) & | 157 | if (((u32)BIT(idx) & |
158 | pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0) | 158 | pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0) { |
159 | return -EINVAL; | 159 | return -EINVAL; |
160 | } | ||
160 | 161 | ||
161 | *ppboardobjpmudata = (struct nv_pmu_boardobj *) | 162 | *ppboardobjpmudata = (struct nv_pmu_boardobj *) |
162 | &pgrp_set->objects[idx].data.board_obj; | 163 | &pgrp_set->objects[idx].data.board_obj; |
@@ -175,8 +176,9 @@ static u32 _clk_vin_devgrp_pmustatus_instget(struct gk20a *g, | |||
175 | 176 | ||
176 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ | 177 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ |
177 | if (((u32)BIT(idx) & | 178 | if (((u32)BIT(idx) & |
178 | pgrp_get_status->hdr.data.super.obj_mask.super.data[0]) == 0) | 179 | pgrp_get_status->hdr.data.super.obj_mask.super.data[0]) == 0) { |
179 | return -EINVAL; | 180 | return -EINVAL; |
181 | } | ||
180 | 182 | ||
181 | *ppboardobjpmustatus = (struct nv_pmu_boardobj_query *) | 183 | *ppboardobjpmustatus = (struct nv_pmu_boardobj_query *) |
182 | &pgrp_get_status->objects[idx].data.board_obj; | 184 | &pgrp_get_status->objects[idx].data.board_obj; |
@@ -219,8 +221,9 @@ u32 clk_vin_sw_setup(struct gk20a *g) | |||
219 | pboardobjgrp->pmustatusinstget = _clk_vin_devgrp_pmustatus_instget; | 221 | pboardobjgrp->pmustatusinstget = _clk_vin_devgrp_pmustatus_instget; |
220 | 222 | ||
221 | status = devinit_get_vin_device_table(g, &g->clk_pmu.avfs_vinobjs); | 223 | status = devinit_get_vin_device_table(g, &g->clk_pmu.avfs_vinobjs); |
222 | if (status) | 224 | if (status) { |
223 | goto done; | 225 | goto done; |
226 | } | ||
224 | 227 | ||
225 | /*update vin calibration to fuse */ | 228 | /*update vin calibration to fuse */ |
226 | g->ops.pmu_ver.clk.clk_avfs_get_vin_cal_data(g, pvinobjs, pvindev); | 229 | g->ops.pmu_ver.clk.clk_avfs_get_vin_cal_data(g, pvinobjs, pvindev); |
@@ -249,8 +252,9 @@ u32 clk_vin_pmu_setup(struct gk20a *g) | |||
249 | 252 | ||
250 | pboardobjgrp = &g->clk_pmu.avfs_vinobjs.super.super; | 253 | pboardobjgrp = &g->clk_pmu.avfs_vinobjs.super.super; |
251 | 254 | ||
252 | if (!pboardobjgrp->bconstructed) | 255 | if (!pboardobjgrp->bconstructed) { |
253 | return -EINVAL; | 256 | return -EINVAL; |
257 | } | ||
254 | 258 | ||
255 | status = pboardobjgrp->pmuinithandle(g, pboardobjgrp); | 259 | status = pboardobjgrp->pmuinithandle(g, pboardobjgrp); |
256 | 260 | ||
@@ -299,8 +303,9 @@ static u32 devinit_get_vin_device_table(struct gk20a *g, | |||
299 | NV_VIN_DESC_FLAGS0_DISABLE_CONTROL); | 303 | NV_VIN_DESC_FLAGS0_DISABLE_CONTROL); |
300 | cal_type = BIOS_GET_FIELD(vin_desc_table_header.flags0, | 304 | cal_type = BIOS_GET_FIELD(vin_desc_table_header.flags0, |
301 | NV_VIN_DESC_FLAGS0_VIN_CAL_TYPE); | 305 | NV_VIN_DESC_FLAGS0_VIN_CAL_TYPE); |
302 | if(!cal_type) | 306 | if (!cal_type) { |
303 | cal_type = CTRL_CLK_VIN_CAL_TYPE_V10; | 307 | cal_type = CTRL_CLK_VIN_CAL_TYPE_V10; |
308 | } | ||
304 | 309 | ||
305 | switch (cal_type) { | 310 | switch (cal_type) { |
306 | case CTRL_CLK_VIN_CAL_TYPE_V10: | 311 | case CTRL_CLK_VIN_CAL_TYPE_V10: |
@@ -333,8 +338,9 @@ static u32 devinit_get_vin_device_table(struct gk20a *g, | |||
333 | memcpy(&vin_desc_table_entry, vin_tbl_entry_ptr, | 338 | memcpy(&vin_desc_table_entry, vin_tbl_entry_ptr, |
334 | sizeof(struct vin_descriptor_entry_10)); | 339 | sizeof(struct vin_descriptor_entry_10)); |
335 | 340 | ||
336 | if (vin_desc_table_entry.vin_device_type == CTRL_CLK_VIN_TYPE_DISABLED) | 341 | if (vin_desc_table_entry.vin_device_type == CTRL_CLK_VIN_TYPE_DISABLED) { |
337 | continue; | 342 | continue; |
343 | } | ||
338 | 344 | ||
339 | vin_device_data.boardobj.type = | 345 | vin_device_data.boardobj.type = |
340 | (u8)vin_desc_table_entry.vin_device_type; | 346 | (u8)vin_desc_table_entry.vin_device_type; |
@@ -379,13 +385,15 @@ static u32 vin_device_construct_v10(struct gk20a *g, | |||
379 | struct vin_device_v10 *ptmpvin_device_v10 = (struct vin_device_v10 *)pargs; | 385 | struct vin_device_v10 *ptmpvin_device_v10 = (struct vin_device_v10 *)pargs; |
380 | u32 status = 0; | 386 | u32 status = 0; |
381 | 387 | ||
382 | if (BOARDOBJ_GET_TYPE(pargs) != CTRL_CLK_VIN_TYPE_V10) | 388 | if (BOARDOBJ_GET_TYPE(pargs) != CTRL_CLK_VIN_TYPE_V10) { |
383 | return -EINVAL; | 389 | return -EINVAL; |
390 | } | ||
384 | 391 | ||
385 | ptmpobj->type_mask |= BIT(CTRL_CLK_VIN_TYPE_V10); | 392 | ptmpobj->type_mask |= BIT(CTRL_CLK_VIN_TYPE_V10); |
386 | status = vin_device_construct_super(g, ppboardobj, size, pargs); | 393 | status = vin_device_construct_super(g, ppboardobj, size, pargs); |
387 | if (status) | 394 | if (status) { |
388 | return -EINVAL; | 395 | return -EINVAL; |
396 | } | ||
389 | 397 | ||
390 | pvin_device_v10 = (struct vin_device_v10 *)*ppboardobj; | 398 | pvin_device_v10 = (struct vin_device_v10 *)*ppboardobj; |
391 | 399 | ||
@@ -407,13 +415,15 @@ static u32 vin_device_construct_v20(struct gk20a *g, | |||
407 | struct vin_device_v20 *ptmpvin_device_v20 = (struct vin_device_v20 *)pargs; | 415 | struct vin_device_v20 *ptmpvin_device_v20 = (struct vin_device_v20 *)pargs; |
408 | u32 status = 0; | 416 | u32 status = 0; |
409 | 417 | ||
410 | if (BOARDOBJ_GET_TYPE(pargs) != CTRL_CLK_VIN_TYPE_V20) | 418 | if (BOARDOBJ_GET_TYPE(pargs) != CTRL_CLK_VIN_TYPE_V20) { |
411 | return -EINVAL; | 419 | return -EINVAL; |
420 | } | ||
412 | 421 | ||
413 | ptmpobj->type_mask |= BIT(CTRL_CLK_VIN_TYPE_V20); | 422 | ptmpobj->type_mask |= BIT(CTRL_CLK_VIN_TYPE_V20); |
414 | status = vin_device_construct_super(g, ppboardobj, size, pargs); | 423 | status = vin_device_construct_super(g, ppboardobj, size, pargs); |
415 | if (status) | 424 | if (status) { |
416 | return -EINVAL; | 425 | return -EINVAL; |
426 | } | ||
417 | 427 | ||
418 | pvin_device_v20 = (struct vin_device_v20 *)*ppboardobj; | 428 | pvin_device_v20 = (struct vin_device_v20 *)*ppboardobj; |
419 | 429 | ||
@@ -434,8 +444,9 @@ static u32 vin_device_construct_super(struct gk20a *g, | |||
434 | u32 status = 0; | 444 | u32 status = 0; |
435 | status = boardobj_construct_super(g, ppboardobj, size, pargs); | 445 | status = boardobj_construct_super(g, ppboardobj, size, pargs); |
436 | 446 | ||
437 | if (status) | 447 | if (status) { |
438 | return -EINVAL; | 448 | return -EINVAL; |
449 | } | ||
439 | 450 | ||
440 | pvin_device = (struct vin_device *)*ppboardobj; | 451 | pvin_device = (struct vin_device *)*ppboardobj; |
441 | 452 | ||
@@ -470,8 +481,9 @@ static struct vin_device *construct_vin_device(struct gk20a *g, void *pargs) | |||
470 | return NULL; | 481 | return NULL; |
471 | }; | 482 | }; |
472 | 483 | ||
473 | if (status) | 484 | if (status) { |
474 | return NULL; | 485 | return NULL; |
486 | } | ||
475 | 487 | ||
476 | nvgpu_log_info(g, " Done"); | 488 | nvgpu_log_info(g, " Done"); |
477 | 489 | ||
@@ -491,8 +503,9 @@ static u32 vin_device_init_pmudata_v10(struct gk20a *g, | |||
491 | nvgpu_log_info(g, " "); | 503 | nvgpu_log_info(g, " "); |
492 | 504 | ||
493 | status = vin_device_init_pmudata_super(g, board_obj_ptr, ppmudata); | 505 | status = vin_device_init_pmudata_super(g, board_obj_ptr, ppmudata); |
494 | if (status != 0) | 506 | if (status != 0) { |
495 | return status; | 507 | return status; |
508 | } | ||
496 | 509 | ||
497 | pvin_dev_v20 = (struct vin_device_v20 *)board_obj_ptr; | 510 | pvin_dev_v20 = (struct vin_device_v20 *)board_obj_ptr; |
498 | perf_pmu_data = (struct nv_pmu_clk_clk_vin_device_v10_boardobj_set *) | 511 | perf_pmu_data = (struct nv_pmu_clk_clk_vin_device_v10_boardobj_set *) |
@@ -517,8 +530,9 @@ static u32 vin_device_init_pmudata_v20(struct gk20a *g, | |||
517 | nvgpu_log_info(g, " "); | 530 | nvgpu_log_info(g, " "); |
518 | 531 | ||
519 | status = vin_device_init_pmudata_super(g, board_obj_ptr, ppmudata); | 532 | status = vin_device_init_pmudata_super(g, board_obj_ptr, ppmudata); |
520 | if (status != 0) | 533 | if (status != 0) { |
521 | return status; | 534 | return status; |
535 | } | ||
522 | 536 | ||
523 | pvin_dev_v20 = (struct vin_device_v20 *)board_obj_ptr; | 537 | pvin_dev_v20 = (struct vin_device_v20 *)board_obj_ptr; |
524 | perf_pmu_data = (struct nv_pmu_clk_clk_vin_device_v20_boardobj_set *) | 538 | perf_pmu_data = (struct nv_pmu_clk_clk_vin_device_v20_boardobj_set *) |
@@ -543,8 +557,9 @@ static u32 vin_device_init_pmudata_super(struct gk20a *g, | |||
543 | nvgpu_log_info(g, " "); | 557 | nvgpu_log_info(g, " "); |
544 | 558 | ||
545 | status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata); | 559 | status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata); |
546 | if (status != 0) | 560 | if (status != 0) { |
547 | return status; | 561 | return status; |
562 | } | ||
548 | 563 | ||
549 | pvin_dev = (struct vin_device *)board_obj_ptr; | 564 | pvin_dev = (struct vin_device *)board_obj_ptr; |
550 | perf_pmu_data = (struct nv_pmu_clk_clk_vin_device_boardobj_set *) | 565 | perf_pmu_data = (struct nv_pmu_clk_clk_vin_device_boardobj_set *) |