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Diffstat (limited to 'drivers/gpu/nvgpu/clk')
-rw-r--r--drivers/gpu/nvgpu/clk/clk.c30
-rw-r--r--drivers/gpu/nvgpu/clk/clk_domain.c3
-rw-r--r--drivers/gpu/nvgpu/clk/clk_freq_controller.c3
-rw-r--r--drivers/gpu/nvgpu/clk/clk_mclk.c4
4 files changed, 28 insertions, 12 deletions
diff --git a/drivers/gpu/nvgpu/clk/clk.c b/drivers/gpu/nvgpu/clk/clk.c
index 8b36394d..c1b8d5e1 100644
--- a/drivers/gpu/nvgpu/clk/clk.c
+++ b/drivers/gpu/nvgpu/clk/clk.c
@@ -49,15 +49,19 @@ int clk_pmu_freq_controller_load(struct gk20a *g, bool bload)
49{ 49{
50 struct pmu_cmd cmd; 50 struct pmu_cmd cmd;
51 struct pmu_msg msg; 51 struct pmu_msg msg;
52 struct pmu_payload payload = { {0} }; 52 struct pmu_payload payload;
53 u32 status; 53 u32 status;
54 u32 seqdesc; 54 u32 seqdesc;
55 struct nv_pmu_clk_rpc rpccall = {0}; 55 struct nv_pmu_clk_rpc rpccall;
56 struct clkrpc_pmucmdhandler_params handler = {0}; 56 struct clkrpc_pmucmdhandler_params handler;
57 struct nv_pmu_clk_load *clkload; 57 struct nv_pmu_clk_load *clkload;
58 struct clk_freq_controllers *pclk_freq_controllers; 58 struct clk_freq_controllers *pclk_freq_controllers;
59 struct ctrl_boardobjgrp_mask_e32 *load_mask; 59 struct ctrl_boardobjgrp_mask_e32 *load_mask;
60 60
61 memset(&payload, 0, sizeof(struct pmu_payload));
62 memset(&rpccall, 0, sizeof(struct nv_pmu_clk_rpc));
63 memset(&handler, 0, sizeof(struct clkrpc_pmucmdhandler_params));
64
61 pclk_freq_controllers = &g->clk_pmu.clk_freq_controllers; 65 pclk_freq_controllers = &g->clk_pmu.clk_freq_controllers;
62 rpccall.function = NV_PMU_CLK_RPC_ID_LOAD; 66 rpccall.function = NV_PMU_CLK_RPC_ID_LOAD;
63 clkload = &rpccall.params.clk_load; 67 clkload = &rpccall.params.clk_load;
@@ -120,13 +124,17 @@ u32 clk_pmu_vin_load(struct gk20a *g)
120{ 124{
121 struct pmu_cmd cmd; 125 struct pmu_cmd cmd;
122 struct pmu_msg msg; 126 struct pmu_msg msg;
123 struct pmu_payload payload = { {0} }; 127 struct pmu_payload payload;
124 u32 status; 128 u32 status;
125 u32 seqdesc; 129 u32 seqdesc;
126 struct nv_pmu_clk_rpc rpccall = {0}; 130 struct nv_pmu_clk_rpc rpccall;
127 struct clkrpc_pmucmdhandler_params handler = {0}; 131 struct clkrpc_pmucmdhandler_params handler;
128 struct nv_pmu_clk_load *clkload; 132 struct nv_pmu_clk_load *clkload;
129 133
134 memset(&payload, 0, sizeof(struct pmu_payload));
135 memset(&rpccall, 0, sizeof(struct nv_pmu_clk_rpc));
136 memset(&handler, 0, sizeof(struct clkrpc_pmucmdhandler_params));
137
130 rpccall.function = NV_PMU_CLK_RPC_ID_LOAD; 138 rpccall.function = NV_PMU_CLK_RPC_ID_LOAD;
131 clkload = &rpccall.params.clk_load; 139 clkload = &rpccall.params.clk_load;
132 clkload->feature = NV_NV_PMU_CLK_LOAD_FEATURE_VIN; 140 clkload->feature = NV_NV_PMU_CLK_LOAD_FEATURE_VIN;
@@ -179,13 +187,17 @@ static u32 clk_pmu_vf_inject(struct gk20a *g, struct set_fll_clk *setfllclk)
179{ 187{
180 struct pmu_cmd cmd; 188 struct pmu_cmd cmd;
181 struct pmu_msg msg; 189 struct pmu_msg msg;
182 struct pmu_payload payload = { {0} }; 190 struct pmu_payload payload;
183 u32 status; 191 u32 status;
184 u32 seqdesc; 192 u32 seqdesc;
185 struct nv_pmu_clk_rpc rpccall = {0}; 193 struct nv_pmu_clk_rpc rpccall;
186 struct clkrpc_pmucmdhandler_params handler = {0}; 194 struct clkrpc_pmucmdhandler_params handler;
187 struct nv_pmu_clk_vf_change_inject *vfchange; 195 struct nv_pmu_clk_vf_change_inject *vfchange;
188 196
197 memset(&payload, 0, sizeof(struct pmu_payload));
198 memset(&rpccall, 0, sizeof(struct nv_pmu_clk_rpc));
199 memset(&handler, 0, sizeof(struct clkrpc_pmucmdhandler_params));
200
189 if ((setfllclk->gpc2clkmhz == 0) || (setfllclk->xbar2clkmhz == 0) || 201 if ((setfllclk->gpc2clkmhz == 0) || (setfllclk->xbar2clkmhz == 0) ||
190 (setfllclk->sys2clkmhz == 0) || (setfllclk->voltuv == 0)) 202 (setfllclk->sys2clkmhz == 0) || (setfllclk->voltuv == 0))
191 return -EINVAL; 203 return -EINVAL;
diff --git a/drivers/gpu/nvgpu/clk/clk_domain.c b/drivers/gpu/nvgpu/clk/clk_domain.c
index c784bdb4..84ce7371 100644
--- a/drivers/gpu/nvgpu/clk/clk_domain.c
+++ b/drivers/gpu/nvgpu/clk/clk_domain.c
@@ -31,7 +31,8 @@ static u32 devinit_get_clocks_table(struct gk20a *g,
31static u32 clk_domain_pmudatainit_super(struct gk20a *g, struct boardobj 31static u32 clk_domain_pmudatainit_super(struct gk20a *g, struct boardobj
32 *board_obj_ptr, struct nv_pmu_boardobj *ppmudata); 32 *board_obj_ptr, struct nv_pmu_boardobj *ppmudata);
33 33
34const struct vbios_clocks_table_1x_hal_clock_entry vbiosclktbl1xhalentry[] = { 34static const struct vbios_clocks_table_1x_hal_clock_entry
35 vbiosclktbl1xhalentry[] = {
35 { clkwhich_gpc2clk, true, }, 36 { clkwhich_gpc2clk, true, },
36 { clkwhich_xbar2clk, true, }, 37 { clkwhich_xbar2clk, true, },
37 { clkwhich_mclk, false, }, 38 { clkwhich_mclk, false, },
diff --git a/drivers/gpu/nvgpu/clk/clk_freq_controller.c b/drivers/gpu/nvgpu/clk/clk_freq_controller.c
index 61c8b81b..632d7b35 100644
--- a/drivers/gpu/nvgpu/clk/clk_freq_controller.c
+++ b/drivers/gpu/nvgpu/clk/clk_freq_controller.c
@@ -144,7 +144,8 @@ static u32 clk_freq_controller_construct_pi(struct gk20a *g,
144 return status; 144 return status;
145} 145}
146 146
147struct clk_freq_controller *clk_clk_freq_controller_construct(struct gk20a *g, 147static struct clk_freq_controller *clk_clk_freq_controller_construct(
148 struct gk20a *g,
148 void *pargs) 149 void *pargs)
149{ 150{
150 struct boardobj *board_obj_ptr = NULL; 151 struct boardobj *board_obj_ptr = NULL;
diff --git a/drivers/gpu/nvgpu/clk/clk_mclk.c b/drivers/gpu/nvgpu/clk/clk_mclk.c
index 690f8681..cf04c98c 100644
--- a/drivers/gpu/nvgpu/clk/clk_mclk.c
+++ b/drivers/gpu/nvgpu/clk/clk_mclk.c
@@ -2262,7 +2262,7 @@ fail_mclk_mutex:
2262int clk_mclkseq_change_mclk_gddr5(struct gk20a *g, u16 val) 2262int clk_mclkseq_change_mclk_gddr5(struct gk20a *g, u16 val)
2263{ 2263{
2264 struct clk_mclk_state *mclk; 2264 struct clk_mclk_state *mclk;
2265 struct pmu_payload payload = { {0} }; 2265 struct pmu_payload payload;
2266 struct nv_pmu_seq_cmd cmd; 2266 struct nv_pmu_seq_cmd cmd;
2267 struct nv_pmu_seq_cmd_run_script *pseq_cmd; 2267 struct nv_pmu_seq_cmd_run_script *pseq_cmd;
2268 u32 seqdesc; 2268 u32 seqdesc;
@@ -2277,6 +2277,8 @@ int clk_mclkseq_change_mclk_gddr5(struct gk20a *g, u16 val)
2277 2277
2278 gk20a_dbg_info(""); 2278 gk20a_dbg_info("");
2279 2279
2280 memset(&payload, 0, sizeof(struct pmu_payload));
2281
2280 mclk = &g->clk_pmu.clk_mclk; 2282 mclk = &g->clk_pmu.clk_mclk;
2281 2283
2282 nvgpu_mutex_acquire(&mclk->mclk_lock); 2284 nvgpu_mutex_acquire(&mclk->mclk_lock);