diff options
Diffstat (limited to 'drivers/gpu/nvgpu/clk')
-rw-r--r-- | drivers/gpu/nvgpu/clk/clk.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/clk/clk_domain.c | 56 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/clk/clk_fll.c | 28 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/clk/clk_freq_controller.c | 14 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/clk/clk_prog.c | 46 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/clk/clk_vf_point.c | 26 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/clk/clk_vin.c | 36 |
7 files changed, 105 insertions, 105 deletions
diff --git a/drivers/gpu/nvgpu/clk/clk.c b/drivers/gpu/nvgpu/clk/clk.c index ecc352b1..a8d99bbb 100644 --- a/drivers/gpu/nvgpu/clk/clk.c +++ b/drivers/gpu/nvgpu/clk/clk.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -43,7 +43,7 @@ static void clkrpc_pmucmdhandler(struct gk20a *g, struct pmu_msg *msg, | |||
43 | struct clkrpc_pmucmdhandler_params *phandlerparams = | 43 | struct clkrpc_pmucmdhandler_params *phandlerparams = |
44 | (struct clkrpc_pmucmdhandler_params *)param; | 44 | (struct clkrpc_pmucmdhandler_params *)param; |
45 | 45 | ||
46 | gk20a_dbg_info(""); | 46 | nvgpu_log_info(g, " "); |
47 | 47 | ||
48 | if (msg->msg.clk.msg_type != NV_PMU_CLK_MSG_ID_RPC) { | 48 | if (msg->msg.clk.msg_type != NV_PMU_CLK_MSG_ID_RPC) { |
49 | nvgpu_err(g, "unsupported msg for VFE LOAD RPC %x", | 49 | nvgpu_err(g, "unsupported msg for VFE LOAD RPC %x", |
diff --git a/drivers/gpu/nvgpu/clk/clk_domain.c b/drivers/gpu/nvgpu/clk/clk_domain.c index 1d47d2d5..f306cf56 100644 --- a/drivers/gpu/nvgpu/clk/clk_domain.c +++ b/drivers/gpu/nvgpu/clk/clk_domain.c | |||
@@ -153,7 +153,7 @@ static u32 _clk_domains_pmudata_instget(struct gk20a *g, | |||
153 | (struct nv_pmu_clk_clk_domain_boardobj_grp_set *) | 153 | (struct nv_pmu_clk_clk_domain_boardobj_grp_set *) |
154 | pmuboardobjgrp; | 154 | pmuboardobjgrp; |
155 | 155 | ||
156 | gk20a_dbg_info(""); | 156 | nvgpu_log_info(g, " "); |
157 | 157 | ||
158 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ | 158 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ |
159 | if (((u32)BIT(idx) & | 159 | if (((u32)BIT(idx) & |
@@ -162,7 +162,7 @@ static u32 _clk_domains_pmudata_instget(struct gk20a *g, | |||
162 | 162 | ||
163 | *ppboardobjpmudata = (struct nv_pmu_boardobj *) | 163 | *ppboardobjpmudata = (struct nv_pmu_boardobj *) |
164 | &pgrp_set->objects[idx].data.board_obj; | 164 | &pgrp_set->objects[idx].data.board_obj; |
165 | gk20a_dbg_info(" Done"); | 165 | nvgpu_log_info(g, " Done"); |
166 | return 0; | 166 | return 0; |
167 | } | 167 | } |
168 | 168 | ||
@@ -176,7 +176,7 @@ u32 clk_domain_sw_setup(struct gk20a *g) | |||
176 | struct clk_domain_3x_slave *pdomain_slave; | 176 | struct clk_domain_3x_slave *pdomain_slave; |
177 | u8 i; | 177 | u8 i; |
178 | 178 | ||
179 | gk20a_dbg_info(""); | 179 | nvgpu_log_info(g, " "); |
180 | 180 | ||
181 | status = boardobjgrpconstruct_e32(g, &g->clk_pmu.clk_domainobjs.super); | 181 | status = boardobjgrpconstruct_e32(g, &g->clk_pmu.clk_domainobjs.super); |
182 | if (status) { | 182 | if (status) { |
@@ -255,7 +255,7 @@ u32 clk_domain_sw_setup(struct gk20a *g) | |||
255 | } | 255 | } |
256 | 256 | ||
257 | done: | 257 | done: |
258 | gk20a_dbg_info(" done status %x", status); | 258 | nvgpu_log_info(g, " done status %x", status); |
259 | return status; | 259 | return status; |
260 | } | 260 | } |
261 | 261 | ||
@@ -264,7 +264,7 @@ u32 clk_domain_pmu_setup(struct gk20a *g) | |||
264 | u32 status; | 264 | u32 status; |
265 | struct boardobjgrp *pboardobjgrp = NULL; | 265 | struct boardobjgrp *pboardobjgrp = NULL; |
266 | 266 | ||
267 | gk20a_dbg_info(""); | 267 | nvgpu_log_info(g, " "); |
268 | 268 | ||
269 | pboardobjgrp = &g->clk_pmu.clk_domainobjs.super.super; | 269 | pboardobjgrp = &g->clk_pmu.clk_domainobjs.super.super; |
270 | 270 | ||
@@ -273,7 +273,7 @@ u32 clk_domain_pmu_setup(struct gk20a *g) | |||
273 | 273 | ||
274 | status = pboardobjgrp->pmuinithandle(g, pboardobjgrp); | 274 | status = pboardobjgrp->pmuinithandle(g, pboardobjgrp); |
275 | 275 | ||
276 | gk20a_dbg_info("Done"); | 276 | nvgpu_log_info(g, "Done"); |
277 | return status; | 277 | return status; |
278 | } | 278 | } |
279 | 279 | ||
@@ -298,7 +298,7 @@ static u32 devinit_get_clocks_table(struct gk20a *g, | |||
298 | struct clk_domain_3x_slave v3x_slave; | 298 | struct clk_domain_3x_slave v3x_slave; |
299 | } clk_domain_data; | 299 | } clk_domain_data; |
300 | 300 | ||
301 | gk20a_dbg_info(""); | 301 | nvgpu_log_info(g, " "); |
302 | 302 | ||
303 | clocks_table_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g, | 303 | clocks_table_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g, |
304 | g->bios.clock_token, CLOCKS_TABLE); | 304 | g->bios.clock_token, CLOCKS_TABLE); |
@@ -459,7 +459,7 @@ static u32 devinit_get_clocks_table(struct gk20a *g, | |||
459 | } | 459 | } |
460 | 460 | ||
461 | done: | 461 | done: |
462 | gk20a_dbg_info(" done status %x", status); | 462 | nvgpu_log_info(g, " done status %x", status); |
463 | return status; | 463 | return status; |
464 | } | 464 | } |
465 | 465 | ||
@@ -467,7 +467,7 @@ static u32 clkdomainclkproglink_not_supported(struct gk20a *g, | |||
467 | struct clk_pmupstate *pclk, | 467 | struct clk_pmupstate *pclk, |
468 | struct clk_domain *pdomain) | 468 | struct clk_domain *pdomain) |
469 | { | 469 | { |
470 | gk20a_dbg_info(""); | 470 | nvgpu_log_info(g, " "); |
471 | return -EINVAL; | 471 | return -EINVAL; |
472 | } | 472 | } |
473 | 473 | ||
@@ -480,7 +480,7 @@ static int clkdomainvfsearch_stub( | |||
480 | u8 rail) | 480 | u8 rail) |
481 | 481 | ||
482 | { | 482 | { |
483 | gk20a_dbg_info(""); | 483 | nvgpu_log_info(g, " "); |
484 | return -EINVAL; | 484 | return -EINVAL; |
485 | } | 485 | } |
486 | 486 | ||
@@ -492,7 +492,7 @@ static u32 clkdomaingetfpoints_stub( | |||
492 | u16 *pfreqpointsinmhz, | 492 | u16 *pfreqpointsinmhz, |
493 | u8 rail) | 493 | u8 rail) |
494 | { | 494 | { |
495 | gk20a_dbg_info(""); | 495 | nvgpu_log_info(g, " "); |
496 | return -EINVAL; | 496 | return -EINVAL; |
497 | } | 497 | } |
498 | 498 | ||
@@ -541,7 +541,7 @@ static u32 _clk_domain_pmudatainit_3x(struct gk20a *g, | |||
541 | struct clk_domain_3x *pclk_domain_3x; | 541 | struct clk_domain_3x *pclk_domain_3x; |
542 | struct nv_pmu_clk_clk_domain_3x_boardobj_set *pset; | 542 | struct nv_pmu_clk_clk_domain_3x_boardobj_set *pset; |
543 | 543 | ||
544 | gk20a_dbg_info(""); | 544 | nvgpu_log_info(g, " "); |
545 | 545 | ||
546 | status = clk_domain_pmudatainit_super(g, board_obj_ptr, ppmudata); | 546 | status = clk_domain_pmudatainit_super(g, board_obj_ptr, ppmudata); |
547 | if (status != 0) | 547 | if (status != 0) |
@@ -592,7 +592,7 @@ static u32 clkdomainclkproglink_3x_prog(struct gk20a *g, | |||
592 | struct clk_prog *pprog = NULL; | 592 | struct clk_prog *pprog = NULL; |
593 | u8 i; | 593 | u8 i; |
594 | 594 | ||
595 | gk20a_dbg_info(""); | 595 | nvgpu_log_info(g, " "); |
596 | 596 | ||
597 | for (i = p3xprog->clk_prog_idx_first; | 597 | for (i = p3xprog->clk_prog_idx_first; |
598 | i <= p3xprog->clk_prog_idx_last; | 598 | i <= p3xprog->clk_prog_idx_last; |
@@ -616,7 +616,7 @@ static int clkdomaingetslaveclk(struct gk20a *g, | |||
616 | u8 slaveidx; | 616 | u8 slaveidx; |
617 | struct clk_domain_3x_master *p3xmaster; | 617 | struct clk_domain_3x_master *p3xmaster; |
618 | 618 | ||
619 | gk20a_dbg_info(""); | 619 | nvgpu_log_info(g, " "); |
620 | 620 | ||
621 | if (pclkmhz == NULL) | 621 | if (pclkmhz == NULL) |
622 | return -EINVAL; | 622 | return -EINVAL; |
@@ -657,7 +657,7 @@ static int clkdomainvfsearch(struct gk20a *g, | |||
657 | u16 bestclkmhz; | 657 | u16 bestclkmhz; |
658 | u32 bestvoltuv; | 658 | u32 bestvoltuv; |
659 | 659 | ||
660 | gk20a_dbg_info(""); | 660 | nvgpu_log_info(g, " "); |
661 | 661 | ||
662 | if ((pclkmhz == NULL) || (pvoltuv == NULL)) | 662 | if ((pclkmhz == NULL) || (pvoltuv == NULL)) |
663 | return -EINVAL; | 663 | return -EINVAL; |
@@ -719,7 +719,7 @@ static int clkdomainvfsearch(struct gk20a *g, | |||
719 | goto done; | 719 | goto done; |
720 | } | 720 | } |
721 | done: | 721 | done: |
722 | gk20a_dbg_info("done status %x", status); | 722 | nvgpu_log_info(g, "done status %x", status); |
723 | return status; | 723 | return status; |
724 | } | 724 | } |
725 | 725 | ||
@@ -744,7 +744,7 @@ static u32 clkdomaingetfpoints | |||
744 | u16 *freqpointsdata; | 744 | u16 *freqpointsdata; |
745 | u8 i; | 745 | u8 i; |
746 | 746 | ||
747 | gk20a_dbg_info(""); | 747 | nvgpu_log_info(g, " "); |
748 | 748 | ||
749 | if (pfpointscount == NULL) | 749 | if (pfpointscount == NULL) |
750 | return -EINVAL; | 750 | return -EINVAL; |
@@ -783,7 +783,7 @@ static u32 clkdomaingetfpoints | |||
783 | 783 | ||
784 | *pfpointscount = totalcount; | 784 | *pfpointscount = totalcount; |
785 | done: | 785 | done: |
786 | gk20a_dbg_info("done status %x", status); | 786 | nvgpu_log_info(g, "done status %x", status); |
787 | return status; | 787 | return status; |
788 | } | 788 | } |
789 | 789 | ||
@@ -796,7 +796,7 @@ static u32 _clk_domain_pmudatainit_3x_prog(struct gk20a *g, | |||
796 | struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set *pset; | 796 | struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set *pset; |
797 | struct clk_domains *pdomains = &(g->clk_pmu.clk_domainobjs); | 797 | struct clk_domains *pdomains = &(g->clk_pmu.clk_domainobjs); |
798 | 798 | ||
799 | gk20a_dbg_info(""); | 799 | nvgpu_log_info(g, " "); |
800 | 800 | ||
801 | status = _clk_domain_pmudatainit_3x(g, board_obj_ptr, ppmudata); | 801 | status = _clk_domain_pmudatainit_3x(g, board_obj_ptr, ppmudata); |
802 | if (status != 0) | 802 | if (status != 0) |
@@ -876,7 +876,7 @@ static u32 _clk_domain_pmudatainit_3x_slave(struct gk20a *g, | |||
876 | struct clk_domain_3x_slave *pclk_domain_3x_slave; | 876 | struct clk_domain_3x_slave *pclk_domain_3x_slave; |
877 | struct nv_pmu_clk_clk_domain_3x_slave_boardobj_set *pset; | 877 | struct nv_pmu_clk_clk_domain_3x_slave_boardobj_set *pset; |
878 | 878 | ||
879 | gk20a_dbg_info(""); | 879 | nvgpu_log_info(g, " "); |
880 | 880 | ||
881 | status = _clk_domain_pmudatainit_3x_prog(g, board_obj_ptr, ppmudata); | 881 | status = _clk_domain_pmudatainit_3x_prog(g, board_obj_ptr, ppmudata); |
882 | if (status != 0) | 882 | if (status != 0) |
@@ -935,7 +935,7 @@ static u32 clkdomainclkproglink_3x_master(struct gk20a *g, | |||
935 | u16 freq_max_last_mhz = 0; | 935 | u16 freq_max_last_mhz = 0; |
936 | u8 i; | 936 | u8 i; |
937 | 937 | ||
938 | gk20a_dbg_info(""); | 938 | nvgpu_log_info(g, " "); |
939 | 939 | ||
940 | status = clkdomainclkproglink_3x_prog(g, pclk, pdomain); | 940 | status = clkdomainclkproglink_3x_prog(g, pclk, pdomain); |
941 | if (status) | 941 | if (status) |
@@ -961,7 +961,7 @@ static u32 clkdomainclkproglink_3x_master(struct gk20a *g, | |||
961 | goto done; | 961 | goto done; |
962 | } | 962 | } |
963 | done: | 963 | done: |
964 | gk20a_dbg_info("done status %x", status); | 964 | nvgpu_log_info(g, "done status %x", status); |
965 | return status; | 965 | return status; |
966 | } | 966 | } |
967 | 967 | ||
@@ -973,7 +973,7 @@ static u32 _clk_domain_pmudatainit_3x_master(struct gk20a *g, | |||
973 | struct clk_domain_3x_master *pclk_domain_3x_master; | 973 | struct clk_domain_3x_master *pclk_domain_3x_master; |
974 | struct nv_pmu_clk_clk_domain_3x_master_boardobj_set *pset; | 974 | struct nv_pmu_clk_clk_domain_3x_master_boardobj_set *pset; |
975 | 975 | ||
976 | gk20a_dbg_info(""); | 976 | nvgpu_log_info(g, " "); |
977 | 977 | ||
978 | status = _clk_domain_pmudatainit_3x_prog(g, board_obj_ptr, ppmudata); | 978 | status = _clk_domain_pmudatainit_3x_prog(g, board_obj_ptr, ppmudata); |
979 | if (status != 0) | 979 | if (status != 0) |
@@ -1021,7 +1021,7 @@ static u32 clkdomainclkproglink_fixed(struct gk20a *g, | |||
1021 | struct clk_pmupstate *pclk, | 1021 | struct clk_pmupstate *pclk, |
1022 | struct clk_domain *pdomain) | 1022 | struct clk_domain *pdomain) |
1023 | { | 1023 | { |
1024 | gk20a_dbg_info(""); | 1024 | nvgpu_log_info(g, " "); |
1025 | return 0; | 1025 | return 0; |
1026 | } | 1026 | } |
1027 | 1027 | ||
@@ -1033,7 +1033,7 @@ static u32 _clk_domain_pmudatainit_3x_fixed(struct gk20a *g, | |||
1033 | struct clk_domain_3x_fixed *pclk_domain_3x_fixed; | 1033 | struct clk_domain_3x_fixed *pclk_domain_3x_fixed; |
1034 | struct nv_pmu_clk_clk_domain_3x_fixed_boardobj_set *pset; | 1034 | struct nv_pmu_clk_clk_domain_3x_fixed_boardobj_set *pset; |
1035 | 1035 | ||
1036 | gk20a_dbg_info(""); | 1036 | nvgpu_log_info(g, " "); |
1037 | 1037 | ||
1038 | status = _clk_domain_pmudatainit_3x(g, board_obj_ptr, ppmudata); | 1038 | status = _clk_domain_pmudatainit_3x(g, board_obj_ptr, ppmudata); |
1039 | if (status != 0) | 1039 | if (status != 0) |
@@ -1085,7 +1085,7 @@ static struct clk_domain *construct_clk_domain(struct gk20a *g, void *pargs) | |||
1085 | struct boardobj *board_obj_ptr = NULL; | 1085 | struct boardobj *board_obj_ptr = NULL; |
1086 | u32 status; | 1086 | u32 status; |
1087 | 1087 | ||
1088 | gk20a_dbg_info(" %d", BOARDOBJ_GET_TYPE(pargs)); | 1088 | nvgpu_log_info(g, " %d", BOARDOBJ_GET_TYPE(pargs)); |
1089 | switch (BOARDOBJ_GET_TYPE(pargs)) { | 1089 | switch (BOARDOBJ_GET_TYPE(pargs)) { |
1090 | case CTRL_CLK_CLK_DOMAIN_TYPE_3X_FIXED: | 1090 | case CTRL_CLK_CLK_DOMAIN_TYPE_3X_FIXED: |
1091 | status = clk_domain_construct_3x_fixed(g, &board_obj_ptr, | 1091 | status = clk_domain_construct_3x_fixed(g, &board_obj_ptr, |
@@ -1109,7 +1109,7 @@ static struct clk_domain *construct_clk_domain(struct gk20a *g, void *pargs) | |||
1109 | if (status) | 1109 | if (status) |
1110 | return NULL; | 1110 | return NULL; |
1111 | 1111 | ||
1112 | gk20a_dbg_info(" Done"); | 1112 | nvgpu_log_info(g, " Done"); |
1113 | 1113 | ||
1114 | return (struct clk_domain *)board_obj_ptr; | 1114 | return (struct clk_domain *)board_obj_ptr; |
1115 | } | 1115 | } |
@@ -1122,7 +1122,7 @@ static u32 clk_domain_pmudatainit_super(struct gk20a *g, | |||
1122 | struct clk_domain *pclk_domain; | 1122 | struct clk_domain *pclk_domain; |
1123 | struct nv_pmu_clk_clk_domain_boardobj_set *pset; | 1123 | struct nv_pmu_clk_clk_domain_boardobj_set *pset; |
1124 | 1124 | ||
1125 | gk20a_dbg_info(""); | 1125 | nvgpu_log_info(g, " "); |
1126 | 1126 | ||
1127 | status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata); | 1127 | status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata); |
1128 | if (status != 0) | 1128 | if (status != 0) |
diff --git a/drivers/gpu/nvgpu/clk/clk_fll.c b/drivers/gpu/nvgpu/clk/clk_fll.c index 15d386d5..87222b90 100644 --- a/drivers/gpu/nvgpu/clk/clk_fll.c +++ b/drivers/gpu/nvgpu/clk/clk_fll.c | |||
@@ -50,7 +50,7 @@ static u32 _clk_fll_devgrp_pmudatainit_super(struct gk20a *g, | |||
50 | pboardobjgrp; | 50 | pboardobjgrp; |
51 | u32 status = 0; | 51 | u32 status = 0; |
52 | 52 | ||
53 | gk20a_dbg_info(""); | 53 | nvgpu_log_info(g, " "); |
54 | 54 | ||
55 | status = boardobjgrp_pmudatainit_e32(g, pboardobjgrp, pboardobjgrppmu); | 55 | status = boardobjgrp_pmudatainit_e32(g, pboardobjgrp, pboardobjgrppmu); |
56 | if (status) { | 56 | if (status) { |
@@ -67,7 +67,7 @@ static u32 _clk_fll_devgrp_pmudatainit_super(struct gk20a *g, | |||
67 | pfll_objs->lut_prog_master_mask.super.bitcount, | 67 | pfll_objs->lut_prog_master_mask.super.bitcount, |
68 | &pset->lut_prog_master_mask.super); | 68 | &pset->lut_prog_master_mask.super); |
69 | 69 | ||
70 | gk20a_dbg_info(" Done"); | 70 | nvgpu_log_info(g, " Done"); |
71 | return status; | 71 | return status; |
72 | } | 72 | } |
73 | 73 | ||
@@ -80,7 +80,7 @@ static u32 _clk_fll_devgrp_pmudata_instget(struct gk20a *g, | |||
80 | (struct nv_pmu_clk_clk_fll_device_boardobj_grp_set *) | 80 | (struct nv_pmu_clk_clk_fll_device_boardobj_grp_set *) |
81 | pmuboardobjgrp; | 81 | pmuboardobjgrp; |
82 | 82 | ||
83 | gk20a_dbg_info(""); | 83 | nvgpu_log_info(g, " "); |
84 | 84 | ||
85 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ | 85 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ |
86 | if (((u32)BIT(idx) & | 86 | if (((u32)BIT(idx) & |
@@ -89,7 +89,7 @@ static u32 _clk_fll_devgrp_pmudata_instget(struct gk20a *g, | |||
89 | 89 | ||
90 | *ppboardobjpmudata = (struct nv_pmu_boardobj *) | 90 | *ppboardobjpmudata = (struct nv_pmu_boardobj *) |
91 | &pgrp_set->objects[idx].data.board_obj; | 91 | &pgrp_set->objects[idx].data.board_obj; |
92 | gk20a_dbg_info(" Done"); | 92 | nvgpu_log_info(g, " Done"); |
93 | return 0; | 93 | return 0; |
94 | } | 94 | } |
95 | 95 | ||
@@ -123,7 +123,7 @@ u32 clk_fll_sw_setup(struct gk20a *g) | |||
123 | u8 i; | 123 | u8 i; |
124 | u8 j; | 124 | u8 j; |
125 | 125 | ||
126 | gk20a_dbg_info(""); | 126 | nvgpu_log_info(g, " "); |
127 | 127 | ||
128 | status = boardobjgrpconstruct_e32(g, &g->clk_pmu.avfs_fllobjs.super); | 128 | status = boardobjgrpconstruct_e32(g, &g->clk_pmu.avfs_fllobjs.super); |
129 | if (status) { | 129 | if (status) { |
@@ -202,7 +202,7 @@ u32 clk_fll_sw_setup(struct gk20a *g) | |||
202 | } | 202 | } |
203 | } | 203 | } |
204 | done: | 204 | done: |
205 | gk20a_dbg_info(" done status %x", status); | 205 | nvgpu_log_info(g, " done status %x", status); |
206 | return status; | 206 | return status; |
207 | } | 207 | } |
208 | 208 | ||
@@ -211,7 +211,7 @@ u32 clk_fll_pmu_setup(struct gk20a *g) | |||
211 | u32 status; | 211 | u32 status; |
212 | struct boardobjgrp *pboardobjgrp = NULL; | 212 | struct boardobjgrp *pboardobjgrp = NULL; |
213 | 213 | ||
214 | gk20a_dbg_info(""); | 214 | nvgpu_log_info(g, " "); |
215 | 215 | ||
216 | pboardobjgrp = &g->clk_pmu.avfs_fllobjs.super.super; | 216 | pboardobjgrp = &g->clk_pmu.avfs_fllobjs.super.super; |
217 | 217 | ||
@@ -220,7 +220,7 @@ u32 clk_fll_pmu_setup(struct gk20a *g) | |||
220 | 220 | ||
221 | status = pboardobjgrp->pmuinithandle(g, pboardobjgrp); | 221 | status = pboardobjgrp->pmuinithandle(g, pboardobjgrp); |
222 | 222 | ||
223 | gk20a_dbg_info("Done"); | 223 | nvgpu_log_info(g, "Done"); |
224 | return status; | 224 | return status; |
225 | } | 225 | } |
226 | 226 | ||
@@ -241,7 +241,7 @@ static u32 devinit_get_fll_device_table(struct gk20a *g, | |||
241 | u32 vbios_domain = NV_PERF_DOMAIN_4X_CLOCK_DOMAIN_SKIP; | 241 | u32 vbios_domain = NV_PERF_DOMAIN_4X_CLOCK_DOMAIN_SKIP; |
242 | struct avfsvinobjs *pvinobjs = &g->clk_pmu.avfs_vinobjs; | 242 | struct avfsvinobjs *pvinobjs = &g->clk_pmu.avfs_vinobjs; |
243 | 243 | ||
244 | gk20a_dbg_info(""); | 244 | nvgpu_log_info(g, " "); |
245 | 245 | ||
246 | fll_table_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g, | 246 | fll_table_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g, |
247 | g->bios.clock_token, FLL_TABLE); | 247 | g->bios.clock_token, FLL_TABLE); |
@@ -350,7 +350,7 @@ static u32 devinit_get_fll_device_table(struct gk20a *g, | |||
350 | } | 350 | } |
351 | 351 | ||
352 | done: | 352 | done: |
353 | gk20a_dbg_info(" done status %x", status); | 353 | nvgpu_log_info(g, " done status %x", status); |
354 | return status; | 354 | return status; |
355 | } | 355 | } |
356 | 356 | ||
@@ -399,7 +399,7 @@ static struct fll_device *construct_fll_device(struct gk20a *g, | |||
399 | struct fll_device *board_obj_fll_ptr = NULL; | 399 | struct fll_device *board_obj_fll_ptr = NULL; |
400 | u32 status; | 400 | u32 status; |
401 | 401 | ||
402 | gk20a_dbg_info(""); | 402 | nvgpu_log_info(g, " "); |
403 | status = boardobj_construct_super(g, &board_obj_ptr, | 403 | status = boardobj_construct_super(g, &board_obj_ptr, |
404 | sizeof(struct fll_device), pargs); | 404 | sizeof(struct fll_device), pargs); |
405 | if (status) | 405 | if (status) |
@@ -429,7 +429,7 @@ static struct fll_device *construct_fll_device(struct gk20a *g, | |||
429 | boardobjgrpmask_e32_init( | 429 | boardobjgrpmask_e32_init( |
430 | &board_obj_fll_ptr->lut_prog_broadcast_slave_mask, NULL); | 430 | &board_obj_fll_ptr->lut_prog_broadcast_slave_mask, NULL); |
431 | 431 | ||
432 | gk20a_dbg_info(" Done"); | 432 | nvgpu_log_info(g, " Done"); |
433 | 433 | ||
434 | return (struct fll_device *)board_obj_ptr; | 434 | return (struct fll_device *)board_obj_ptr; |
435 | } | 435 | } |
@@ -442,7 +442,7 @@ static u32 fll_device_init_pmudata_super(struct gk20a *g, | |||
442 | struct fll_device *pfll_dev; | 442 | struct fll_device *pfll_dev; |
443 | struct nv_pmu_clk_clk_fll_device_boardobj_set *perf_pmu_data; | 443 | struct nv_pmu_clk_clk_fll_device_boardobj_set *perf_pmu_data; |
444 | 444 | ||
445 | gk20a_dbg_info(""); | 445 | nvgpu_log_info(g, " "); |
446 | 446 | ||
447 | status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata); | 447 | status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata); |
448 | if (status != 0) | 448 | if (status != 0) |
@@ -473,7 +473,7 @@ static u32 fll_device_init_pmudata_super(struct gk20a *g, | |||
473 | pfll_dev->lut_prog_broadcast_slave_mask.super.bitcount, | 473 | pfll_dev->lut_prog_broadcast_slave_mask.super.bitcount, |
474 | &perf_pmu_data->lut_prog_broadcast_slave_mask.super); | 474 | &perf_pmu_data->lut_prog_broadcast_slave_mask.super); |
475 | 475 | ||
476 | gk20a_dbg_info(" Done"); | 476 | nvgpu_log_info(g, " Done"); |
477 | 477 | ||
478 | return status; | 478 | return status; |
479 | } | 479 | } |
diff --git a/drivers/gpu/nvgpu/clk/clk_freq_controller.c b/drivers/gpu/nvgpu/clk/clk_freq_controller.c index fce177a7..9091f71b 100644 --- a/drivers/gpu/nvgpu/clk/clk_freq_controller.c +++ b/drivers/gpu/nvgpu/clk/clk_freq_controller.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -321,7 +321,7 @@ u32 clk_freq_controller_pmu_setup(struct gk20a *g) | |||
321 | u32 status; | 321 | u32 status; |
322 | struct boardobjgrp *pboardobjgrp = NULL; | 322 | struct boardobjgrp *pboardobjgrp = NULL; |
323 | 323 | ||
324 | gk20a_dbg_info(""); | 324 | nvgpu_log_info(g, " "); |
325 | 325 | ||
326 | pboardobjgrp = &g->clk_pmu.clk_freq_controllers.super.super; | 326 | pboardobjgrp = &g->clk_pmu.clk_freq_controllers.super.super; |
327 | 327 | ||
@@ -330,7 +330,7 @@ u32 clk_freq_controller_pmu_setup(struct gk20a *g) | |||
330 | 330 | ||
331 | status = pboardobjgrp->pmuinithandle(g, pboardobjgrp); | 331 | status = pboardobjgrp->pmuinithandle(g, pboardobjgrp); |
332 | 332 | ||
333 | gk20a_dbg_info("Done"); | 333 | nvgpu_log_info(g, "Done"); |
334 | return status; | 334 | return status; |
335 | } | 335 | } |
336 | 336 | ||
@@ -343,7 +343,7 @@ static u32 _clk_freq_controller_devgrp_pmudata_instget(struct gk20a *g, | |||
343 | (struct nv_pmu_clk_clk_freq_controller_boardobj_grp_set *) | 343 | (struct nv_pmu_clk_clk_freq_controller_boardobj_grp_set *) |
344 | pmuboardobjgrp; | 344 | pmuboardobjgrp; |
345 | 345 | ||
346 | gk20a_dbg_info(""); | 346 | nvgpu_log_info(g, " "); |
347 | 347 | ||
348 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ | 348 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ |
349 | if (((u32)BIT(idx) & | 349 | if (((u32)BIT(idx) & |
@@ -352,7 +352,7 @@ static u32 _clk_freq_controller_devgrp_pmudata_instget(struct gk20a *g, | |||
352 | 352 | ||
353 | *ppboardobjpmudata = (struct nv_pmu_boardobj *) | 353 | *ppboardobjpmudata = (struct nv_pmu_boardobj *) |
354 | &pgrp_set->objects[idx].data.board_obj; | 354 | &pgrp_set->objects[idx].data.board_obj; |
355 | gk20a_dbg_info(" Done"); | 355 | nvgpu_log_info(g, " Done"); |
356 | return 0; | 356 | return 0; |
357 | } | 357 | } |
358 | 358 | ||
@@ -392,7 +392,7 @@ u32 clk_freq_controller_sw_setup(struct gk20a *g) | |||
392 | u8 i; | 392 | u8 i; |
393 | u8 j; | 393 | u8 j; |
394 | 394 | ||
395 | gk20a_dbg_info(""); | 395 | nvgpu_log_info(g, " "); |
396 | 396 | ||
397 | pclk_freq_controllers = &g->clk_pmu.clk_freq_controllers; | 397 | pclk_freq_controllers = &g->clk_pmu.clk_freq_controllers; |
398 | status = boardobjgrpconstruct_e32(g, &pclk_freq_controllers->super); | 398 | status = boardobjgrpconstruct_e32(g, &pclk_freq_controllers->super); |
@@ -447,6 +447,6 @@ u32 clk_freq_controller_sw_setup(struct gk20a *g) | |||
447 | freq_ctrl_load_mask.super, i); | 447 | freq_ctrl_load_mask.super, i); |
448 | } | 448 | } |
449 | done: | 449 | done: |
450 | gk20a_dbg_info(" done status %x", status); | 450 | nvgpu_log_info(g, " done status %x", status); |
451 | return status; | 451 | return status; |
452 | } | 452 | } |
diff --git a/drivers/gpu/nvgpu/clk/clk_prog.c b/drivers/gpu/nvgpu/clk/clk_prog.c index 6b5315b4..8926b9f5 100644 --- a/drivers/gpu/nvgpu/clk/clk_prog.c +++ b/drivers/gpu/nvgpu/clk/clk_prog.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -72,7 +72,7 @@ static u32 _clk_progs_pmudata_instget(struct gk20a *g, | |||
72 | struct nv_pmu_clk_clk_prog_boardobj_grp_set *pgrp_set = | 72 | struct nv_pmu_clk_clk_prog_boardobj_grp_set *pgrp_set = |
73 | (struct nv_pmu_clk_clk_prog_boardobj_grp_set *)pmuboardobjgrp; | 73 | (struct nv_pmu_clk_clk_prog_boardobj_grp_set *)pmuboardobjgrp; |
74 | 74 | ||
75 | gk20a_dbg_info(""); | 75 | nvgpu_log_info(g, " "); |
76 | 76 | ||
77 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ | 77 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ |
78 | if (((u32)BIT(idx) & | 78 | if (((u32)BIT(idx) & |
@@ -81,7 +81,7 @@ static u32 _clk_progs_pmudata_instget(struct gk20a *g, | |||
81 | 81 | ||
82 | *ppboardobjpmudata = (struct nv_pmu_boardobj *) | 82 | *ppboardobjpmudata = (struct nv_pmu_boardobj *) |
83 | &pgrp_set->objects[idx].data.board_obj; | 83 | &pgrp_set->objects[idx].data.board_obj; |
84 | gk20a_dbg_info(" Done"); | 84 | nvgpu_log_info(g, " Done"); |
85 | return 0; | 85 | return 0; |
86 | } | 86 | } |
87 | 87 | ||
@@ -91,7 +91,7 @@ u32 clk_prog_sw_setup(struct gk20a *g) | |||
91 | struct boardobjgrp *pboardobjgrp = NULL; | 91 | struct boardobjgrp *pboardobjgrp = NULL; |
92 | struct clk_progs *pclkprogobjs; | 92 | struct clk_progs *pclkprogobjs; |
93 | 93 | ||
94 | gk20a_dbg_info(""); | 94 | nvgpu_log_info(g, " "); |
95 | 95 | ||
96 | status = boardobjgrpconstruct_e255(g, &g->clk_pmu.clk_progobjs.super); | 96 | status = boardobjgrpconstruct_e255(g, &g->clk_pmu.clk_progobjs.super); |
97 | if (status) { | 97 | if (status) { |
@@ -130,7 +130,7 @@ u32 clk_prog_sw_setup(struct gk20a *g) | |||
130 | 130 | ||
131 | 131 | ||
132 | done: | 132 | done: |
133 | gk20a_dbg_info(" done status %x", status); | 133 | nvgpu_log_info(g, " done status %x", status); |
134 | return status; | 134 | return status; |
135 | } | 135 | } |
136 | 136 | ||
@@ -139,7 +139,7 @@ u32 clk_prog_pmu_setup(struct gk20a *g) | |||
139 | u32 status; | 139 | u32 status; |
140 | struct boardobjgrp *pboardobjgrp = NULL; | 140 | struct boardobjgrp *pboardobjgrp = NULL; |
141 | 141 | ||
142 | gk20a_dbg_info(""); | 142 | nvgpu_log_info(g, " "); |
143 | 143 | ||
144 | pboardobjgrp = &g->clk_pmu.clk_progobjs.super.super; | 144 | pboardobjgrp = &g->clk_pmu.clk_progobjs.super.super; |
145 | 145 | ||
@@ -148,7 +148,7 @@ u32 clk_prog_pmu_setup(struct gk20a *g) | |||
148 | 148 | ||
149 | status = pboardobjgrp->pmuinithandle(g, pboardobjgrp); | 149 | status = pboardobjgrp->pmuinithandle(g, pboardobjgrp); |
150 | 150 | ||
151 | gk20a_dbg_info("Done"); | 151 | nvgpu_log_info(g, "Done"); |
152 | return status; | 152 | return status; |
153 | } | 153 | } |
154 | 154 | ||
@@ -186,7 +186,7 @@ static u32 devinit_get_clk_prog_table(struct gk20a *g, | |||
186 | struct clk_prog_1x_master_table v1x_master_table; | 186 | struct clk_prog_1x_master_table v1x_master_table; |
187 | } prog_data; | 187 | } prog_data; |
188 | 188 | ||
189 | gk20a_dbg_info(""); | 189 | nvgpu_log_info(g, " "); |
190 | 190 | ||
191 | clkprogs_tbl_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g, | 191 | clkprogs_tbl_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g, |
192 | g->bios.clock_token, CLOCK_PROGRAMMING_TABLE); | 192 | g->bios.clock_token, CLOCK_PROGRAMMING_TABLE); |
@@ -372,7 +372,7 @@ static u32 devinit_get_clk_prog_table(struct gk20a *g, | |||
372 | } | 372 | } |
373 | } | 373 | } |
374 | done: | 374 | done: |
375 | gk20a_dbg_info(" done status %x", status); | 375 | nvgpu_log_info(g, " done status %x", status); |
376 | return status; | 376 | return status; |
377 | } | 377 | } |
378 | 378 | ||
@@ -382,7 +382,7 @@ static u32 _clk_prog_pmudatainit_super(struct gk20a *g, | |||
382 | { | 382 | { |
383 | u32 status = 0; | 383 | u32 status = 0; |
384 | 384 | ||
385 | gk20a_dbg_info(""); | 385 | nvgpu_log_info(g, " "); |
386 | 386 | ||
387 | status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata); | 387 | status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata); |
388 | return status; | 388 | return status; |
@@ -396,7 +396,7 @@ static u32 _clk_prog_pmudatainit_1x(struct gk20a *g, | |||
396 | struct clk_prog_1x *pclk_prog_1x; | 396 | struct clk_prog_1x *pclk_prog_1x; |
397 | struct nv_pmu_clk_clk_prog_1x_boardobj_set *pset; | 397 | struct nv_pmu_clk_clk_prog_1x_boardobj_set *pset; |
398 | 398 | ||
399 | gk20a_dbg_info(""); | 399 | nvgpu_log_info(g, " "); |
400 | 400 | ||
401 | status = _clk_prog_pmudatainit_super(g, board_obj_ptr, ppmudata); | 401 | status = _clk_prog_pmudatainit_super(g, board_obj_ptr, ppmudata); |
402 | if (status != 0) | 402 | if (status != 0) |
@@ -424,7 +424,7 @@ static u32 _clk_prog_pmudatainit_1x_master(struct gk20a *g, | |||
424 | u32 vfsize = sizeof(struct ctrl_clk_clk_prog_1x_master_vf_entry) * | 424 | u32 vfsize = sizeof(struct ctrl_clk_clk_prog_1x_master_vf_entry) * |
425 | g->clk_pmu.clk_progobjs.vf_entry_count; | 425 | g->clk_pmu.clk_progobjs.vf_entry_count; |
426 | 426 | ||
427 | gk20a_dbg_info(""); | 427 | nvgpu_log_info(g, " "); |
428 | 428 | ||
429 | status = _clk_prog_pmudatainit_1x(g, board_obj_ptr, ppmudata); | 429 | status = _clk_prog_pmudatainit_1x(g, board_obj_ptr, ppmudata); |
430 | 430 | ||
@@ -455,7 +455,7 @@ static u32 _clk_prog_pmudatainit_1x_master_ratio(struct gk20a *g, | |||
455 | u32 slavesize = sizeof(struct ctrl_clk_clk_prog_1x_master_ratio_slave_entry) * | 455 | u32 slavesize = sizeof(struct ctrl_clk_clk_prog_1x_master_ratio_slave_entry) * |
456 | g->clk_pmu.clk_progobjs.slave_entry_count; | 456 | g->clk_pmu.clk_progobjs.slave_entry_count; |
457 | 457 | ||
458 | gk20a_dbg_info(""); | 458 | nvgpu_log_info(g, " "); |
459 | 459 | ||
460 | status = _clk_prog_pmudatainit_1x_master(g, board_obj_ptr, ppmudata); | 460 | status = _clk_prog_pmudatainit_1x_master(g, board_obj_ptr, ppmudata); |
461 | if (status != 0) | 461 | if (status != 0) |
@@ -483,7 +483,7 @@ static u32 _clk_prog_pmudatainit_1x_master_table(struct gk20a *g, | |||
483 | u32 slavesize = sizeof(struct ctrl_clk_clk_prog_1x_master_ratio_slave_entry) * | 483 | u32 slavesize = sizeof(struct ctrl_clk_clk_prog_1x_master_ratio_slave_entry) * |
484 | g->clk_pmu.clk_progobjs.slave_entry_count; | 484 | g->clk_pmu.clk_progobjs.slave_entry_count; |
485 | 485 | ||
486 | gk20a_dbg_info(""); | 486 | nvgpu_log_info(g, " "); |
487 | 487 | ||
488 | status = _clk_prog_pmudatainit_1x_master(g, board_obj_ptr, ppmudata); | 488 | status = _clk_prog_pmudatainit_1x_master(g, board_obj_ptr, ppmudata); |
489 | if (status != 0) | 489 | if (status != 0) |
@@ -510,7 +510,7 @@ static u32 _clk_prog_1x_master_rail_construct_vf_point(struct gk20a *g, | |||
510 | struct clk_vf_point *p_vf_point; | 510 | struct clk_vf_point *p_vf_point; |
511 | u32 status; | 511 | u32 status; |
512 | 512 | ||
513 | gk20a_dbg_info(""); | 513 | nvgpu_log_info(g, " "); |
514 | 514 | ||
515 | p_vf_point = construct_clk_vf_point(g, (void *)p_vf_point_tmp); | 515 | p_vf_point = construct_clk_vf_point(g, (void *)p_vf_point_tmp); |
516 | if (p_vf_point == NULL) { | 516 | if (p_vf_point == NULL) { |
@@ -527,7 +527,7 @@ static u32 _clk_prog_1x_master_rail_construct_vf_point(struct gk20a *g, | |||
527 | p_vf_rail->vf_point_idx_last = (*p_vf_point_idx)++; | 527 | p_vf_rail->vf_point_idx_last = (*p_vf_point_idx)++; |
528 | 528 | ||
529 | done: | 529 | done: |
530 | gk20a_dbg_info("done status %x", status); | 530 | nvgpu_log_info(g, "done status %x", status); |
531 | return status; | 531 | return status; |
532 | } | 532 | } |
533 | 533 | ||
@@ -561,7 +561,7 @@ static u32 clk_prog_construct_1x(struct gk20a *g, | |||
561 | (struct clk_prog_1x *)pargs; | 561 | (struct clk_prog_1x *)pargs; |
562 | u32 status = 0; | 562 | u32 status = 0; |
563 | 563 | ||
564 | gk20a_dbg_info(" "); | 564 | nvgpu_log_info(g, " "); |
565 | ptmpobj->type_mask |= BIT(CTRL_CLK_CLK_PROG_TYPE_1X); | 565 | ptmpobj->type_mask |= BIT(CTRL_CLK_CLK_PROG_TYPE_1X); |
566 | status = clk_prog_construct_super(g, ppboardobj, size, pargs); | 566 | status = clk_prog_construct_super(g, ppboardobj, size, pargs); |
567 | if (status) | 567 | if (status) |
@@ -592,7 +592,7 @@ static u32 clk_prog_construct_1x_master(struct gk20a *g, | |||
592 | g->clk_pmu.clk_progobjs.vf_entry_count; | 592 | g->clk_pmu.clk_progobjs.vf_entry_count; |
593 | u8 railidx; | 593 | u8 railidx; |
594 | 594 | ||
595 | gk20a_dbg_info(" type - %x", BOARDOBJ_GET_TYPE(pargs)); | 595 | nvgpu_log_info(g, " type - %x", BOARDOBJ_GET_TYPE(pargs)); |
596 | 596 | ||
597 | ptmpobj->type_mask |= BIT(CTRL_CLK_CLK_PROG_TYPE_1X_MASTER); | 597 | ptmpobj->type_mask |= BIT(CTRL_CLK_CLK_PROG_TYPE_1X_MASTER); |
598 | status = clk_prog_construct_1x(g, ppboardobj, size, pargs); | 598 | status = clk_prog_construct_1x(g, ppboardobj, size, pargs); |
@@ -686,7 +686,7 @@ static u32 clk_prog_construct_1x_master_table(struct gk20a *g, | |||
686 | u32 slavesize = sizeof(struct ctrl_clk_clk_prog_1x_master_ratio_slave_entry) * | 686 | u32 slavesize = sizeof(struct ctrl_clk_clk_prog_1x_master_ratio_slave_entry) * |
687 | g->clk_pmu.clk_progobjs.slave_entry_count; | 687 | g->clk_pmu.clk_progobjs.slave_entry_count; |
688 | 688 | ||
689 | gk20a_dbg_info("type - %x", BOARDOBJ_GET_TYPE(pargs)); | 689 | nvgpu_log_info(g, "type - %x", BOARDOBJ_GET_TYPE(pargs)); |
690 | 690 | ||
691 | if (BOARDOBJ_GET_TYPE(pargs) != CTRL_CLK_CLK_PROG_TYPE_1X_MASTER_TABLE) | 691 | if (BOARDOBJ_GET_TYPE(pargs) != CTRL_CLK_CLK_PROG_TYPE_1X_MASTER_TABLE) |
692 | return -EINVAL; | 692 | return -EINVAL; |
@@ -727,7 +727,7 @@ static struct clk_prog *construct_clk_prog(struct gk20a *g, void *pargs) | |||
727 | struct boardobj *board_obj_ptr = NULL; | 727 | struct boardobj *board_obj_ptr = NULL; |
728 | u32 status; | 728 | u32 status; |
729 | 729 | ||
730 | gk20a_dbg_info(" type - %x", BOARDOBJ_GET_TYPE(pargs)); | 730 | nvgpu_log_info(g, " type - %x", BOARDOBJ_GET_TYPE(pargs)); |
731 | switch (BOARDOBJ_GET_TYPE(pargs)) { | 731 | switch (BOARDOBJ_GET_TYPE(pargs)) { |
732 | case CTRL_CLK_CLK_PROG_TYPE_1X: | 732 | case CTRL_CLK_CLK_PROG_TYPE_1X: |
733 | status = clk_prog_construct_1x(g, &board_obj_ptr, | 733 | status = clk_prog_construct_1x(g, &board_obj_ptr, |
@@ -754,7 +754,7 @@ static struct clk_prog *construct_clk_prog(struct gk20a *g, void *pargs) | |||
754 | return NULL; | 754 | return NULL; |
755 | } | 755 | } |
756 | 756 | ||
757 | gk20a_dbg_info(" Done"); | 757 | nvgpu_log_info(g, " Done"); |
758 | 758 | ||
759 | return (struct clk_prog *)board_obj_ptr; | 759 | return (struct clk_prog *)board_obj_ptr; |
760 | } | 760 | } |
@@ -777,7 +777,7 @@ static u32 vfflatten_prog_1x_master(struct gk20a *g, | |||
777 | u8 vf_point_idx; | 777 | u8 vf_point_idx; |
778 | u8 vf_rail_idx; | 778 | u8 vf_rail_idx; |
779 | 779 | ||
780 | gk20a_dbg_info(""); | 780 | nvgpu_log_info(g, " "); |
781 | memset(&vf_point_data, 0x0, sizeof(vf_point_data)); | 781 | memset(&vf_point_data, 0x0, sizeof(vf_point_data)); |
782 | 782 | ||
783 | vf_point_idx = BOARDOBJGRP_NEXT_EMPTY_IDX( | 783 | vf_point_idx = BOARDOBJGRP_NEXT_EMPTY_IDX( |
@@ -851,7 +851,7 @@ static u32 vfflatten_prog_1x_master(struct gk20a *g, | |||
851 | *pfreqmaxlastmhz = p1xmaster->super.freq_max_mhz; | 851 | *pfreqmaxlastmhz = p1xmaster->super.freq_max_mhz; |
852 | 852 | ||
853 | done: | 853 | done: |
854 | gk20a_dbg_info("done status %x", status); | 854 | nvgpu_log_info(g, "done status %x", status); |
855 | return status; | 855 | return status; |
856 | } | 856 | } |
857 | 857 | ||
diff --git a/drivers/gpu/nvgpu/clk/clk_vf_point.c b/drivers/gpu/nvgpu/clk/clk_vf_point.c index 8333b2b0..b459c012 100644 --- a/drivers/gpu/nvgpu/clk/clk_vf_point.c +++ b/drivers/gpu/nvgpu/clk/clk_vf_point.c | |||
@@ -59,7 +59,7 @@ static u32 _clk_vf_points_pmudata_instget(struct gk20a *g, | |||
59 | (struct nv_pmu_clk_clk_vf_point_boardobj_grp_set *) | 59 | (struct nv_pmu_clk_clk_vf_point_boardobj_grp_set *) |
60 | pmuboardobjgrp; | 60 | pmuboardobjgrp; |
61 | 61 | ||
62 | gk20a_dbg_info(""); | 62 | nvgpu_log_info(g, " "); |
63 | 63 | ||
64 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ | 64 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ |
65 | if (idx >= CTRL_BOARDOBJGRP_E255_MAX_OBJECTS) | 65 | if (idx >= CTRL_BOARDOBJGRP_E255_MAX_OBJECTS) |
@@ -67,7 +67,7 @@ static u32 _clk_vf_points_pmudata_instget(struct gk20a *g, | |||
67 | 67 | ||
68 | *ppboardobjpmudata = (struct nv_pmu_boardobj *) | 68 | *ppboardobjpmudata = (struct nv_pmu_boardobj *) |
69 | &pgrp_set->objects[idx].data.board_obj; | 69 | &pgrp_set->objects[idx].data.board_obj; |
70 | gk20a_dbg_info(" Done"); | 70 | nvgpu_log_info(g, " Done"); |
71 | return 0; | 71 | return 0; |
72 | } | 72 | } |
73 | 73 | ||
@@ -94,7 +94,7 @@ u32 clk_vf_point_sw_setup(struct gk20a *g) | |||
94 | u32 status; | 94 | u32 status; |
95 | struct boardobjgrp *pboardobjgrp = NULL; | 95 | struct boardobjgrp *pboardobjgrp = NULL; |
96 | 96 | ||
97 | gk20a_dbg_info(""); | 97 | nvgpu_log_info(g, " "); |
98 | 98 | ||
99 | status = boardobjgrpconstruct_e255(g, &g->clk_pmu.clk_vf_pointobjs.super); | 99 | status = boardobjgrpconstruct_e255(g, &g->clk_pmu.clk_vf_pointobjs.super); |
100 | if (status) { | 100 | if (status) { |
@@ -132,7 +132,7 @@ u32 clk_vf_point_sw_setup(struct gk20a *g) | |||
132 | pboardobjgrp->pmustatusinstget = _clk_vf_points_pmustatus_instget; | 132 | pboardobjgrp->pmustatusinstget = _clk_vf_points_pmustatus_instget; |
133 | 133 | ||
134 | done: | 134 | done: |
135 | gk20a_dbg_info(" done status %x", status); | 135 | nvgpu_log_info(g, " done status %x", status); |
136 | return status; | 136 | return status; |
137 | } | 137 | } |
138 | 138 | ||
@@ -141,7 +141,7 @@ u32 clk_vf_point_pmu_setup(struct gk20a *g) | |||
141 | u32 status; | 141 | u32 status; |
142 | struct boardobjgrp *pboardobjgrp = NULL; | 142 | struct boardobjgrp *pboardobjgrp = NULL; |
143 | 143 | ||
144 | gk20a_dbg_info(""); | 144 | nvgpu_log_info(g, " "); |
145 | 145 | ||
146 | pboardobjgrp = &g->clk_pmu.clk_vf_pointobjs.super.super; | 146 | pboardobjgrp = &g->clk_pmu.clk_vf_pointobjs.super.super; |
147 | 147 | ||
@@ -150,7 +150,7 @@ u32 clk_vf_point_pmu_setup(struct gk20a *g) | |||
150 | 150 | ||
151 | status = pboardobjgrp->pmuinithandle(g, pboardobjgrp); | 151 | status = pboardobjgrp->pmuinithandle(g, pboardobjgrp); |
152 | 152 | ||
153 | gk20a_dbg_info("Done"); | 153 | nvgpu_log_info(g, "Done"); |
154 | return status; | 154 | return status; |
155 | } | 155 | } |
156 | 156 | ||
@@ -187,7 +187,7 @@ static u32 _clk_vf_point_pmudatainit_volt(struct gk20a *g, | |||
187 | struct clk_vf_point_volt *pclk_vf_point_volt; | 187 | struct clk_vf_point_volt *pclk_vf_point_volt; |
188 | struct nv_pmu_clk_clk_vf_point_volt_boardobj_set *pset; | 188 | struct nv_pmu_clk_clk_vf_point_volt_boardobj_set *pset; |
189 | 189 | ||
190 | gk20a_dbg_info(""); | 190 | nvgpu_log_info(g, " "); |
191 | 191 | ||
192 | status = _clk_vf_point_pmudatainit_super(g, board_obj_ptr, ppmudata); | 192 | status = _clk_vf_point_pmudatainit_super(g, board_obj_ptr, ppmudata); |
193 | if (status != 0) | 193 | if (status != 0) |
@@ -214,7 +214,7 @@ static u32 _clk_vf_point_pmudatainit_freq(struct gk20a *g, | |||
214 | struct clk_vf_point_freq *pclk_vf_point_freq; | 214 | struct clk_vf_point_freq *pclk_vf_point_freq; |
215 | struct nv_pmu_clk_clk_vf_point_freq_boardobj_set *pset; | 215 | struct nv_pmu_clk_clk_vf_point_freq_boardobj_set *pset; |
216 | 216 | ||
217 | gk20a_dbg_info(""); | 217 | nvgpu_log_info(g, " "); |
218 | 218 | ||
219 | status = _clk_vf_point_pmudatainit_super(g, board_obj_ptr, ppmudata); | 219 | status = _clk_vf_point_pmudatainit_super(g, board_obj_ptr, ppmudata); |
220 | if (status != 0) | 220 | if (status != 0) |
@@ -297,7 +297,7 @@ struct clk_vf_point *construct_clk_vf_point(struct gk20a *g, void *pargs) | |||
297 | struct boardobj *board_obj_ptr = NULL; | 297 | struct boardobj *board_obj_ptr = NULL; |
298 | u32 status; | 298 | u32 status; |
299 | 299 | ||
300 | gk20a_dbg_info(""); | 300 | nvgpu_log_info(g, " "); |
301 | switch (BOARDOBJ_GET_TYPE(pargs)) { | 301 | switch (BOARDOBJ_GET_TYPE(pargs)) { |
302 | case CTRL_CLK_CLK_VF_POINT_TYPE_FREQ: | 302 | case CTRL_CLK_CLK_VF_POINT_TYPE_FREQ: |
303 | status = clk_vf_point_construct_freq(g, &board_obj_ptr, | 303 | status = clk_vf_point_construct_freq(g, &board_obj_ptr, |
@@ -316,7 +316,7 @@ struct clk_vf_point *construct_clk_vf_point(struct gk20a *g, void *pargs) | |||
316 | if (status) | 316 | if (status) |
317 | return NULL; | 317 | return NULL; |
318 | 318 | ||
319 | gk20a_dbg_info(" Done"); | 319 | nvgpu_log_info(g, " Done"); |
320 | 320 | ||
321 | return (struct clk_vf_point *)board_obj_ptr; | 321 | return (struct clk_vf_point *)board_obj_ptr; |
322 | } | 322 | } |
@@ -329,7 +329,7 @@ static u32 _clk_vf_point_pmudatainit_super(struct gk20a *g, | |||
329 | struct clk_vf_point *pclk_vf_point; | 329 | struct clk_vf_point *pclk_vf_point; |
330 | struct nv_pmu_clk_clk_vf_point_boardobj_set *pset; | 330 | struct nv_pmu_clk_clk_vf_point_boardobj_set *pset; |
331 | 331 | ||
332 | gk20a_dbg_info(""); | 332 | nvgpu_log_info(g, " "); |
333 | 333 | ||
334 | status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata); | 334 | status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata); |
335 | if (status != 0) | 335 | if (status != 0) |
@@ -355,7 +355,7 @@ static u32 clk_vf_point_update(struct gk20a *g, | |||
355 | struct clk_vf_point *pclk_vf_point; | 355 | struct clk_vf_point *pclk_vf_point; |
356 | struct nv_pmu_clk_clk_vf_point_boardobj_get_status *pstatus; | 356 | struct nv_pmu_clk_clk_vf_point_boardobj_get_status *pstatus; |
357 | 357 | ||
358 | gk20a_dbg_info(""); | 358 | nvgpu_log_info(g, " "); |
359 | 359 | ||
360 | 360 | ||
361 | pclk_vf_point = | 361 | pclk_vf_point = |
@@ -388,7 +388,7 @@ u32 clk_vf_point_cache(struct gk20a *g) | |||
388 | u32 status; | 388 | u32 status; |
389 | u8 index; | 389 | u8 index; |
390 | 390 | ||
391 | gk20a_dbg_info(""); | 391 | nvgpu_log_info(g, " "); |
392 | pclk_vf_points = &g->clk_pmu.clk_vf_pointobjs; | 392 | pclk_vf_points = &g->clk_pmu.clk_vf_pointobjs; |
393 | pboardobjgrp = &pclk_vf_points->super.super; | 393 | pboardobjgrp = &pclk_vf_points->super.super; |
394 | pboardobjgrpmask = &pclk_vf_points->super.mask.super; | 394 | pboardobjgrpmask = &pclk_vf_points->super.mask.super; |
diff --git a/drivers/gpu/nvgpu/clk/clk_vin.c b/drivers/gpu/nvgpu/clk/clk_vin.c index 74bcd247..66efefef 100644 --- a/drivers/gpu/nvgpu/clk/clk_vin.c +++ b/drivers/gpu/nvgpu/clk/clk_vin.c | |||
@@ -323,13 +323,13 @@ static u32 _clk_vin_devgrp_pmudatainit_super(struct gk20a *g, | |||
323 | struct avfsvinobjs *pvin_obbj = (struct avfsvinobjs *)pboardobjgrp; | 323 | struct avfsvinobjs *pvin_obbj = (struct avfsvinobjs *)pboardobjgrp; |
324 | u32 status = 0; | 324 | u32 status = 0; |
325 | 325 | ||
326 | gk20a_dbg_info(""); | 326 | nvgpu_log_info(g, " "); |
327 | 327 | ||
328 | status = boardobjgrp_pmudatainit_e32(g, pboardobjgrp, pboardobjgrppmu); | 328 | status = boardobjgrp_pmudatainit_e32(g, pboardobjgrp, pboardobjgrppmu); |
329 | 329 | ||
330 | pset->b_vin_is_disable_allowed = pvin_obbj->vin_is_disable_allowed; | 330 | pset->b_vin_is_disable_allowed = pvin_obbj->vin_is_disable_allowed; |
331 | 331 | ||
332 | gk20a_dbg_info(" Done"); | 332 | nvgpu_log_info(g, " Done"); |
333 | return status; | 333 | return status; |
334 | } | 334 | } |
335 | 335 | ||
@@ -342,7 +342,7 @@ static u32 _clk_vin_devgrp_pmudata_instget(struct gk20a *g, | |||
342 | (struct nv_pmu_clk_clk_vin_device_boardobj_grp_set *) | 342 | (struct nv_pmu_clk_clk_vin_device_boardobj_grp_set *) |
343 | pmuboardobjgrp; | 343 | pmuboardobjgrp; |
344 | 344 | ||
345 | gk20a_dbg_info(""); | 345 | nvgpu_log_info(g, " "); |
346 | 346 | ||
347 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ | 347 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ |
348 | if (((u32)BIT(idx) & | 348 | if (((u32)BIT(idx) & |
@@ -351,7 +351,7 @@ static u32 _clk_vin_devgrp_pmudata_instget(struct gk20a *g, | |||
351 | 351 | ||
352 | *ppboardobjpmudata = (struct nv_pmu_boardobj *) | 352 | *ppboardobjpmudata = (struct nv_pmu_boardobj *) |
353 | &pgrp_set->objects[idx].data.board_obj; | 353 | &pgrp_set->objects[idx].data.board_obj; |
354 | gk20a_dbg_info(" Done"); | 354 | nvgpu_log_info(g, " Done"); |
355 | return 0; | 355 | return 0; |
356 | } | 356 | } |
357 | 357 | ||
@@ -381,7 +381,7 @@ u32 clk_vin_sw_setup(struct gk20a *g) | |||
381 | struct vin_device_v20 *pvindev = NULL; | 381 | struct vin_device_v20 *pvindev = NULL; |
382 | struct avfsvinobjs *pvinobjs; | 382 | struct avfsvinobjs *pvinobjs; |
383 | 383 | ||
384 | gk20a_dbg_info(""); | 384 | nvgpu_log_info(g, " "); |
385 | 385 | ||
386 | status = boardobjgrpconstruct_e32(g, &g->clk_pmu.avfs_vinobjs.super); | 386 | status = boardobjgrpconstruct_e32(g, &g->clk_pmu.avfs_vinobjs.super); |
387 | if (status) { | 387 | if (status) { |
@@ -427,7 +427,7 @@ u32 clk_vin_sw_setup(struct gk20a *g) | |||
427 | } | 427 | } |
428 | 428 | ||
429 | done: | 429 | done: |
430 | gk20a_dbg_info(" done status %x", status); | 430 | nvgpu_log_info(g, " done status %x", status); |
431 | return status; | 431 | return status; |
432 | } | 432 | } |
433 | 433 | ||
@@ -436,7 +436,7 @@ u32 clk_vin_pmu_setup(struct gk20a *g) | |||
436 | u32 status; | 436 | u32 status; |
437 | struct boardobjgrp *pboardobjgrp = NULL; | 437 | struct boardobjgrp *pboardobjgrp = NULL; |
438 | 438 | ||
439 | gk20a_dbg_info(""); | 439 | nvgpu_log_info(g, " "); |
440 | 440 | ||
441 | pboardobjgrp = &g->clk_pmu.avfs_vinobjs.super.super; | 441 | pboardobjgrp = &g->clk_pmu.avfs_vinobjs.super.super; |
442 | 442 | ||
@@ -445,7 +445,7 @@ u32 clk_vin_pmu_setup(struct gk20a *g) | |||
445 | 445 | ||
446 | status = pboardobjgrp->pmuinithandle(g, pboardobjgrp); | 446 | status = pboardobjgrp->pmuinithandle(g, pboardobjgrp); |
447 | 447 | ||
448 | gk20a_dbg_info("Done"); | 448 | nvgpu_log_info(g, "Done"); |
449 | return status; | 449 | return status; |
450 | } | 450 | } |
451 | 451 | ||
@@ -470,7 +470,7 @@ static u32 devinit_get_vin_device_table(struct gk20a *g, | |||
470 | struct vin_device_v20 vin_device_v20; | 470 | struct vin_device_v20 vin_device_v20; |
471 | } vin_device_data; | 471 | } vin_device_data; |
472 | 472 | ||
473 | gk20a_dbg_info(""); | 473 | nvgpu_log_info(g, " "); |
474 | 474 | ||
475 | vin_table_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g, | 475 | vin_table_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g, |
476 | g->bios.clock_token, VIN_TABLE); | 476 | g->bios.clock_token, VIN_TABLE); |
@@ -557,7 +557,7 @@ static u32 devinit_get_vin_device_table(struct gk20a *g, | |||
557 | } | 557 | } |
558 | 558 | ||
559 | done: | 559 | done: |
560 | gk20a_dbg_info(" done status %x", status); | 560 | nvgpu_log_info(g, " done status %x", status); |
561 | return status; | 561 | return status; |
562 | } | 562 | } |
563 | 563 | ||
@@ -645,7 +645,7 @@ static struct vin_device *construct_vin_device(struct gk20a *g, void *pargs) | |||
645 | struct boardobj *board_obj_ptr = NULL; | 645 | struct boardobj *board_obj_ptr = NULL; |
646 | u32 status; | 646 | u32 status; |
647 | 647 | ||
648 | gk20a_dbg_info(" %d", BOARDOBJ_GET_TYPE(pargs)); | 648 | nvgpu_log_info(g, " %d", BOARDOBJ_GET_TYPE(pargs)); |
649 | switch (BOARDOBJ_GET_TYPE(pargs)) { | 649 | switch (BOARDOBJ_GET_TYPE(pargs)) { |
650 | case CTRL_CLK_VIN_TYPE_V10: | 650 | case CTRL_CLK_VIN_TYPE_V10: |
651 | status = vin_device_construct_v10(g, &board_obj_ptr, | 651 | status = vin_device_construct_v10(g, &board_obj_ptr, |
@@ -664,7 +664,7 @@ static struct vin_device *construct_vin_device(struct gk20a *g, void *pargs) | |||
664 | if (status) | 664 | if (status) |
665 | return NULL; | 665 | return NULL; |
666 | 666 | ||
667 | gk20a_dbg_info(" Done"); | 667 | nvgpu_log_info(g, " Done"); |
668 | 668 | ||
669 | return (struct vin_device *)board_obj_ptr; | 669 | return (struct vin_device *)board_obj_ptr; |
670 | } | 670 | } |
@@ -679,7 +679,7 @@ static u32 vin_device_init_pmudata_v10(struct gk20a *g, | |||
679 | struct vin_device_v20 *pvin_dev_v20; | 679 | struct vin_device_v20 *pvin_dev_v20; |
680 | struct nv_pmu_clk_clk_vin_device_v10_boardobj_set *perf_pmu_data; | 680 | struct nv_pmu_clk_clk_vin_device_v10_boardobj_set *perf_pmu_data; |
681 | 681 | ||
682 | gk20a_dbg_info(""); | 682 | nvgpu_log_info(g, " "); |
683 | 683 | ||
684 | status = vin_device_init_pmudata_super(g, board_obj_ptr, ppmudata); | 684 | status = vin_device_init_pmudata_super(g, board_obj_ptr, ppmudata); |
685 | if (status != 0) | 685 | if (status != 0) |
@@ -692,7 +692,7 @@ static u32 vin_device_init_pmudata_v10(struct gk20a *g, | |||
692 | perf_pmu_data->data.vin_cal.intercept = pvin_dev_v20->data.vin_cal.cal_v10.intercept; | 692 | perf_pmu_data->data.vin_cal.intercept = pvin_dev_v20->data.vin_cal.cal_v10.intercept; |
693 | perf_pmu_data->data.vin_cal.slope = pvin_dev_v20->data.vin_cal.cal_v10.slope; | 693 | perf_pmu_data->data.vin_cal.slope = pvin_dev_v20->data.vin_cal.cal_v10.slope; |
694 | 694 | ||
695 | gk20a_dbg_info(" Done"); | 695 | nvgpu_log_info(g, " Done"); |
696 | 696 | ||
697 | return status; | 697 | return status; |
698 | } | 698 | } |
@@ -705,7 +705,7 @@ static u32 vin_device_init_pmudata_v20(struct gk20a *g, | |||
705 | struct vin_device_v20 *pvin_dev_v20; | 705 | struct vin_device_v20 *pvin_dev_v20; |
706 | struct nv_pmu_clk_clk_vin_device_v20_boardobj_set *perf_pmu_data; | 706 | struct nv_pmu_clk_clk_vin_device_v20_boardobj_set *perf_pmu_data; |
707 | 707 | ||
708 | gk20a_dbg_info(""); | 708 | nvgpu_log_info(g, " "); |
709 | 709 | ||
710 | status = vin_device_init_pmudata_super(g, board_obj_ptr, ppmudata); | 710 | status = vin_device_init_pmudata_super(g, board_obj_ptr, ppmudata); |
711 | if (status != 0) | 711 | if (status != 0) |
@@ -718,7 +718,7 @@ static u32 vin_device_init_pmudata_v20(struct gk20a *g, | |||
718 | perf_pmu_data->data.vin_cal.cal_v20.offset = pvin_dev_v20->data.vin_cal.cal_v20.offset; | 718 | perf_pmu_data->data.vin_cal.cal_v20.offset = pvin_dev_v20->data.vin_cal.cal_v20.offset; |
719 | perf_pmu_data->data.vin_cal.cal_v20.gain = pvin_dev_v20->data.vin_cal.cal_v20.gain; | 719 | perf_pmu_data->data.vin_cal.cal_v20.gain = pvin_dev_v20->data.vin_cal.cal_v20.gain; |
720 | 720 | ||
721 | gk20a_dbg_info(" Done"); | 721 | nvgpu_log_info(g, " Done"); |
722 | 722 | ||
723 | return status; | 723 | return status; |
724 | } | 724 | } |
@@ -731,7 +731,7 @@ static u32 vin_device_init_pmudata_super(struct gk20a *g, | |||
731 | struct vin_device *pvin_dev; | 731 | struct vin_device *pvin_dev; |
732 | struct nv_pmu_clk_clk_vin_device_boardobj_set *perf_pmu_data; | 732 | struct nv_pmu_clk_clk_vin_device_boardobj_set *perf_pmu_data; |
733 | 733 | ||
734 | gk20a_dbg_info(""); | 734 | nvgpu_log_info(g, " "); |
735 | 735 | ||
736 | status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata); | 736 | status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata); |
737 | if (status != 0) | 737 | if (status != 0) |
@@ -745,7 +745,7 @@ static u32 vin_device_init_pmudata_super(struct gk20a *g, | |||
745 | perf_pmu_data->volt_domain = pvin_dev->volt_domain; | 745 | perf_pmu_data->volt_domain = pvin_dev->volt_domain; |
746 | perf_pmu_data->flls_shared_mask = pvin_dev->flls_shared_mask; | 746 | perf_pmu_data->flls_shared_mask = pvin_dev->flls_shared_mask; |
747 | 747 | ||
748 | gk20a_dbg_info(" Done"); | 748 | nvgpu_log_info(g, " Done"); |
749 | 749 | ||
750 | return status; | 750 | return status; |
751 | } | 751 | } |