2 files changed, 38 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/clk/clk.c b/drivers/gpu/nvgpu/clk/clk.c
index f0624595..8532a08b 100644
--- a/drivers/gpu/nvgpu/clk/clk.c
+++ b/drivers/gpu/nvgpu/clk/clk.c
@@ -866,6 +866,43 @@ u32 nvgpu_clk_set_boot_fll_clk_gv10x(struct gk20a *g)
         return status;
 }
 
+int nvgpu_clk_set_fll_clk_gv10x(struct gk20a *g)
+{
+        int status;
+        struct change_fll_clk bootfllclk;
+        u16 gpcclk_clkmhz = BOOT_GPCCLK_MHZ;
+        u32 gpcclk_voltuv = 0U;
+        u32 voltuv = 0U;
+
+        status = clk_vf_point_cache(g);
+        if (status != 0) {
+                nvgpu_err(g, "caching failed");
+                return status;
+        }
+
+        status = clk_domain_get_f_or_v(g, CTRL_CLK_DOMAIN_GPCCLK,
+                &gpcclk_clkmhz, &gpcclk_voltuv, CTRL_VOLT_DOMAIN_LOGIC);
+        if (status != 0) {
+                return status;
+        }
+
+        voltuv = gpcclk_voltuv;
+
+        status = volt_set_voltage(g, voltuv, 0U);
+        if (status != 0) {
+                nvgpu_err(g, "attempt to set max voltage failed %d", voltuv);
+        }
+
+        bootfllclk.api_clk_domain = CTRL_CLK_DOMAIN_GPCCLK;
+        bootfllclk.clkmhz = gpcclk_clkmhz;
+        bootfllclk.voltuv = voltuv;
+        status = clk_program_fllclks(g, &bootfllclk);
+        if (status != 0) {
+                nvgpu_err(g, "attempt to set max gpcclk failed");
+        }
+        return status;
+}
+
 u32 clk_domain_get_f_or_v(
         struct gk20a *g,
         u32 clkapidomain,
diff --git a/drivers/gpu/nvgpu/clk/clk.h b/drivers/gpu/nvgpu/clk/clk.h
index 5a6aeae3..3f4bdf73 100644
--- a/drivers/gpu/nvgpu/clk/clk.h
+++ b/drivers/gpu/nvgpu/clk/clk.h
@@ -138,6 +138,7 @@ u32 nvgpu_clk_vf_change_inject_data_fill_gp10x(struct gk20a *g,
         struct nv_pmu_clk_rpc *rpccall,
         struct set_fll_clk *setfllclk);
 u32 nvgpu_clk_set_boot_fll_clk_gv10x(struct gk20a *g);
+int nvgpu_clk_set_fll_clk_gv10x(struct gk20a *g);
 int clk_pmu_freq_effective_avg_load(struct gk20a *g, bool bload);
 u32 clk_freq_effective_avg(struct gk20a *g, u32  clkDomainMask);
 #endif /* NVGPU_CLK_H */