diff options
Diffstat (limited to 'drivers/gpu/nvgpu/clk')
-rw-r--r-- | drivers/gpu/nvgpu/clk/clk.c | 89 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/clk/clk.h | 6 |
2 files changed, 73 insertions, 22 deletions
diff --git a/drivers/gpu/nvgpu/clk/clk.c b/drivers/gpu/nvgpu/clk/clk.c index a8d99bbb..28f08cb6 100644 --- a/drivers/gpu/nvgpu/clk/clk.c +++ b/drivers/gpu/nvgpu/clk/clk.c | |||
@@ -219,31 +219,13 @@ done: | |||
219 | return status; | 219 | return status; |
220 | } | 220 | } |
221 | 221 | ||
222 | static u32 clk_pmu_vf_inject(struct gk20a *g, struct set_fll_clk *setfllclk) | 222 | u32 nvgpu_clk_vf_change_inject_data_fill_gp10x(struct gk20a *g, |
223 | struct nv_pmu_clk_rpc *rpccall, | ||
224 | struct set_fll_clk *setfllclk) | ||
223 | { | 225 | { |
224 | struct pmu_cmd cmd; | ||
225 | struct pmu_payload payload; | ||
226 | u32 status; | ||
227 | u32 seqdesc; | ||
228 | struct nv_pmu_clk_rpc rpccall; | ||
229 | struct clkrpc_pmucmdhandler_params handler; | ||
230 | struct nv_pmu_clk_vf_change_inject *vfchange; | 226 | struct nv_pmu_clk_vf_change_inject *vfchange; |
231 | 227 | ||
232 | memset(&payload, 0, sizeof(struct pmu_payload)); | 228 | vfchange = &rpccall->params.clk_vf_change_inject; |
233 | memset(&rpccall, 0, sizeof(struct nv_pmu_clk_rpc)); | ||
234 | memset(&handler, 0, sizeof(struct clkrpc_pmucmdhandler_params)); | ||
235 | |||
236 | if ((setfllclk->gpc2clkmhz == 0) || (setfllclk->xbar2clkmhz == 0) || | ||
237 | (setfllclk->sys2clkmhz == 0) || (setfllclk->voltuv == 0)) | ||
238 | return -EINVAL; | ||
239 | |||
240 | if ((setfllclk->target_regime_id_gpc > CTRL_CLK_FLL_REGIME_ID_FR) || | ||
241 | (setfllclk->target_regime_id_sys > CTRL_CLK_FLL_REGIME_ID_FR) || | ||
242 | (setfllclk->target_regime_id_xbar > CTRL_CLK_FLL_REGIME_ID_FR)) | ||
243 | return -EINVAL; | ||
244 | |||
245 | rpccall.function = NV_PMU_CLK_RPC_ID_CLK_VF_CHANGE_INJECT; | ||
246 | vfchange = &rpccall.params.clk_vf_change_inject; | ||
247 | vfchange->flags = 0; | 229 | vfchange->flags = 0; |
248 | vfchange->clk_list.num_domains = 3; | 230 | vfchange->clk_list.num_domains = 3; |
249 | vfchange->clk_list.clk_domains[0].clk_domain = CTRL_CLK_DOMAIN_GPC2CLK; | 231 | vfchange->clk_list.clk_domains[0].clk_domain = CTRL_CLK_DOMAIN_GPC2CLK; |
@@ -276,6 +258,69 @@ static u32 clk_pmu_vf_inject(struct gk20a *g, struct set_fll_clk *setfllclk) | |||
276 | vfchange->volt_list.rails[0].voltage_min_noise_unaware_uv = | 258 | vfchange->volt_list.rails[0].voltage_min_noise_unaware_uv = |
277 | setfllclk->voltuv; | 259 | setfllclk->voltuv; |
278 | 260 | ||
261 | return 0; | ||
262 | } | ||
263 | |||
264 | u32 nvgpu_clk_vf_change_inject_data_fill_gv10x(struct gk20a *g, | ||
265 | struct nv_pmu_clk_rpc *rpccall, | ||
266 | struct set_fll_clk *setfllclk) | ||
267 | { | ||
268 | struct nv_pmu_clk_vf_change_inject_v1 *vfchange; | ||
269 | |||
270 | vfchange = &rpccall->params.clk_vf_change_inject_v1; | ||
271 | vfchange->flags = 0; | ||
272 | vfchange->clk_list.num_domains = 4; | ||
273 | vfchange->clk_list.clk_domains[0].clk_domain = CTRL_CLK_DOMAIN_GPCCLK; | ||
274 | vfchange->clk_list.clk_domains[0].clk_freq_khz = | ||
275 | setfllclk->gpc2clkmhz * 1000; | ||
276 | |||
277 | vfchange->clk_list.clk_domains[1].clk_domain = CTRL_CLK_DOMAIN_XBARCLK; | ||
278 | vfchange->clk_list.clk_domains[1].clk_freq_khz = | ||
279 | setfllclk->xbar2clkmhz * 1000; | ||
280 | |||
281 | vfchange->clk_list.clk_domains[2].clk_domain = CTRL_CLK_DOMAIN_SYSCLK; | ||
282 | vfchange->clk_list.clk_domains[2].clk_freq_khz = | ||
283 | setfllclk->sys2clkmhz * 1000; | ||
284 | |||
285 | vfchange->clk_list.clk_domains[3].clk_domain = CTRL_CLK_DOMAIN_NVDCLK; | ||
286 | vfchange->clk_list.clk_domains[3].clk_freq_khz = 855 * 1000; | ||
287 | |||
288 | vfchange->volt_list.num_rails = 1; | ||
289 | vfchange->volt_list.rails[0].rail_idx = 0; | ||
290 | vfchange->volt_list.rails[0].voltage_uv = setfllclk->voltuv; | ||
291 | vfchange->volt_list.rails[0].voltage_min_noise_unaware_uv = | ||
292 | setfllclk->voltuv; | ||
293 | |||
294 | return 0; | ||
295 | } | ||
296 | |||
297 | static u32 clk_pmu_vf_inject(struct gk20a *g, struct set_fll_clk *setfllclk) | ||
298 | { | ||
299 | struct pmu_cmd cmd; | ||
300 | struct pmu_payload payload; | ||
301 | u32 status; | ||
302 | u32 seqdesc; | ||
303 | struct nv_pmu_clk_rpc rpccall; | ||
304 | struct clkrpc_pmucmdhandler_params handler; | ||
305 | |||
306 | memset(&payload, 0, sizeof(struct pmu_payload)); | ||
307 | memset(&rpccall, 0, sizeof(struct nv_pmu_clk_rpc)); | ||
308 | memset(&handler, 0, sizeof(struct clkrpc_pmucmdhandler_params)); | ||
309 | |||
310 | if ((setfllclk->gpc2clkmhz == 0) || (setfllclk->xbar2clkmhz == 0) || | ||
311 | (setfllclk->sys2clkmhz == 0) || (setfllclk->voltuv == 0)) | ||
312 | return -EINVAL; | ||
313 | |||
314 | if ((setfllclk->target_regime_id_gpc > CTRL_CLK_FLL_REGIME_ID_FR) || | ||
315 | (setfllclk->target_regime_id_sys > CTRL_CLK_FLL_REGIME_ID_FR) || | ||
316 | (setfllclk->target_regime_id_xbar > CTRL_CLK_FLL_REGIME_ID_FR)) | ||
317 | return -EINVAL; | ||
318 | |||
319 | rpccall.function = NV_PMU_CLK_RPC_ID_CLK_VF_CHANGE_INJECT; | ||
320 | |||
321 | g->ops.pmu_ver.clk.clk_vf_change_inject_data_fill(g, | ||
322 | &rpccall, setfllclk); | ||
323 | |||
279 | cmd.hdr.unit_id = PMU_UNIT_CLK; | 324 | cmd.hdr.unit_id = PMU_UNIT_CLK; |
280 | cmd.hdr.size = (u32)sizeof(struct nv_pmu_clk_cmd) + | 325 | cmd.hdr.size = (u32)sizeof(struct nv_pmu_clk_cmd) + |
281 | (u32)sizeof(struct pmu_hdr); | 326 | (u32)sizeof(struct pmu_hdr); |
diff --git a/drivers/gpu/nvgpu/clk/clk.h b/drivers/gpu/nvgpu/clk/clk.h index a19e2e77..019a1c11 100644 --- a/drivers/gpu/nvgpu/clk/clk.h +++ b/drivers/gpu/nvgpu/clk/clk.h | |||
@@ -127,4 +127,10 @@ u32 clk_domain_get_f_points( | |||
127 | int clk_get_fll_clks(struct gk20a *g, struct set_fll_clk *fllclk); | 127 | int clk_get_fll_clks(struct gk20a *g, struct set_fll_clk *fllclk); |
128 | int clk_set_fll_clks(struct gk20a *g, struct set_fll_clk *fllclk); | 128 | int clk_set_fll_clks(struct gk20a *g, struct set_fll_clk *fllclk); |
129 | int clk_pmu_freq_controller_load(struct gk20a *g, bool bload, u8 bit_idx); | 129 | int clk_pmu_freq_controller_load(struct gk20a *g, bool bload, u8 bit_idx); |
130 | u32 nvgpu_clk_vf_change_inject_data_fill_gv10x(struct gk20a *g, | ||
131 | struct nv_pmu_clk_rpc *rpccall, | ||
132 | struct set_fll_clk *setfllclk); | ||
133 | u32 nvgpu_clk_vf_change_inject_data_fill_gp10x(struct gk20a *g, | ||
134 | struct nv_pmu_clk_rpc *rpccall, | ||
135 | struct set_fll_clk *setfllclk); | ||
130 | #endif | 136 | #endif |