diff options
Diffstat (limited to 'drivers/gpu/nvgpu/clk/clk_freq_controller.h')
-rw-r--r-- | drivers/gpu/nvgpu/clk/clk_freq_controller.h | 74 |
1 files changed, 74 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/clk/clk_freq_controller.h b/drivers/gpu/nvgpu/clk/clk_freq_controller.h new file mode 100644 index 00000000..957a4f08 --- /dev/null +++ b/drivers/gpu/nvgpu/clk/clk_freq_controller.h | |||
@@ -0,0 +1,74 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | */ | ||
13 | |||
14 | #ifndef _CLK_FREQ_CONTROLLER_H_ | ||
15 | #define _CLK_FREQ_CONTROLLER_H_ | ||
16 | |||
17 | #define CTRL_CLK_CLK_FREQ_CONTROLLER_ID_SYS 0x00 | ||
18 | #define CTRL_CLK_CLK_FREQ_CONTROLLER_ID_LTC 0x01 | ||
19 | #define CTRL_CLK_CLK_FREQ_CONTROLLER_ID_XBAR 0x02 | ||
20 | #define CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC0 0x03 | ||
21 | #define CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC1 0x04 | ||
22 | #define CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC2 0x05 | ||
23 | #define CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC3 0x06 | ||
24 | #define CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC4 0x07 | ||
25 | #define CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC5 0x08 | ||
26 | #define CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPCS 0x09 | ||
27 | |||
28 | #define CTRL_CLK_CLK_FREQ_CONTROLLER_MASK_UNICAST_GPC \ | ||
29 | (BIT(CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC0) | \ | ||
30 | BIT(CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC1) | \ | ||
31 | BIT(CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC2) | \ | ||
32 | BIT(CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC3) | \ | ||
33 | BIT(CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC4) | \ | ||
34 | BIT(CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC5)) | ||
35 | |||
36 | #define CTRL_CLK_CLK_FREQ_CONTROLLER_TYPE_DISABLED 0x00 | ||
37 | #define CTRL_CLK_CLK_FREQ_CONTROLLER_TYPE_PI 0x01 | ||
38 | |||
39 | |||
40 | struct clk_freq_controller { | ||
41 | struct boardobj super; | ||
42 | u8 controller_id; | ||
43 | u8 parts_freq_mode; | ||
44 | bool bdisable; | ||
45 | u32 clk_domain; | ||
46 | s16 freq_cap_noise_unaware_vmin_above; | ||
47 | s16 freq_cap_noise_unaware_vmin_below; | ||
48 | s16 freq_hyst_pos_mhz; | ||
49 | s16 freq_hyst_neg_mhz; | ||
50 | }; | ||
51 | |||
52 | struct clk_freq_controller_pi { | ||
53 | struct clk_freq_controller super; | ||
54 | s32 prop_gain; | ||
55 | s32 integ_gain; | ||
56 | s32 integ_decay; | ||
57 | s32 volt_delta_min; | ||
58 | s32 volt_delta_max; | ||
59 | u8 slowdown_pct_min; | ||
60 | bool bpoison; | ||
61 | }; | ||
62 | |||
63 | struct clk_freq_controllers { | ||
64 | struct boardobjgrp_e32 super; | ||
65 | u32 sampling_period_ms; | ||
66 | struct boardobjgrpmask_e32 freq_ctrl_load_mask; | ||
67 | u8 volt_policy_idx; | ||
68 | void *pprereq_load; | ||
69 | }; | ||
70 | |||
71 | u32 clk_freq_controller_sw_setup(struct gk20a *g); | ||
72 | u32 clk_freq_controller_pmu_setup(struct gk20a *g); | ||
73 | |||
74 | #endif | ||