1 files changed, 125 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/clk/clk_domain.h b/drivers/gpu/nvgpu/clk/clk_domain.h
new file mode 100644
index 00000000..5374d643
--- /dev/null
+++ b/drivers/gpu/nvgpu/clk/clk_domain.h
@@ -0,0 +1,125 @@
+/*
+* Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+*
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+*/
+#ifndef _CLKDOMAIN_H_
+#define _CLKDOMAIN_H_
+#include "ctrl/ctrlclk.h"
+#include "ctrl/ctrlboardobj.h"
+#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
+#include "boardobj/boardobjgrp_e32.h"
+#include "boardobj/boardobjgrpmask.h"
+struct clk_domains;
+struct clk_domain;
+/*data and function definition to talk to driver*/
+u32 clk_domain_sw_setup(struct gk20a *g);
+u32 clk_domain_pmu_setup(struct gk20a *g);
+typedef u32 clkproglink(struct gk20a *g, struct clk_pmupstate *pclk,
+                        struct clk_domain *pdomain);
+typedef int clkvfsearch(struct gk20a *g, struct clk_pmupstate *pclk,
+                        struct clk_domain *pdomain, u16 *clkmhz,
+                        u32 *voltuv, u8 rail);
+typedef int clkgetslaveclk(struct gk20a *g, struct clk_pmupstate *pclk,
+                        struct clk_domain *pdomain, u16 *clkmhz,
+                        u16 masterclkmhz);
+typedef u32 clkgetfpoints(struct gk20a *g, struct clk_pmupstate *pclk,
+                        struct clk_domain *pdomain, u32 *pfpointscount,
+                          u16 *pfreqpointsinmhz, u8 rail);
+struct clk_domains {
+        struct boardobjgrp_e32 super;
+        u8 n_num_entries;
+        u8 version;
+        bool b_enforce_vf_monotonicity;
+        bool b_enforce_vf_smoothening;
+        u32 vbios_domains;
+        struct boardobjgrpmask_e32 prog_domains_mask;
+        struct boardobjgrpmask_e32 master_domains_mask;
+        u16 cntr_sampling_periodms;
+        struct ctrl_clk_clk_delta  deltas;
+        struct clk_domain *ordered_noise_aware_list[CTRL_BOARDOBJ_MAX_BOARD_OBJECTS];
+        struct clk_domain *ordered_noise_unaware_list[CTRL_BOARDOBJ_MAX_BOARD_OBJECTS];
+};
+struct clk_domain {
+        struct boardobj super;
+        u32 api_domain;
+        u32 part_mask;
+        u8 domain;
+        u8 perf_domain_index;
+        u8 perf_domain_grp_idx;
+        u8 ratio_domain;
+        u8 usage;
+        clkproglink *clkdomainclkproglink;
+        clkvfsearch *clkdomainclkvfsearch;
+        clkgetfpoints *clkdomainclkgetfpoints;
+};
+struct clk_domain_3x {
+        struct clk_domain super;
+        bool b_noise_aware_capable;
+};
+struct clk_domain_3x_fixed {
+        struct clk_domain_3x super;
+        u16  freq_mhz;
+};
+struct clk_domain_3x_prog {
+        struct clk_domain_3x super;
+        u8  clk_prog_idx_first;
+        u8  clk_prog_idx_last;
+        u8 noise_unaware_ordering_index;
+        u8 noise_aware_ordering_index;
+        bool b_force_noise_unaware_ordering;
+        int factory_offset_khz;
+        short freq_delta_min_mhz;
+        short freq_delta_max_mhz;
+        struct ctrl_clk_clk_delta deltas;
+};
+struct clk_domain_3x_master {
+        struct clk_domain_3x_prog super;
+        u32 slave_idxs_mask;
+};
+struct clk_domain_3x_slave {
+        struct clk_domain_3x_prog super;
+        u8 master_idx;
+        clkgetslaveclk *clkdomainclkgetslaveclk;
+};
+u32 clk_domain_clk_prog_link(struct gk20a *g, struct clk_pmupstate *pclk);
+#define CLK_CLK_DOMAIN_GET(pclk, idx)                                   \
+        ((struct clk_domain *)BOARDOBJGRP_OBJ_GET_BY_IDX(               \
+                &pclk->clk_domainobjs.super.super, (u8)(idx)))
+#endif

diff --git a/drivers/gpu/nvgpu/clk/clk_domain.h b/drivers/gpu/nvgpu/clk/clk_domain.h new file mode 100644 index 00000000..5374d643 --- /dev/null +++ b/drivers/gpu/nvgpu/clk/clk_domain.h
@@ -0,0 +1,125 @@
	1	/*
	2	* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	18	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	19	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	20	* DEALINGS IN THE SOFTWARE.
	21	*/
	22
	23	#ifndef _CLKDOMAIN_H_
	24	#define _CLKDOMAIN_H_
	25
	26	#include "ctrl/ctrlclk.h"
	27	#include "ctrl/ctrlboardobj.h"
	28	#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
	29	#include "boardobj/boardobjgrp_e32.h"
	30	#include "boardobj/boardobjgrpmask.h"
	31
	32	struct clk_domains;
	33	struct clk_domain;
	34
	35	/data and function definition to talk to driver/
	36	u32 clk_domain_sw_setup(struct gk20a *g);
	37	u32 clk_domain_pmu_setup(struct gk20a *g);
	38
	39	typedef u32 clkproglink(struct gk20a g, struct clk_pmupstate pclk,
	40	struct clk_domain *pdomain);
	41
	42	typedef int clkvfsearch(struct gk20a g, struct clk_pmupstate pclk,
	43	struct clk_domain pdomain, u16 clkmhz,
	44	u32 *voltuv, u8 rail);
	45
	46	typedef int clkgetslaveclk(struct gk20a g, struct clk_pmupstate pclk,
	47	struct clk_domain pdomain, u16 clkmhz,
	48	u16 masterclkmhz);
	49
	50	typedef u32 clkgetfpoints(struct gk20a g, struct clk_pmupstate pclk,
	51	struct clk_domain pdomain, u32 pfpointscount,
	52	u16 *pfreqpointsinmhz, u8 rail);
	53
	54	struct clk_domains {
	55	struct boardobjgrp_e32 super;
	56	u8 n_num_entries;
	57	u8 version;
	58	bool b_enforce_vf_monotonicity;
	59	bool b_enforce_vf_smoothening;
	60	u32 vbios_domains;
	61	struct boardobjgrpmask_e32 prog_domains_mask;
	62	struct boardobjgrpmask_e32 master_domains_mask;
	63	u16 cntr_sampling_periodms;
	64	struct ctrl_clk_clk_delta deltas;
	65
	66	struct clk_domain *ordered_noise_aware_list[CTRL_BOARDOBJ_MAX_BOARD_OBJECTS];
	67
	68	struct clk_domain *ordered_noise_unaware_list[CTRL_BOARDOBJ_MAX_BOARD_OBJECTS];
	69	};
	70
	71	struct clk_domain {
	72	struct boardobj super;
	73	u32 api_domain;
	74	u32 part_mask;
	75	u8 domain;
	76	u8 perf_domain_index;
	77	u8 perf_domain_grp_idx;
	78	u8 ratio_domain;
	79	u8 usage;
	80	clkproglink *clkdomainclkproglink;
	81	clkvfsearch *clkdomainclkvfsearch;
	82	clkgetfpoints *clkdomainclkgetfpoints;
	83	};
	84
	85	struct clk_domain_3x {
	86	struct clk_domain super;
	87	bool b_noise_aware_capable;
	88	};
	89
	90	struct clk_domain_3x_fixed {
	91	struct clk_domain_3x super;
	92	u16 freq_mhz;
	93	};
	94
	95	struct clk_domain_3x_prog {
	96	struct clk_domain_3x super;
	97	u8 clk_prog_idx_first;
	98	u8 clk_prog_idx_last;
	99	u8 noise_unaware_ordering_index;
	100	u8 noise_aware_ordering_index;
	101	bool b_force_noise_unaware_ordering;
	102	int factory_offset_khz;
	103	short freq_delta_min_mhz;
	104	short freq_delta_max_mhz;
	105	struct ctrl_clk_clk_delta deltas;
	106	};
	107
	108	struct clk_domain_3x_master {
	109	struct clk_domain_3x_prog super;
	110	u32 slave_idxs_mask;
	111	};
	112
	113	struct clk_domain_3x_slave {
	114	struct clk_domain_3x_prog super;
	115	u8 master_idx;
	116	clkgetslaveclk *clkdomainclkgetslaveclk;
	117	};
	118
	119	u32 clk_domain_clk_prog_link(struct gk20a g, struct clk_pmupstate pclk);
	120
	121	#define CLK_CLK_DOMAIN_GET(pclk, idx) \
	122	((struct clk_domain *)BOARDOBJGRP_OBJ_GET_BY_IDX( \
	123	&pclk->clk_domainobjs.super.super, (u8)(idx)))
	124
	125	#endif