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path: root/drivers/gpu/nvgpu/clk/clk_common.c
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Diffstat (limited to 'drivers/gpu/nvgpu/clk/clk_common.c')
-rw-r--r--drivers/gpu/nvgpu/clk/clk_common.c62
1 files changed, 0 insertions, 62 deletions
diff --git a/drivers/gpu/nvgpu/clk/clk_common.c b/drivers/gpu/nvgpu/clk/clk_common.c
deleted file mode 100644
index 0704ba2b..00000000
--- a/drivers/gpu/nvgpu/clk/clk_common.c
+++ /dev/null
@@ -1,62 +0,0 @@
1/*
2 * Copyright (c) 2011-2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <linux/clk.h>
18
19#include "gk20a/gk20a.h"
20#include "gk20a/platform_gk20a.h"
21
22struct clk *gk20a_clk_get(struct gk20a *g)
23{
24 if (!g->clk.tegra_clk) {
25 struct clk *clk;
26 char clk_dev_id[32];
27 struct device *dev = dev_from_gk20a(g);
28
29 snprintf(clk_dev_id, 32, "tegra_%s", dev_name(dev));
30
31 clk = clk_get_sys(clk_dev_id, "gpu");
32 if (IS_ERR(clk)) {
33 nvgpu_err(g, "fail to get tegra gpu clk %s/gpu\n",
34 clk_dev_id);
35 return NULL;
36 }
37 g->clk.tegra_clk = clk;
38 }
39
40 return g->clk.tegra_clk;
41}
42
43unsigned long gk20a_clk_get_rate(struct gk20a *g)
44{
45 struct clk_gk20a *clk = &g->clk;
46 return rate_gpc2clk_to_gpu(clk->gpc_pll.freq);
47}
48
49long gk20a_clk_round_rate(struct gk20a *g, unsigned long rate)
50{
51 /* make sure the clock is available */
52 if (!gk20a_clk_get(g))
53 return rate;
54
55 return clk_round_rate(clk_get_parent(g->clk.tegra_clk), rate);
56}
57
58int gk20a_clk_set_rate(struct gk20a *g, unsigned long rate)
59{
60 return clk_set_rate(g->clk.tegra_clk, rate);
61}
62