diff options
Diffstat (limited to 'drivers/gpu/nvgpu/clk/clk.h')
-rw-r--r-- | drivers/gpu/nvgpu/clk/clk.h | 130 |
1 files changed, 130 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/clk/clk.h b/drivers/gpu/nvgpu/clk/clk.h new file mode 100644 index 00000000..a19e2e77 --- /dev/null +++ b/drivers/gpu/nvgpu/clk/clk.h | |||
@@ -0,0 +1,130 @@ | |||
1 | /* | ||
2 | * general clock structures & definitions | ||
3 | * | ||
4 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | #ifndef _CLK_H_ | ||
25 | #define _CLK_H_ | ||
26 | |||
27 | #include "clk_vin.h" | ||
28 | #include "clk_fll.h" | ||
29 | #include "clk_domain.h" | ||
30 | #include "clk_prog.h" | ||
31 | #include "clk_vf_point.h" | ||
32 | #include "clk_mclk.h" | ||
33 | #include "clk_freq_controller.h" | ||
34 | |||
35 | #define NV_PERF_DOMAIN_4X_CLOCK_DOMAIN_SKIP 0x10 | ||
36 | #define NV_PERF_DOMAIN_4X_CLOCK_DOMAIN_MASK 0x1F | ||
37 | #define NV_PERF_DOMAIN_4X_CLOCK_DOMAIN_SHIFT 0 | ||
38 | |||
39 | struct gk20a; | ||
40 | |||
41 | /* clock related defines for GPUs supporting clock control from pmu*/ | ||
42 | struct clk_pmupstate { | ||
43 | struct avfsvinobjs avfs_vinobjs; | ||
44 | struct avfsfllobjs avfs_fllobjs; | ||
45 | struct clk_domains clk_domainobjs; | ||
46 | struct clk_progs clk_progobjs; | ||
47 | struct clk_vf_points clk_vf_pointobjs; | ||
48 | struct clk_mclk_state clk_mclk; | ||
49 | struct clk_freq_controllers clk_freq_controllers; | ||
50 | }; | ||
51 | |||
52 | struct clockentry { | ||
53 | u8 vbios_clk_domain; | ||
54 | u8 clk_which; | ||
55 | u8 perf_index; | ||
56 | u32 api_clk_domain; | ||
57 | }; | ||
58 | |||
59 | struct set_fll_clk { | ||
60 | u32 voltuv; | ||
61 | u16 gpc2clkmhz; | ||
62 | u32 current_regime_id_gpc; | ||
63 | u32 target_regime_id_gpc; | ||
64 | u16 sys2clkmhz; | ||
65 | u32 current_regime_id_sys; | ||
66 | u32 target_regime_id_sys; | ||
67 | u16 xbar2clkmhz; | ||
68 | u32 current_regime_id_xbar; | ||
69 | u32 target_regime_id_xbar; | ||
70 | }; | ||
71 | |||
72 | #define NV_PERF_HEADER_4X_CLOCKS_DOMAINS_MAX_NUMCLKS 9 | ||
73 | |||
74 | struct vbios_clock_domain { | ||
75 | u8 clock_type; | ||
76 | u8 num_domains; | ||
77 | struct clockentry clock_entry[NV_PERF_HEADER_4X_CLOCKS_DOMAINS_MAX_NUMCLKS]; | ||
78 | }; | ||
79 | |||
80 | struct vbios_clocks_table_1x_hal_clock_entry { | ||
81 | enum nv_pmu_clk_clkwhich domain; | ||
82 | bool b_noise_aware_capable; | ||
83 | }; | ||
84 | |||
85 | #define NV_PERF_HEADER_4X_CLOCKS_DOMAINS_4_GPC2CLK 0 | ||
86 | #define NV_PERF_HEADER_4X_CLOCKS_DOMAINS_4_XBAR2CLK 1 | ||
87 | #define NV_PERF_HEADER_4X_CLOCKS_DOMAINS_4_DRAMCLK 2 | ||
88 | #define NV_PERF_HEADER_4X_CLOCKS_DOMAINS_4_SYS2CLK 3 | ||
89 | #define NV_PERF_HEADER_4X_CLOCKS_DOMAINS_4_HUB2CLK 4 | ||
90 | #define NV_PERF_HEADER_4X_CLOCKS_DOMAINS_4_MSDCLK 5 | ||
91 | #define NV_PERF_HEADER_4X_CLOCKS_DOMAINS_4_PWRCLK 6 | ||
92 | #define NV_PERF_HEADER_4X_CLOCKS_DOMAINS_4_DISPCLK 7 | ||
93 | #define NV_PERF_HEADER_4X_CLOCKS_DOMAINS_4_NUMCLKS 8 | ||
94 | |||
95 | #define PERF_CLK_MCLK 0 | ||
96 | #define PERF_CLK_DISPCLK 1 | ||
97 | #define PERF_CLK_GPC2CLK 2 | ||
98 | #define PERF_CLK_HOSTCLK 3 | ||
99 | #define PERF_CLK_LTC2CLK 4 | ||
100 | #define PERF_CLK_SYS2CLK 5 | ||
101 | #define PERF_CLK_HUB2CLK 6 | ||
102 | #define PERF_CLK_LEGCLK 7 | ||
103 | #define PERF_CLK_MSDCLK 8 | ||
104 | #define PERF_CLK_XCLK 9 | ||
105 | #define PERF_CLK_PWRCLK 10 | ||
106 | #define PERF_CLK_XBAR2CLK 11 | ||
107 | #define PERF_CLK_PCIEGENCLK 12 | ||
108 | #define PERF_CLK_NUM 13 | ||
109 | |||
110 | #define BOOT_GPC2CLK_MHZ 2581 | ||
111 | |||
112 | u32 clk_pmu_vin_load(struct gk20a *g); | ||
113 | u32 clk_domain_print_vf_table(struct gk20a *g, u32 clkapidomain); | ||
114 | u32 clk_domain_get_f_or_v( | ||
115 | struct gk20a *g, | ||
116 | u32 clkapidomain, | ||
117 | u16 *pclkmhz, | ||
118 | u32 *pvoltuv, | ||
119 | u8 railidx | ||
120 | ); | ||
121 | u32 clk_domain_get_f_points( | ||
122 | struct gk20a *g, | ||
123 | u32 clkapidomain, | ||
124 | u32 *fpointscount, | ||
125 | u16 *freqpointsinmhz | ||
126 | ); | ||
127 | int clk_get_fll_clks(struct gk20a *g, struct set_fll_clk *fllclk); | ||
128 | int clk_set_fll_clks(struct gk20a *g, struct set_fll_clk *fllclk); | ||
129 | int clk_pmu_freq_controller_load(struct gk20a *g, bool bload, u8 bit_idx); | ||
130 | #endif | ||