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path: root/drivers/gpu/nvgpu/clk/clk.h
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Diffstat (limited to 'drivers/gpu/nvgpu/clk/clk.h')
-rw-r--r--drivers/gpu/nvgpu/clk/clk.h8
1 files changed, 1 insertions, 7 deletions
diff --git a/drivers/gpu/nvgpu/clk/clk.h b/drivers/gpu/nvgpu/clk/clk.h
index cd65f6f5..afff6963 100644
--- a/drivers/gpu/nvgpu/clk/clk.h
+++ b/drivers/gpu/nvgpu/clk/clk.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * general clock structures & definitions 2 * general clock structures & definitions
3 * 3 *
4 * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a 6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"), 7 * copy of this software and associated documentation files (the "Software"),
@@ -127,12 +127,6 @@ u32 clk_domain_get_f_or_v(
127 u32 *pvoltuv, 127 u32 *pvoltuv,
128 u8 railidx 128 u8 railidx
129); 129);
130u32 clk_domain_get_f_points(
131 struct gk20a *g,
132 u32 clkapidomain,
133 u32 *fpointscount,
134 u16 *freqpointsinmhz
135);
136int clk_get_fll_clks(struct gk20a *g, struct set_fll_clk *fllclk); 130int clk_get_fll_clks(struct gk20a *g, struct set_fll_clk *fllclk);
137int clk_set_fll_clks(struct gk20a *g, struct set_fll_clk *fllclk); 131int clk_set_fll_clks(struct gk20a *g, struct set_fll_clk *fllclk);
138int clk_pmu_freq_controller_load(struct gk20a *g, bool bload, u8 bit_idx); 132int clk_pmu_freq_controller_load(struct gk20a *g, bool bload, u8 bit_idx);