1 files changed, 35 insertions, 5 deletions
diff --git a/drivers/gpu/nvgpu/clk/clk.c b/drivers/gpu/nvgpu/clk/clk.c
index 99b5b17c..3906be48 100644
--- a/drivers/gpu/nvgpu/clk/clk.c
+++ b/drivers/gpu/nvgpu/clk/clk.c
@@ -55,7 +55,7 @@ static void clkrpc_pmucmdhandler(struct gk20a *g, struct pmu_msg *msg,
                phandlerparams->success = 1;
 }
-int clk_pmu_freq_controller_load(struct gk20a *g, bool bload)
+int clk_pmu_freq_controller_load(struct gk20a *g, bool bload, u8 bit_idx)
 {
        struct pmu_cmd cmd;
        struct pmu_msg msg;
@@ -67,6 +67,7 @@ int clk_pmu_freq_controller_load(struct gk20a *g, bool bload)
        struct nv_pmu_clk_load *clkload;
        struct clk_freq_controllers *pclk_freq_controllers;
        struct ctrl_boardobjgrp_mask_e32 *load_mask;
+        struct boardobjgrpmask_e32 isolate_cfc_mask;
        memset(&payload, 0, sizeof(struct pmu_payload));
        memset(&rpccall, 0, sizeof(struct nv_pmu_clk_rpc));
@@ -82,10 +83,39 @@ int clk_pmu_freq_controller_load(struct gk20a *g, bool bload)
        load_mask = &rpccall.params.clk_load.payload.freq_controllers.load_mask;
-        status = boardobjgrpmask_export(
+        status = boardobjgrpmask_e32_init(&isolate_cfc_mask, NULL);
-                &pclk_freq_controllers->freq_ctrl_load_mask.super,
-                pclk_freq_controllers->freq_ctrl_load_mask.super.bitcount,
+        if (bit_idx == CTRL_CLK_CLK_FREQ_CONTROLLER_ID_ALL) {
-                &load_mask->super);
+                status = boardobjgrpmask_export(
+                                &pclk_freq_controllers->
+                                        freq_ctrl_load_mask.super,
+                                pclk_freq_controllers->
+                                        freq_ctrl_load_mask.super.bitcount,
+                                &load_mask->super);
+        } else {
+                status = boardobjgrpmask_bitset(&isolate_cfc_mask.super,
+                                                bit_idx);
+                status = boardobjgrpmask_export(&isolate_cfc_mask.super,
+                                        isolate_cfc_mask.super.bitcount,
+                                        &load_mask->super);
+                if (bload)
+                        status = boardobjgrpmask_bitset(
+                                        &pclk_freq_controllers->
+                                                freq_ctrl_load_mask.super,
+                                        bit_idx);
+                else
+                        status = boardobjgrpmask_bitclr(
+                                        &pclk_freq_controllers->
+                                                freq_ctrl_load_mask.super,
+                                        bit_idx);
+        }
+        if (status) {
+                nvgpu_err(g, "Error in generating mask used to select CFC");
+                goto done;
+        }
        cmd.hdr.unit_id = PMU_UNIT_CLK;
        cmd.hdr.size =  (u32)sizeof(struct nv_pmu_clk_cmd) +

diff --git a/drivers/gpu/nvgpu/clk/clk.c b/drivers/gpu/nvgpu/clk/clk.c index 99b5b17c..3906be48 100644 --- a/drivers/gpu/nvgpu/clk/clk.c +++ b/drivers/gpu/nvgpu/clk/clk.c
@@ -55,7 +55,7 @@ static void clkrpc_pmucmdhandler(struct gk20a g, struct pmu_msg msg,
55	phandlerparams->success = 1;	55	phandlerparams->success = 1;
56	}	56	}
57		57
58	int clk_pmu_freq_controller_load(struct gk20a *g, bool bload)	58	int clk_pmu_freq_controller_load(struct gk20a *g, bool bload, u8 bit_idx)
59	{	59	{
60	struct pmu_cmd cmd;	60	struct pmu_cmd cmd;
61	struct pmu_msg msg;	61	struct pmu_msg msg;
@@ -67,6 +67,7 @@ int clk_pmu_freq_controller_load(struct gk20a *g, bool bload)
67	struct nv_pmu_clk_load *clkload;	67	struct nv_pmu_clk_load *clkload;
68	struct clk_freq_controllers *pclk_freq_controllers;	68	struct clk_freq_controllers *pclk_freq_controllers;
69	struct ctrl_boardobjgrp_mask_e32 *load_mask;	69	struct ctrl_boardobjgrp_mask_e32 *load_mask;
		70	struct boardobjgrpmask_e32 isolate_cfc_mask;
70		71
71	memset(&payload, 0, sizeof(struct pmu_payload));	72	memset(&payload, 0, sizeof(struct pmu_payload));
72	memset(&rpccall, 0, sizeof(struct nv_pmu_clk_rpc));	73	memset(&rpccall, 0, sizeof(struct nv_pmu_clk_rpc));
@@ -82,10 +83,39 @@ int clk_pmu_freq_controller_load(struct gk20a *g, bool bload)
82		83
83	load_mask = &rpccall.params.clk_load.payload.freq_controllers.load_mask;	84	load_mask = &rpccall.params.clk_load.payload.freq_controllers.load_mask;
84		85
85	status = boardobjgrpmask_export(	86	status = boardobjgrpmask_e32_init(&isolate_cfc_mask, NULL);
86	&pclk_freq_controllers->freq_ctrl_load_mask.super,	87
87	pclk_freq_controllers->freq_ctrl_load_mask.super.bitcount,	88	if (bit_idx == CTRL_CLK_CLK_FREQ_CONTROLLER_ID_ALL) {
88	&load_mask->super);	89	status = boardobjgrpmask_export(
		90	&pclk_freq_controllers->
		91	freq_ctrl_load_mask.super,
		92	pclk_freq_controllers->
		93	freq_ctrl_load_mask.super.bitcount,
		94	&load_mask->super);
		95
		96
		97	} else {
		98	status = boardobjgrpmask_bitset(&isolate_cfc_mask.super,
		99	bit_idx);
		100	status = boardobjgrpmask_export(&isolate_cfc_mask.super,
		101	isolate_cfc_mask.super.bitcount,
		102	&load_mask->super);
		103	if (bload)
		104	status = boardobjgrpmask_bitset(
		105	&pclk_freq_controllers->
		106	freq_ctrl_load_mask.super,
		107	bit_idx);
		108	else
		109	status = boardobjgrpmask_bitclr(
		110	&pclk_freq_controllers->
		111	freq_ctrl_load_mask.super,
		112	bit_idx);
		113	}
		114
		115	if (status) {
		116	nvgpu_err(g, "Error in generating mask used to select CFC");
		117	goto done;
		118	}
89		119
90	cmd.hdr.unit_id = PMU_UNIT_CLK;	120	cmd.hdr.unit_id = PMU_UNIT_CLK;
91	cmd.hdr.size = (u32)sizeof(struct nv_pmu_clk_cmd) +	121	cmd.hdr.size = (u32)sizeof(struct nv_pmu_clk_cmd) +