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Diffstat (limited to 'drivers/gpu/nvgpu/boardobj/boardobjgrp_e255.c')
-rw-r--r--drivers/gpu/nvgpu/boardobj/boardobjgrp_e255.c86
1 files changed, 86 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/boardobj/boardobjgrp_e255.c b/drivers/gpu/nvgpu/boardobj/boardobjgrp_e255.c
new file mode 100644
index 00000000..7aabb89e
--- /dev/null
+++ b/drivers/gpu/nvgpu/boardobj/boardobjgrp_e255.c
@@ -0,0 +1,86 @@
1/*
2* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
3*
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21*/
22
23#include "gk20a/gk20a.h"
24#include "boardobj.h"
25#include "boardobjgrp_e255.h"
26#include "ctrl/ctrlboardobj.h"
27#include "boardobjgrp.h"
28#include "boardobjgrpmask.h"
29
30u32 boardobjgrpconstruct_e255(struct gk20a *g,
31 struct boardobjgrp_e255 *pboardobjgrp_e255)
32{
33 u32 status = 0;
34 u8 objslots;
35
36 gk20a_dbg_info("");
37
38 objslots = 255;
39 status = boardobjgrpmask_e255_init(&pboardobjgrp_e255->mask, NULL);
40 if (status)
41 goto boardobjgrpconstruct_e255_exit;
42
43 pboardobjgrp_e255->super.type = CTRL_BOARDOBJGRP_TYPE_E255;
44 pboardobjgrp_e255->super.ppobjects = pboardobjgrp_e255->objects;
45 pboardobjgrp_e255->super.objslots = objslots;
46 pboardobjgrp_e255->super.mask = &(pboardobjgrp_e255->mask.super);
47
48 status = boardobjgrp_construct_super(g, &pboardobjgrp_e255->super);
49 if (status)
50 goto boardobjgrpconstruct_e255_exit;
51
52 pboardobjgrp_e255->super.pmuhdrdatainit =
53 boardobjgrp_pmuhdrdatainit_e255;
54
55boardobjgrpconstruct_e255_exit:
56 return status;
57}
58
59u32 boardobjgrp_pmuhdrdatainit_e255(struct gk20a *g,
60 struct boardobjgrp *pboardobjgrp,
61 struct nv_pmu_boardobjgrp_super *pboardobjgrppmu,
62 struct boardobjgrpmask *mask)
63{
64 struct nv_pmu_boardobjgrp_e255 *pgrpe255 =
65 (struct nv_pmu_boardobjgrp_e255 *)pboardobjgrppmu;
66 u32 status;
67
68 gk20a_dbg_info("");
69
70 if (pboardobjgrp == NULL)
71 return -EINVAL;
72
73 if (pboardobjgrppmu == NULL)
74 return -EINVAL;
75
76 status = boardobjgrpmask_export(mask,
77 mask->bitcount,
78 &pgrpe255->obj_mask.super);
79 if (status) {
80 nvgpu_err(g, "e255 init:failed export grpmask");
81 return status;
82 }
83
84 return boardobjgrp_pmuhdrdatainit_super(g,
85 pboardobjgrp, pboardobjgrppmu, mask);
86}