diff options
3 files changed, 111 insertions, 12 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.c b/drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.c index b780457f..e7777871 100644 --- a/drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GP10B priv ring | 2 | * GP10B priv ring |
3 | * | 3 | * |
4 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -33,6 +33,69 @@ | |||
33 | #include <nvgpu/hw/gp10b/hw_pri_ringstation_sys_gp10b.h> | 33 | #include <nvgpu/hw/gp10b/hw_pri_ringstation_sys_gp10b.h> |
34 | #include <nvgpu/hw/gp10b/hw_pri_ringstation_gpc_gp10b.h> | 34 | #include <nvgpu/hw/gp10b/hw_pri_ringstation_gpc_gp10b.h> |
35 | 35 | ||
36 | static const char * const invalid_str = "invalid"; | ||
37 | |||
38 | static const char *const error_type_badf1xyy[] = { | ||
39 | "client timeout", | ||
40 | "decode error", | ||
41 | "client in reset", | ||
42 | "client floorswept", | ||
43 | "client stuck ack", | ||
44 | "client expected ack", | ||
45 | "fence error", | ||
46 | "subid error", | ||
47 | "byte access unsupported", | ||
48 | }; | ||
49 | |||
50 | static const char *const error_type_badf2xyy[] = { | ||
51 | "orphan gpc/fbp" | ||
52 | }; | ||
53 | |||
54 | static const char *const error_type_badf3xyy[] = { | ||
55 | "priv ring dead" | ||
56 | }; | ||
57 | |||
58 | static const char *const error_type_badf5xyy[] = { | ||
59 | "client error", | ||
60 | "priv level violation", | ||
61 | "indirect priv level violation", | ||
62 | "local local ring error", | ||
63 | "falcon mem access priv level violation", | ||
64 | "pri route error" | ||
65 | }; | ||
66 | |||
67 | static void gp10b_priv_ring_decode_error_code(struct gk20a *g, | ||
68 | u32 error_code) | ||
69 | { | ||
70 | u32 error_type, error_type_index; | ||
71 | |||
72 | error_type = (error_code & 0x0000f000) >> 24; | ||
73 | error_type_index = (error_code & 0x00000f00) >> 16; | ||
74 | error_code = error_code & 0xBADFf000; | ||
75 | |||
76 | if (error_code == 0xBADF1000) { | ||
77 | if (error_type_index < | ||
78 | ARRAY_SIZE(error_type_badf1xyy)) | ||
79 | nvgpu_err(g, "%s", | ||
80 | error_type_badf1xyy[error_type_index]); | ||
81 | } else if (error_code == 0xBADF2000) { | ||
82 | if (error_type_index < | ||
83 | ARRAY_SIZE(error_type_badf2xyy)) | ||
84 | nvgpu_err(g, "%s", | ||
85 | error_type_badf2xyy[error_type_index]); | ||
86 | } else if (error_code == 0xBADF3000) { | ||
87 | if (error_type_index < | ||
88 | ARRAY_SIZE(error_type_badf3xyy)) | ||
89 | nvgpu_err(g, "%s", | ||
90 | error_type_badf3xyy[error_type_index]); | ||
91 | } else if (error_code == 0xBADF5000) { | ||
92 | if (error_type_index < | ||
93 | ARRAY_SIZE(error_type_badf5xyy)) | ||
94 | nvgpu_err(g, "%s", | ||
95 | error_type_badf5xyy[error_type_index]); | ||
96 | } | ||
97 | } | ||
98 | |||
36 | void gp10b_priv_ring_isr(struct gk20a *g) | 99 | void gp10b_priv_ring_isr(struct gk20a *g) |
37 | { | 100 | { |
38 | u32 status0, status1; | 101 | u32 status0, status1; |
@@ -40,6 +103,8 @@ void gp10b_priv_ring_isr(struct gk20a *g) | |||
40 | s32 retry = 100; | 103 | s32 retry = 100; |
41 | u32 gpc; | 104 | u32 gpc; |
42 | u32 gpc_stride, offset; | 105 | u32 gpc_stride, offset; |
106 | u32 error_info; | ||
107 | u32 error_code; | ||
43 | 108 | ||
44 | if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { | 109 | if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { |
45 | nvgpu_info(g, "unhandled priv ring intr"); | 110 | nvgpu_info(g, "unhandled priv ring intr"); |
@@ -63,11 +128,20 @@ void gp10b_priv_ring_isr(struct gk20a *g) | |||
63 | nvgpu_err(g, "ring overflowed"); | 128 | nvgpu_err(g, "ring overflowed"); |
64 | 129 | ||
65 | if (pri_ringmaster_intr_status0_gbl_write_error_sys_v(status0) != 0) { | 130 | if (pri_ringmaster_intr_status0_gbl_write_error_sys_v(status0) != 0) { |
66 | nvgpu_err(g, "SYS write error. ADR %08x WRDAT %08x INFO %08x, CODE %08x", | 131 | error_info = |
132 | gk20a_readl(g, pri_ringstation_sys_priv_error_info_r()); | ||
133 | error_code = | ||
134 | gk20a_readl(g, pri_ringstation_sys_priv_error_code_r()); | ||
135 | nvgpu_err(g, "SYS write error. ADR 0x%08x WRDAT 0x%08x " | ||
136 | "INFO 0x%08x (subid 0x%08x priv level %d), " | ||
137 | "CODE 0x%08x", | ||
67 | gk20a_readl(g, pri_ringstation_sys_priv_error_adr_r()), | 138 | gk20a_readl(g, pri_ringstation_sys_priv_error_adr_r()), |
68 | gk20a_readl(g, pri_ringstation_sys_priv_error_wrdat_r()), | 139 | gk20a_readl(g, pri_ringstation_sys_priv_error_wrdat_r()), |
69 | gk20a_readl(g, pri_ringstation_sys_priv_error_info_r()), | 140 | error_info, |
70 | gk20a_readl(g, pri_ringstation_sys_priv_error_code_r())); | 141 | pri_ringstation_sys_priv_error_info_subid_v(error_info), |
142 | pri_ringstation_sys_priv_error_info_priv_level_v(error_info), | ||
143 | error_code); | ||
144 | gp10b_priv_ring_decode_error_code(g, error_code); | ||
71 | } | 145 | } |
72 | 146 | ||
73 | if (status1) { | 147 | if (status1) { |
@@ -75,16 +149,25 @@ void gp10b_priv_ring_isr(struct gk20a *g) | |||
75 | for (gpc = 0; gpc < g->gr.gpc_count; gpc++) { | 149 | for (gpc = 0; gpc < g->gr.gpc_count; gpc++) { |
76 | offset = gpc * gpc_stride; | 150 | offset = gpc * gpc_stride; |
77 | if (status1 & BIT(gpc)) { | 151 | if (status1 & BIT(gpc)) { |
78 | nvgpu_err(g, "GPC%u write error. ADR %08x " | 152 | error_info = gk20a_readl(g, |
79 | "WRDAT %08x INFO %08x, CODE %08x", gpc, | 153 | pri_ringstation_gpc_gpc0_priv_error_info_r() + offset); |
154 | error_code = gk20a_readl(g, | ||
155 | pri_ringstation_gpc_gpc0_priv_error_code_r() + offset); | ||
156 | nvgpu_err(g, "GPC%u write error. ADR 0x%08x " | ||
157 | "WRDAT 0x%08x " | ||
158 | "INFO 0x%08x (subid 0x%08x priv level %d), " | ||
159 | "CODE 0x%08x", gpc, | ||
80 | gk20a_readl(g, | 160 | gk20a_readl(g, |
81 | pri_ringstation_gpc_gpc0_priv_error_adr_r() + offset), | 161 | pri_ringstation_gpc_gpc0_priv_error_adr_r() + offset), |
82 | gk20a_readl(g, | 162 | gk20a_readl(g, |
83 | pri_ringstation_gpc_gpc0_priv_error_wrdat_r() + offset), | 163 | pri_ringstation_gpc_gpc0_priv_error_wrdat_r() + offset), |
84 | gk20a_readl(g, | 164 | error_info, |
85 | pri_ringstation_gpc_gpc0_priv_error_info_r() + offset), | 165 | pri_ringstation_gpc_gpc0_priv_error_info_subid_v(error_info), |
86 | gk20a_readl(g, | 166 | pri_ringstation_gpc_gpc0_priv_error_info_priv_level_v(error_info), |
87 | pri_ringstation_gpc_gpc0_priv_error_code_r() + offset)); | 167 | error_code); |
168 | |||
169 | gp10b_priv_ring_decode_error_code(g, error_code); | ||
170 | |||
88 | status1 = status1 & (~(BIT(gpc))); | 171 | status1 = status1 & (~(BIT(gpc))); |
89 | if (!status1) | 172 | if (!status1) |
90 | break; | 173 | break; |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringstation_gpc_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringstation_gpc_gp10b.h index 1bd5a0f7..ba55658e 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringstation_gpc_gp10b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringstation_gpc_gp10b.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -72,6 +72,14 @@ static inline u32 pri_ringstation_gpc_gpc0_priv_error_info_r(void) | |||
72 | { | 72 | { |
73 | return 0x00128128U; | 73 | return 0x00128128U; |
74 | } | 74 | } |
75 | static inline u32 pri_ringstation_gpc_gpc0_priv_error_info_subid_v(u32 r) | ||
76 | { | ||
77 | return (r >> 24U) & 0x3fU; | ||
78 | } | ||
79 | static inline u32 pri_ringstation_gpc_gpc0_priv_error_info_priv_level_v(u32 r) | ||
80 | { | ||
81 | return (r >> 20U) & 0x3U; | ||
82 | } | ||
75 | static inline u32 pri_ringstation_gpc_gpc0_priv_error_code_r(void) | 83 | static inline u32 pri_ringstation_gpc_gpc0_priv_error_code_r(void) |
76 | { | 84 | { |
77 | return 0x0012812cU; | 85 | return 0x0012812cU; |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringstation_sys_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringstation_sys_gp10b.h index c4d9ef1b..1dcb1a3c 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringstation_sys_gp10b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringstation_sys_gp10b.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -84,6 +84,14 @@ static inline u32 pri_ringstation_sys_priv_error_info_r(void) | |||
84 | { | 84 | { |
85 | return 0x00122128U; | 85 | return 0x00122128U; |
86 | } | 86 | } |
87 | static inline u32 pri_ringstation_sys_priv_error_info_subid_v(u32 r) | ||
88 | { | ||
89 | return (r >> 24U) & 0x3fU; | ||
90 | } | ||
91 | static inline u32 pri_ringstation_sys_priv_error_info_priv_level_v(u32 r) | ||
92 | { | ||
93 | return (r >> 20U) & 0x3U; | ||
94 | } | ||
87 | static inline u32 pri_ringstation_sys_priv_error_code_r(void) | 95 | static inline u32 pri_ringstation_sys_priv_error_code_r(void) |
88 | { | 96 | { |
89 | return 0x0012212cU; | 97 | return 0x0012212cU; |