5 files changed, 40 insertions, 23 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
index ccc3afca..2daeb1d0 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
@@ -1,7 +1,7 @@
 /*
  * GK20A Graphics FIFO (gr host)
  *
- * Copyright (c) 2011-2016, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2011-2017, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -2870,6 +2870,22 @@ int gk20a_fifo_set_runlist_interleave(struct gk20a *g,
         return 0;
 }
 
+int gk20a_fifo_tsg_set_timeslice(struct tsg_gk20a *tsg, u32 timeslice)
+{
+        struct gk20a *g = tsg->g;
+
+        if (timeslice < g->min_timeslice_us ||
+                timeslice > g->max_timeslice_us)
+                return -EINVAL;
+
+        gk20a_channel_get_timescale_from_timeslice(g, timeslice,
+                        &tsg->timeslice_timeout, &tsg->timeslice_scale);
+
+        tsg->timeslice_us = timeslice;
+
+        return g->ops.fifo.update_runlist(g, tsg->runlist_id, ~0, true, true);
+}
+
 static int gk20a_fifo_update_runlist_locked(struct gk20a *g, u32 runlist_id,
                                             u32 hw_chid, bool add,
                                             bool wait_for_finish)
@@ -3296,6 +3312,7 @@ void gk20a_init_fifo(struct gpu_ops *gops)
         gops->fifo.get_num_fifos = gk20a_fifo_get_num_fifos;
         gops->fifo.get_pbdma_signature = gk20a_fifo_get_pbdma_signature;
         gops->fifo.set_runlist_interleave = gk20a_fifo_set_runlist_interleave;
+        gops->fifo.tsg_set_timeslice = gk20a_fifo_tsg_set_timeslice;
         gops->fifo.force_reset_ch = gk20a_fifo_force_reset_ch;
         gops->fifo.engine_enum_from_type = gk20a_fifo_engine_enum_from_type;
         /* gk20a doesn't support device_info_data packet parsing */
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
index c32142e3..20baf9de 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
@@ -3,7 +3,7 @@
  *
  * GK20A graphics fifo (gr host)
  *
- * Copyright (c) 2011-2016, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2011-2017, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -231,6 +231,8 @@ int gk20a_fifo_set_runlist_interleave(struct gk20a *g,
                                 bool is_tsg,
                                 u32 runlist_id,
                                 u32 new_level);
+int gk20a_fifo_tsg_set_timeslice(struct tsg_gk20a *tsg, u32 timeslice);
+
 
 void gk20a_fifo_debugfs_init(struct device *dev);
 
diff --git a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c
index 81a4b78e..96d6873d 100644
--- a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c
@@ -177,27 +177,24 @@ int gk20a_init_tsg_support(struct gk20a *g, u32 tsgid)
 static int gk20a_tsg_set_priority(struct gk20a *g, struct tsg_gk20a *tsg,
                                 u32 priority)
 {
+        u32 timeslice_us;
+
         switch (priority) {
         case NVGPU_PRIORITY_LOW:
-                tsg->timeslice_us = g->timeslice_low_priority_us;
+                timeslice_us = g->timeslice_low_priority_us;
                 break;
         case NVGPU_PRIORITY_MEDIUM:
-                tsg->timeslice_us = g->timeslice_medium_priority_us;
+                timeslice_us = g->timeslice_medium_priority_us;
                 break;
         case NVGPU_PRIORITY_HIGH:
-                tsg->timeslice_us = g->timeslice_high_priority_us;
+                timeslice_us = g->timeslice_high_priority_us;
                 break;
         default:
                 pr_err("Unsupported priority");
                 return -EINVAL;
         }
 
-        gk20a_channel_get_timescale_from_timeslice(g, tsg->timeslice_us,
-                        &tsg->timeslice_timeout, &tsg->timeslice_scale);
-
-        g->ops.fifo.update_runlist(g, tsg->runlist_id, ~0, true, true);
-
-        return 0;
+        return gk20a_tsg_set_timeslice(tsg, timeslice_us);
 }
 
 static int gk20a_tsg_get_event_data_from_id(struct tsg_gk20a *tsg,
@@ -343,6 +340,8 @@ int gk20a_tsg_set_runlist_interleave(struct tsg_gk20a *tsg, u32 level)
         struct gk20a *g = tsg->g;
         int ret;
 
+        gk20a_dbg(gpu_dbg_sched, "tsgid=%u interleave=%u", tsg->tsgid, level);
+
         switch (level) {
         case NVGPU_RUNLIST_INTERLEAVE_LEVEL_LOW:
         case NVGPU_RUNLIST_INTERLEAVE_LEVEL_MEDIUM:
@@ -364,16 +363,9 @@ int gk20a_tsg_set_timeslice(struct tsg_gk20a *tsg, u32 timeslice)
 {
         struct gk20a *g = tsg->g;
 
-        if (timeslice < g->min_timeslice_us ||
-                timeslice > g->max_timeslice_us)
-                return -EINVAL;
-
-        gk20a_channel_get_timescale_from_timeslice(g, timeslice,
-                        &tsg->timeslice_timeout, &tsg->timeslice_scale);
-
-        tsg->timeslice_us = timeslice;
+        gk20a_dbg(gpu_dbg_sched, "tsgid=%u timeslice=%u us", tsg->tsgid, timeslice);
 
-        return g->ops.fifo.update_runlist(g, tsg->runlist_id, ~0, true, true);
+        return g->ops.fifo.tsg_set_timeslice(tsg, timeslice);
 }
 
 static void release_used_tsg(struct fifo_gk20a *f, struct tsg_gk20a *tsg)
@@ -551,6 +543,8 @@ static int gk20a_tsg_ioctl_set_runlist_interleave(struct gk20a *g,
         struct gk20a_sched_ctrl *sched = &g->sched_ctrl;
         int err;
 
+        gk20a_dbg(gpu_dbg_fn | gpu_dbg_sched, "tsgid=%u", tsg->tsgid);
+
         mutex_lock(&sched->control_lock);
         if (sched->control_locked) {
                 err = -EPERM;
@@ -576,6 +570,8 @@ static int gk20a_tsg_ioctl_set_timeslice(struct gk20a *g,
         struct gk20a_sched_ctrl *sched = &g->sched_ctrl;
         int err;
 
+        gk20a_dbg(gpu_dbg_fn | gpu_dbg_sched, "tsgid=%u", tsg->tsgid);
+
         mutex_lock(&sched->control_lock);
         if (sched->control_locked) {
                 err = -EPERM;
@@ -728,5 +724,4 @@ void gk20a_init_tsg_ops(struct gpu_ops *gops)
 {
         gops->fifo.tsg_bind_channel = gk20a_tsg_bind_channel;
         gops->fifo.tsg_unbind_channel = gk20a_tsg_unbind_channel;
-        gops->fifo.tsg_set_timeslice = gk20a_tsg_set_timeslice;
 }
diff --git a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c
index 3ffc7103..6be6be04 100644
--- a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c
@@ -1,7 +1,7 @@
 /*
  * GM20B Fifo
  *
- * Copyright (c) 2014-2016, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -158,6 +158,7 @@ void gm20b_init_fifo(struct gpu_ops *gops)
         gops->fifo.get_num_fifos = gm20b_fifo_get_num_fifos;
         gops->fifo.get_pbdma_signature = gk20a_fifo_get_pbdma_signature;
         gops->fifo.set_runlist_interleave = gk20a_fifo_set_runlist_interleave;
+        gops->fifo.tsg_set_timeslice = gk20a_fifo_tsg_set_timeslice;
         gops->fifo.force_reset_ch = gk20a_fifo_force_reset_ch;
         gops->fifo.engine_enum_from_type = gk20a_fifo_engine_enum_from_type;
         gops->fifo.device_info_data_parse = gm20b_device_info_data_parse;
diff --git a/drivers/gpu/nvgpu/vgpu/tsg_vgpu.c b/drivers/gpu/nvgpu/vgpu/tsg_vgpu.c
index 9daf9e6d..e668d1ed 100644
--- a/drivers/gpu/nvgpu/vgpu/tsg_vgpu.c
+++ b/drivers/gpu/nvgpu/vgpu/tsg_vgpu.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -114,6 +114,8 @@ static int vgpu_tsg_set_timeslice(struct tsg_gk20a *tsg, u32 timeslice)
         err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
         err = err ? err : msg.ret;
         WARN_ON(err);
+        if (!err)
+                tsg->timeslice_us = timeslice;
 
         return err;
 }