diff options
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c | 22 |
1 files changed, 12 insertions, 10 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c b/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c index 3ba5a2d2..1d764ad2 100644 --- a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c | |||
@@ -38,6 +38,8 @@ void gk20a_enable_priv_ring(struct gk20a *g) | |||
38 | if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) | 38 | if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) |
39 | return; | 39 | return; |
40 | 40 | ||
41 | nvgpu_log(g, gpu_dbg_info, "enabling priv ring"); | ||
42 | |||
41 | if (g->ops.clock_gating.slcg_priring_load_gating_prod) | 43 | if (g->ops.clock_gating.slcg_priring_load_gating_prod) |
42 | g->ops.clock_gating.slcg_priring_load_gating_prod(g, | 44 | g->ops.clock_gating.slcg_priring_load_gating_prod(g, |
43 | g->slcg_enabled); | 45 | g->slcg_enabled); |
@@ -47,9 +49,7 @@ void gk20a_enable_priv_ring(struct gk20a *g) | |||
47 | 49 | ||
48 | gk20a_writel(g, pri_ringstation_sys_decode_config_r(), | 50 | gk20a_writel(g, pri_ringstation_sys_decode_config_r(), |
49 | 0x2); | 51 | 0x2); |
50 | |||
51 | gk20a_readl(g, pri_ringstation_sys_decode_config_r()); | 52 | gk20a_readl(g, pri_ringstation_sys_decode_config_r()); |
52 | |||
53 | } | 53 | } |
54 | 54 | ||
55 | void gk20a_priv_ring_isr(struct gk20a *g) | 55 | void gk20a_priv_ring_isr(struct gk20a *g) |
@@ -86,18 +86,20 @@ void gk20a_priv_ring_isr(struct gk20a *g) | |||
86 | gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_code_r() + gpc * gpc_stride)); | 86 | gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_code_r() + gpc * gpc_stride)); |
87 | } | 87 | } |
88 | } | 88 | } |
89 | 89 | /* clear interrupt */ | |
90 | cmd = gk20a_readl(g, pri_ringmaster_command_r()); | 90 | cmd = gk20a_readl(g, pri_ringmaster_command_r()); |
91 | cmd = set_field(cmd, pri_ringmaster_command_cmd_m(), | 91 | cmd = set_field(cmd, pri_ringmaster_command_cmd_m(), |
92 | pri_ringmaster_command_cmd_ack_interrupt_f()); | 92 | pri_ringmaster_command_cmd_ack_interrupt_f()); |
93 | gk20a_writel(g, pri_ringmaster_command_r(), cmd); | 93 | gk20a_writel(g, pri_ringmaster_command_r(), cmd); |
94 | 94 | /* poll for clear interrupt done */ | |
95 | do { | 95 | cmd = pri_ringmaster_command_cmd_v( |
96 | gk20a_readl(g, pri_ringmaster_command_r())); | ||
97 | while (cmd != pri_ringmaster_command_cmd_no_cmd_v() && retry) { | ||
98 | nvgpu_udelay(20); | ||
99 | retry--; | ||
96 | cmd = pri_ringmaster_command_cmd_v( | 100 | cmd = pri_ringmaster_command_cmd_v( |
97 | gk20a_readl(g, pri_ringmaster_command_r())); | 101 | gk20a_readl(g, pri_ringmaster_command_r())); |
98 | nvgpu_usleep_range(20, 40); | 102 | } |
99 | } while (cmd != pri_ringmaster_command_cmd_no_cmd_v() && --retry); | 103 | if (retry == 0 && cmd != pri_ringmaster_command_cmd_no_cmd_v()) |
100 | 104 | nvgpu_warn(g, "priv ringmaster intr ack too many retries"); | |
101 | if (retry <= 0) | ||
102 | nvgpu_warn(g, "priv ringmaster cmd ack too many retries"); | ||
103 | } | 105 | } |