12 files changed, 0 insertions, 86 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index f802cd56..1fe0cb5d 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -437,7 +437,6 @@ struct gpu_ops {
                 void (*set_preemption_buffer_va)(struct gk20a *g,
                                         struct nvgpu_mem *mem, u64 gpu_va);
                 void (*load_tpc_mask)(struct gk20a *g);
-                int (*inval_icache)(struct gk20a *g, struct channel_gk20a *ch);
                 int (*trigger_suspend)(struct gk20a *g);
                 int (*wait_for_pause)(struct gk20a *g, struct nvgpu_warpstate *w_state);
                 int (*resume_from_pause)(struct gk20a *g);
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index fbba02ca..90643971 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -8549,51 +8549,6 @@ clean_up:
         return err;
 }
 
-int gr_gk20a_inval_icache(struct gk20a *g, struct channel_gk20a *ch)
-{
-        int err = 0;
-        u32     cache_ctrl, regval;
-        struct nvgpu_dbg_reg_op ops;
-
-        ops.op     = REGOP(READ_32);
-        ops.type   = REGOP(TYPE_GR_CTX);
-        ops.status = REGOP(STATUS_SUCCESS);
-        ops.value_hi      = 0;
-        ops.and_n_mask_lo = 0;
-        ops.and_n_mask_hi = 0;
-        ops.offset       = gr_pri_gpc0_gcc_dbg_r();
-
-        err = gr_gk20a_exec_ctx_ops(ch, &ops, 1, 0, 1);
-        if (err) {
-                nvgpu_err(g, "Failed to read register");
-                return err;
-        }
-
-        regval = ops.value_lo;
-
-        ops.op = REGOP(WRITE_32);
-        ops.value_lo = set_field(regval, gr_pri_gpcs_gcc_dbg_invalidate_m(), 1);
-        err = gr_gk20a_exec_ctx_ops(ch, &ops, 1, 1, 0);
-        if (err) {
-                nvgpu_err(g, "Failed to write register");
-                return err;
-        }
-
-        ops.op     = REGOP(READ_32);
-        ops.offset = gr_pri_gpc0_tpc0_sm_cache_control_r();
-        err = gr_gk20a_exec_ctx_ops(ch, &ops, 1, 0, 1);
-        if (err) {
-                nvgpu_err(g, "Failed to read register");
-                return err;
-        }
-
-        cache_ctrl = gk20a_readl(g, gr_pri_gpc0_tpc0_sm_cache_control_r());
-        cache_ctrl = set_field(cache_ctrl, gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m(), 1);
-        gk20a_writel(g, gr_pri_gpc0_tpc0_sm_cache_control_r(), cache_ctrl);
-
-        return 0;
-}
-
 int gr_gk20a_trigger_suspend(struct gk20a *g)
 {
         int err = 0;
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
index 9c9a3caa..a60f6f12 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
@@ -775,7 +775,6 @@ int gr_gk20a_resume_contexts(struct gk20a *g,
                               int *ctx_resident_ch_fd);
 void gk20a_gr_enable_gpc_exceptions(struct gk20a *g);
 void gk20a_gr_enable_exceptions(struct gk20a *g);
-int gr_gk20a_inval_icache(struct gk20a *g, struct channel_gk20a *ch);
 int gr_gk20a_trigger_suspend(struct gk20a *g);
 int gr_gk20a_wait_for_pause(struct gk20a *g, struct nvgpu_warpstate *w_state);
 int gr_gk20a_resume_from_pause(struct gk20a *g);
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
index 3b164f9c..838f0f1b 100644
--- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
@@ -292,7 +292,6 @@ static const struct gpu_ops gm20b_ops = {
                 .write_zcull_ptr = gr_gk20a_write_zcull_ptr,
                 .write_pm_ptr = gr_gk20a_write_pm_ptr,
                 .load_tpc_mask = gr_gm20b_load_tpc_mask,
-                .inval_icache = gr_gk20a_inval_icache,
                 .trigger_suspend = gr_gk20a_trigger_suspend,
                 .wait_for_pause = gr_gk20a_wait_for_pause,
                 .resume_from_pause = gr_gk20a_resume_from_pause,
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c
index 1c5e1800..52fcc9d3 100644
--- a/drivers/gpu/nvgpu/gp106/hal_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c
@@ -352,7 +352,6 @@ static const struct gpu_ops gp106_ops = {
                 .write_zcull_ptr = gr_gk20a_write_zcull_ptr,
                 .write_pm_ptr = gr_gk20a_write_pm_ptr,
                 .load_tpc_mask = gr_gm20b_load_tpc_mask,
-                .inval_icache = gr_gk20a_inval_icache,
                 .trigger_suspend = gr_gk20a_trigger_suspend,
                 .wait_for_pause = gr_gk20a_wait_for_pause,
                 .resume_from_pause = gr_gk20a_resume_from_pause,
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
index b9d8c81a..7df17ed7 100644
--- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
@@ -311,7 +311,6 @@ static const struct gpu_ops gp10b_ops = {
                 .write_zcull_ptr = gr_gk20a_write_zcull_ptr,
                 .write_pm_ptr = gr_gk20a_write_pm_ptr,
                 .load_tpc_mask = gr_gm20b_load_tpc_mask,
-                .inval_icache = gr_gk20a_inval_icache,
                 .trigger_suspend = gr_gk20a_trigger_suspend,
                 .wait_for_pause = gr_gk20a_wait_for_pause,
                 .resume_from_pause = gr_gk20a_resume_from_pause,
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c
index 6904313b..8565d5fc 100644
--- a/drivers/gpu/nvgpu/gv100/hal_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c
@@ -389,7 +389,6 @@ static const struct gpu_ops gv100_ops = {
                 .write_zcull_ptr = gr_gv11b_write_zcull_ptr,
                 .write_pm_ptr = gr_gv11b_write_pm_ptr,
                 .load_tpc_mask = gr_gv11b_load_tpc_mask,
-                .inval_icache = gr_gk20a_inval_icache,
                 .trigger_suspend = gv11b_gr_sm_trigger_suspend,
                 .wait_for_pause = gr_gk20a_wait_for_pause,
                 .resume_from_pause = gv11b_gr_resume_from_pause,
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
index 3772649e..baafa801 100644
--- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
@@ -344,7 +344,6 @@ static const struct gpu_ops gv11b_ops = {
                 .write_zcull_ptr = gr_gv11b_write_zcull_ptr,
                 .write_pm_ptr = gr_gv11b_write_pm_ptr,
                 .load_tpc_mask = gr_gv11b_load_tpc_mask,
-                .inval_icache = gr_gk20a_inval_icache,
                 .trigger_suspend = gv11b_gr_sm_trigger_suspend,
                 .wait_for_pause = gr_gk20a_wait_for_pause,
                 .resume_from_pause = gv11b_gr_resume_from_pause,
diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c b/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c
index 8130b7d0..fc1f7011 100644
--- a/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c
+++ b/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c
@@ -578,27 +578,6 @@ static int nvgpu_gpu_ioctl_l2_fb_ops(struct gk20a *g,
         return err;
 }
 
-/* Invalidate i-cache for kepler & maxwell */
-static int nvgpu_gpu_ioctl_inval_icache(
-                struct gk20a *g,
-                struct nvgpu_gpu_inval_icache_args *args)
-{
-        struct channel_gk20a *ch;
-        int err;
-
-        ch = gk20a_get_channel_from_file(args->channel_fd);
-        if (!ch)
-                return -EINVAL;
-
-        /* Take the global lock, since we'll be doing global regops */
-        nvgpu_mutex_acquire(&g->dbg_sessions_lock);
-        err = g->ops.gr.inval_icache(g, ch);
-        nvgpu_mutex_release(&g->dbg_sessions_lock);
-
-        gk20a_channel_put(ch);
-        return err;
-}
-
 static int nvgpu_gpu_ioctl_set_mmu_debug_mode(
                 struct gk20a *g,
                 struct nvgpu_gpu_mmu_debug_mode_args *args)
@@ -1824,10 +1803,6 @@ long gk20a_ctrl_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg
                 err = nvgpu_gpu_ioctl_l2_fb_ops(g,
                            (struct nvgpu_gpu_l2_fb_args *)buf);
                 break;
-        case NVGPU_GPU_IOCTL_INVAL_ICACHE:
-                err = gr_gk20a_elpg_protected_call(g,
-                                nvgpu_gpu_ioctl_inval_icache(g, (struct nvgpu_gpu_inval_icache_args *)buf));
-                break;
 
         case NVGPU_GPU_IOCTL_SET_MMUDEBUG_MODE:
                 err =  nvgpu_gpu_ioctl_set_mmu_debug_mode(g,
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
index a4ad64a8..b046ba6c 100644
--- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
+++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
@@ -185,7 +185,6 @@ static const struct gpu_ops vgpu_gp10b_ops = {
                 .write_zcull_ptr = gr_gk20a_write_zcull_ptr,
                 .write_pm_ptr = gr_gk20a_write_pm_ptr,
                 .load_tpc_mask = gr_gm20b_load_tpc_mask,
-                .inval_icache = gr_gk20a_inval_icache,
                 .trigger_suspend = gr_gk20a_trigger_suspend,
                 .wait_for_pause = gr_gk20a_wait_for_pause,
                 .resume_from_pause = gr_gk20a_resume_from_pause,
diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
index a02c47f2..f9d09ebd 100644
--- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
+++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
@@ -203,7 +203,6 @@ static const struct gpu_ops vgpu_gv11b_ops = {
                 .write_zcull_ptr = gr_gv11b_write_zcull_ptr,
                 .write_pm_ptr = gr_gv11b_write_pm_ptr,
                 .load_tpc_mask = gr_gv11b_load_tpc_mask,
-                .inval_icache = gr_gk20a_inval_icache,
                 .trigger_suspend = gv11b_gr_sm_trigger_suspend,
                 .wait_for_pause = gr_gk20a_wait_for_pause,
                 .resume_from_pause = gv11b_gr_resume_from_pause,
diff --git a/include/uapi/linux/nvgpu.h b/include/uapi/linux/nvgpu.h
index 0733a7b2..8d884872 100644
--- a/include/uapi/linux/nvgpu.h
+++ b/include/uapi/linux/nvgpu.h
@@ -404,11 +404,6 @@ struct nvgpu_gpu_l2_fb_args {
         __u32 reserved;
 } __packed;
 
-struct nvgpu_gpu_inval_icache_args {
-        int channel_fd;
-        __u32 reserved;
-} __packed;
-
 struct nvgpu_gpu_mmu_debug_mode_args {
         __u32 state;
         __u32 reserved;
@@ -922,8 +917,6 @@ struct nvgpu_gpu_read_single_sm_error_state_args {
         _IOWR(NVGPU_GPU_IOCTL_MAGIC, 11, struct nvgpu_gpu_open_channel_args)
 #define NVGPU_GPU_IOCTL_FLUSH_L2 \
         _IOWR(NVGPU_GPU_IOCTL_MAGIC, 12, struct nvgpu_gpu_l2_fb_args)
-#define NVGPU_GPU_IOCTL_INVAL_ICACHE \
-        _IOWR(NVGPU_GPU_IOCTL_MAGIC, 13, struct nvgpu_gpu_inval_icache_args)
 #define NVGPU_GPU_IOCTL_SET_MMUDEBUG_MODE \
         _IOWR(NVGPU_GPU_IOCTL_MAGIC, 14, struct nvgpu_gpu_mmu_debug_mode_args)
 #define NVGPU_GPU_IOCTL_SET_SM_DEBUG_MODE \