8 files changed, 227 insertions, 8 deletions

diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile
index bbc1118d..1ca21fb5 100644
--- a/drivers/gpu/nvgpu/Makefile
+++ b/drivers/gpu/nvgpu/Makefile
@@ -22,6 +22,8 @@ nvgpu-y += \
         $(nvgpu-t19x)/gv100/mm_gv100.o \
         $(nvgpu-t19x)/gv100/gr_ctx_gv100.o \
         $(nvgpu-t19x)/gv100/fb_gv100.o \
+        $(nvgpu-t19x)/gv100/bios_gv100.o \
+        $(nvgpu-t19x)/gv100/fifo_gv100.o \
         $(nvgpu-t19x)/gv100/hal_gv100.o
 
 nvgpu-$(CONFIG_TEGRA_GK20A) += $(nvgpu-t19x)/gv11b/platform_gv11b_tegra.o
diff --git a/drivers/gpu/nvgpu/gv100/bios_gv100.c b/drivers/gpu/nvgpu/gv100/bios_gv100.c
new file mode 100644
index 00000000..9ca05a11
--- /dev/null
+++ b/drivers/gpu/nvgpu/gv100/bios_gv100.c
@@ -0,0 +1,108 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/bios.h>
+#include <nvgpu/nvgpu_common.h>
+#include <nvgpu/timers.h>
+
+#include "gk20a/gk20a.h"
+#include "gp106/bios_gp106.h"
+#include "bios_gv100.h"
+
+#include <nvgpu/hw/gv100/hw_pwr_gv100.h>
+#include <nvgpu/hw/gv100/hw_bus_gv100.h>
+
+#define PMU_BOOT_TIMEOUT_DEFAULT        100 /* usec */
+#define PMU_BOOT_TIMEOUT_MAX            2000000 /* usec */
+
+#define SCRATCH_PREOS_PROGRESS  6
+#define PREOS_PROGRESS_MASK(r)          ((r >> 12) & 0xf)
+#define PREOS_PROGRESS_NOT_STARTED      0
+#define PREOS_PROGRESS_STARTED          1
+#define PREOS_PROGRESS_EXIT             2
+#define PREOS_PROGRESS_EXIT_SECUREMODE  3
+#define PREOS_PROGRESS_ABORTED          6
+
+#define SCRATCH_PMU_EXIT_AND_HALT       1
+#define PMU_EXIT_AND_HALT_SET(r, v)     ((r & ~0x200UL) | v)
+#define PMU_EXIT_AND_HALT_YES           (0x1UL << 9)
+
+#define SCRATCH_PRE_OS_RELOAD           1
+#define PRE_OS_RELOAD_SET(r, v)         ((r & ~0x100UL) | v)
+#define PRE_OS_RELOAD_YES               (0x1UL << 8)
+
+
+void gv100_bios_preos_reload_check(struct gk20a *g)
+{
+        u32 progress = gk20a_readl(g,
+                                bus_sw_scratch_r(SCRATCH_PREOS_PROGRESS));
+
+        if (PREOS_PROGRESS_MASK(progress) != PREOS_PROGRESS_NOT_STARTED) {
+                u32 reload = gk20a_readl(g,
+                                bus_sw_scratch_r(SCRATCH_PRE_OS_RELOAD));
+
+                gk20a_writel(g, bus_sw_scratch_r(SCRATCH_PRE_OS_RELOAD),
+                        PRE_OS_RELOAD_SET(reload, PRE_OS_RELOAD_YES));
+        }
+}
+
+int gv100_bios_preos_wait_for_halt(struct gk20a *g)
+{
+        int err = -EINVAL;
+        u32 progress;
+        u32 tmp;
+        int preos_completed;
+        struct nvgpu_timeout timeout;
+
+        nvgpu_udelay(PMU_BOOT_TIMEOUT_DEFAULT);
+
+        /* Check the progress */
+        progress = gk20a_readl(g, bus_sw_scratch_r(SCRATCH_PREOS_PROGRESS));
+
+        if (PREOS_PROGRESS_MASK(progress) == PREOS_PROGRESS_STARTED) {
+                err = 0;
+
+                /* Complete the handshake */
+                tmp = gk20a_readl(g,
+                        bus_sw_scratch_r(SCRATCH_PMU_EXIT_AND_HALT));
+
+                gk20a_writel(g, bus_sw_scratch_r(SCRATCH_PMU_EXIT_AND_HALT),
+                        PMU_EXIT_AND_HALT_SET(tmp, PMU_EXIT_AND_HALT_YES));
+
+                nvgpu_timeout_init(g, &timeout,
+                           PMU_BOOT_TIMEOUT_MAX /
+                                PMU_BOOT_TIMEOUT_DEFAULT,
+                           NVGPU_TIMER_RETRY_TIMER);
+
+                do {
+                        progress = gk20a_readl(g,
+                                bus_sw_scratch_r(SCRATCH_PREOS_PROGRESS));
+                        preos_completed = pwr_falcon_cpuctl_halt_intr_v(
+                                gk20a_readl(g, pwr_falcon_cpuctl_r())) &&
+                                        (PREOS_PROGRESS_MASK(progress) ==
+                                        PREOS_PROGRESS_EXIT);
+                        nvgpu_udelay(PMU_BOOT_TIMEOUT_DEFAULT);
+                } while (!preos_completed && !nvgpu_timeout_expired(&timeout));
+        }
+
+        return err;
+}
diff --git a/drivers/gpu/nvgpu/gv100/bios_gv100.h b/drivers/gpu/nvgpu/gv100/bios_gv100.h
new file mode 100644
index 00000000..c6433f57
--- /dev/null
+++ b/drivers/gpu/nvgpu/gv100/bios_gv100.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_BIOS_GV100_H
+#define NVGPU_BIOS_GV100_H
+
+struct gk20a;
+
+void gv100_bios_preos_reload_check(struct gk20a *g);
+int gv100_bios_preos_wait_for_halt(struct gk20a *g);
+
+#endif
diff --git a/drivers/gpu/nvgpu/gv100/fifo_gv100.c b/drivers/gpu/nvgpu/gv100/fifo_gv100.c
new file mode 100644
index 00000000..e19301e6
--- /dev/null
+++ b/drivers/gpu/nvgpu/gv100/fifo_gv100.c
@@ -0,0 +1,32 @@
+/*
+ * GV100 fifo
+ *
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include "fifo_gv100.h"
+
+#include <nvgpu/hw/gv100/hw_ccsr_gv100.h>
+
+u32 gv100_fifo_get_num_fifos(struct gk20a *g)
+{
+        return ccsr_channel__size_1_v();
+}
diff --git a/drivers/gpu/nvgpu/gv100/fifo_gv100.h b/drivers/gpu/nvgpu/gv100/fifo_gv100.h
new file mode 100644
index 00000000..3ffb417c
--- /dev/null
+++ b/drivers/gpu/nvgpu/gv100/fifo_gv100.h
@@ -0,0 +1,32 @@
+/*
+ * GV100 Fifo
+ *
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef FIFO_GV100_H
+#define FIFO_GV100_H
+
+#include <nvgpu/types.h>
+struct gk20a;
+
+u32 gv100_fifo_get_num_fifos(struct gk20a *g);
+#endif
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c
index 028c9d84..7f7ab785 100644
--- a/drivers/gpu/nvgpu/gv100/hal_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c
@@ -61,6 +61,7 @@
 #include "gp106/acr_gp106.h"
 #include "gp106/sec2_gp106.h"
 #include "gp106/bios_gp106.h"
+#include "gv100/bios_gv100.h"
 #include "gp106/therm_gp106.h"
 #include "gp106/xve_gp106.h"
 #include "gp106/clk_gp106.h"
@@ -85,6 +86,10 @@
 #include "gv11b/mm_gv11b.h"
 #include "gv11b/pmu_gv11b.h"
 #include "gv11b/fb_gv11b.h"
+#include "gv100/mm_gv100.h"
+#include "gv11b/pmu_gv11b.h"
+#include "gv100/fb_gv100.h"
+#include "gv100/fifo_gv100.h"
 #include "gv11b/fifo_gv11b.h"
 #include "gv11b/gv11b_gating_reglist.h"
 #include "gv11b/regops_gv11b.h"
@@ -208,6 +213,11 @@ int gv100_init_gpu_characteristics(struct gk20a *g)
 
 
 static const struct gpu_ops gv100_ops = {
+        .bios = {
+                .init = gp106_bios_init,
+                .preos_wait_for_halt = gv100_bios_preos_wait_for_halt,
+                .preos_reload_check = gv100_bios_preos_reload_check,
+        },
         .ltc = {
                 .determine_L2_size_bytes = gp10b_determine_L2_size_bytes,
                 .set_zbc_s_entry = gv11b_ltc_set_zbc_stencil_entry,
@@ -218,7 +228,7 @@ static const struct gpu_ops gv100_ops = {
                 .init_comptags = gp10b_ltc_init_comptags,
                 .cbc_ctrl = gm20b_ltc_cbc_ctrl,
                 .isr = gv11b_ltc_isr,
-                .cbc_fix_config = gv11b_ltc_cbc_fix_config,
+                .cbc_fix_config = NULL,
                 .flush = gm20b_flush_ltc,
                 .set_enabled = gp10b_ltc_set_enabled,
         },
@@ -374,8 +384,7 @@ static const struct gpu_ops gv100_ops = {
         .fb = {
                 .reset = gv100_fb_reset,
                 .init_hw = gk20a_fb_init_hw,
-                .init_fs_state = gv11b_fb_init_fs_state,
-                .init_cbc = gv11b_fb_init_cbc,
+                .init_fs_state = NULL,
                 .set_mmu_page_size = gm20b_fb_set_mmu_page_size,
                 .set_use_full_comp_tag_line =
                         gm20b_fb_set_use_full_comp_tag_line,
@@ -417,7 +426,7 @@ static const struct gpu_ops gv100_ops = {
                 .trigger_mmu_fault = NULL,
                 .get_mmu_fault_info = NULL,
                 .wait_engine_idle = gk20a_fifo_wait_engine_idle,
-                .get_num_fifos = gv11b_fifo_get_num_fifos,
+                .get_num_fifos = gv100_fifo_get_num_fifos,
                 .get_pbdma_signature = gp10b_fifo_get_pbdma_signature,
                 .set_runlist_interleave = gk20a_fifo_set_runlist_interleave,
                 .tsg_set_timeslice = gk20a_fifo_tsg_set_timeslice,
@@ -633,7 +642,6 @@ static const struct gpu_ops gv100_ops = {
         },
         .chip_init_gpu_characteristics = gv100_init_gpu_characteristics,
         .get_litter_value = gv100_get_litter_value,
-        .bios_init = gp106_bios_init,
 };
 
 int gv100_init_hal(struct gk20a *g)
@@ -641,6 +649,7 @@ int gv100_init_hal(struct gk20a *g)
         struct gpu_ops *gops = &g->ops;
         struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics;
 
+        gops->bios = gv100_ops.bios;
         gops->ltc = gv100_ops.ltc;
         gops->ce2 = gv100_ops.ce2;
         gops->gr = gv100_ops.gr;
@@ -674,7 +683,6 @@ int gv100_init_hal(struct gk20a *g)
         gops->chip_init_gpu_characteristics =
                 gv100_ops.chip_init_gpu_characteristics;
         gops->get_litter_value = gv100_ops.get_litter_value;
-        gops->bios_init = gv100_ops.bios_init;
 
         __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true);
         __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
@@ -689,6 +697,8 @@ int gv100_init_hal(struct gk20a *g)
         gv11b_init_uncompressed_kind_map();
         gv11b_init_kind_attr();
 
+        g->bootstrap_owner = LSF_FALCON_ID_SEC2;
+
         g->name = "gv10x";
 
         c->twod_class = FERMI_TWOD_A;
diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c
index 6df29cb0..e452462e 100644
--- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c
@@ -118,7 +118,7 @@ static void gv11b_mm_mmu_hw_fault_buf_init(struct gk20a *g,
         fb_size = (g->ops.fifo.get_num_fifos(g) + 1) *
                                  gmmu_fault_buf_size_v();
 
-        err = nvgpu_dma_alloc_map_sys(vm, fb_size,
+        err = nvgpu_dma_alloc_map(vm, fb_size,
                         &g->mm.hw_fault_buf[FAULT_TYPE_OTHER_AND_NONREPLAY]);
         if (err) {
                 nvgpu_err(g,
@@ -131,7 +131,7 @@ static void gv11b_mm_mmu_hw_fault_buf_init(struct gk20a *g,
                          HW_FAULT_BUF_STATUS_ALLOC_TRUE;
         *hub_intr_types |= HUB_INTR_TYPE_NONREPLAY;
 
-        err = nvgpu_dma_alloc_map_sys(vm, fb_size,
+        err = nvgpu_dma_alloc_map(vm, fb_size,
                         &g->mm.hw_fault_buf[FAULT_TYPE_REPLAY]);
         if (err) {
                 nvgpu_err(g,
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_bus_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_bus_gv100.h
index bc4f7f28..2c89ccd6 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_bus_gv100.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_bus_gv100.h
@@ -56,6 +56,10 @@
 #ifndef _hw_bus_gv100_h_
 #define _hw_bus_gv100_h_
 
+static inline u32 bus_sw_scratch_r(u32 i)
+{
+        return 0x00001580 + i*4;
+}
 static inline u32 bus_bar0_window_r(void)
 {
         return 0x00001700;