diff options
-rw-r--r-- | drivers/gpu/nvgpu/Makefile.nvgpu | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/falcon/falcon.c | 51 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/falcon.h | 190 |
4 files changed, 250 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/Makefile.nvgpu b/drivers/gpu/nvgpu/Makefile.nvgpu index 6bac840f..5400b10d 100644 --- a/drivers/gpu/nvgpu/Makefile.nvgpu +++ b/drivers/gpu/nvgpu/Makefile.nvgpu | |||
@@ -47,6 +47,7 @@ nvgpu-y := \ | |||
47 | common/as.o \ | 47 | common/as.o \ |
48 | common/rbtree.o \ | 48 | common/rbtree.o \ |
49 | common/vbios/bios.o \ | 49 | common/vbios/bios.o \ |
50 | common/falcon/falcon.o \ | ||
50 | gk20a/gk20a.o \ | 51 | gk20a/gk20a.o \ |
51 | gk20a/bus_gk20a.o \ | 52 | gk20a/bus_gk20a.o \ |
52 | gk20a/pramin_gk20a.o \ | 53 | gk20a/pramin_gk20a.o \ |
diff --git a/drivers/gpu/nvgpu/common/falcon/falcon.c b/drivers/gpu/nvgpu/common/falcon/falcon.c new file mode 100644 index 00000000..ac1b390f --- /dev/null +++ b/drivers/gpu/nvgpu/common/falcon/falcon.c | |||
@@ -0,0 +1,51 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | */ | ||
13 | #include <nvgpu/lock.h> | ||
14 | #include <nvgpu/timers.h> | ||
15 | #include <nvgpu/falcon.h> | ||
16 | |||
17 | #include "gk20a/gk20a.h" | ||
18 | |||
19 | void nvgpu_flcn_sw_init(struct gk20a *g, u32 flcn_id) | ||
20 | { | ||
21 | struct nvgpu_falcon *flcn = NULL; | ||
22 | struct gpu_ops *gops = &g->ops; | ||
23 | |||
24 | switch (flcn_id) { | ||
25 | case FALCON_ID_PMU: | ||
26 | flcn = &g->pmu_flcn; | ||
27 | flcn->flcn_id = flcn_id; | ||
28 | break; | ||
29 | case FALCON_ID_SEC2: | ||
30 | flcn = &g->sec2_flcn; | ||
31 | flcn->flcn_id = flcn_id; | ||
32 | break; | ||
33 | case FALCON_ID_FECS: | ||
34 | flcn = &g->fecs_flcn; | ||
35 | flcn->flcn_id = flcn_id; | ||
36 | break; | ||
37 | case FALCON_ID_GPCCS: | ||
38 | flcn = &g->gpccs_flcn; | ||
39 | flcn->flcn_id = flcn_id; | ||
40 | break; | ||
41 | default: | ||
42 | nvgpu_err(g, "Invalid/Unsupported falcon ID %x", flcn->flcn_id); | ||
43 | break; | ||
44 | }; | ||
45 | |||
46 | /* call to HAL method to assign flcn base & ops to selected falcon */ | ||
47 | if (flcn) { | ||
48 | flcn->g = g; | ||
49 | gops->falcon.falcon_hal_sw_init(flcn); | ||
50 | } | ||
51 | } | ||
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 71ff8d3e..74e2c688 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -46,6 +46,7 @@ struct dbg_profiler_object_data; | |||
46 | #include <nvgpu/pramin.h> | 46 | #include <nvgpu/pramin.h> |
47 | #include <nvgpu/acr/nvgpu_acr.h> | 47 | #include <nvgpu/acr/nvgpu_acr.h> |
48 | #include <nvgpu/kref.h> | 48 | #include <nvgpu/kref.h> |
49 | #include <nvgpu/falcon.h> | ||
49 | 50 | ||
50 | #include "clk_gk20a.h" | 51 | #include "clk_gk20a.h" |
51 | #include "ce2_gk20a.h" | 52 | #include "ce2_gk20a.h" |
@@ -869,6 +870,9 @@ struct gpu_ops { | |||
869 | void (*enable_shadow_rom)(struct gk20a *g); | 870 | void (*enable_shadow_rom)(struct gk20a *g); |
870 | void (*disable_shadow_rom)(struct gk20a *g); | 871 | void (*disable_shadow_rom)(struct gk20a *g); |
871 | } xve; | 872 | } xve; |
873 | struct { | ||
874 | void (*falcon_hal_sw_init)(struct nvgpu_falcon *flcn); | ||
875 | } falcon; | ||
872 | }; | 876 | }; |
873 | 877 | ||
874 | struct nvgpu_bios_ucode { | 878 | struct nvgpu_bios_ucode { |
@@ -944,6 +948,10 @@ struct gk20a { | |||
944 | 948 | ||
945 | struct rw_semaphore busy_lock; | 949 | struct rw_semaphore busy_lock; |
946 | 950 | ||
951 | struct nvgpu_falcon pmu_flcn; | ||
952 | struct nvgpu_falcon sec2_flcn; | ||
953 | struct nvgpu_falcon fecs_flcn; | ||
954 | struct nvgpu_falcon gpccs_flcn; | ||
947 | struct clk_gk20a clk; | 955 | struct clk_gk20a clk; |
948 | struct fifo_gk20a fifo; | 956 | struct fifo_gk20a fifo; |
949 | struct gr_gk20a gr; | 957 | struct gr_gk20a gr; |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/falcon.h b/drivers/gpu/nvgpu/include/nvgpu/falcon.h new file mode 100644 index 00000000..17b811dd --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/falcon.h | |||
@@ -0,0 +1,190 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | */ | ||
13 | |||
14 | #ifndef __FALCON_H__ | ||
15 | #define __FALCON_H__ | ||
16 | |||
17 | /* | ||
18 | * Falcon Id Defines | ||
19 | */ | ||
20 | #define FALCON_ID_PMU (0) | ||
21 | #define FALCON_ID_FECS (2) | ||
22 | #define FALCON_ID_GPCCS (3) | ||
23 | #define FALCON_ID_SEC2 (7) | ||
24 | |||
25 | /* | ||
26 | * Falcon Base address Defines | ||
27 | */ | ||
28 | #define FALCON_PWR_BASE 0x0010a000 | ||
29 | #define FALCON_SEC_BASE 0x00087000 | ||
30 | #define FALCON_FECS_BASE 0x00409000 | ||
31 | #define FALCON_GPCCS_BASE 0x0041a000 | ||
32 | |||
33 | /* Falcon Register index */ | ||
34 | #define FALCON_REG_R0 (0) | ||
35 | #define FALCON_REG_R1 (1) | ||
36 | #define FALCON_REG_R2 (2) | ||
37 | #define FALCON_REG_R3 (3) | ||
38 | #define FALCON_REG_R4 (4) | ||
39 | #define FALCON_REG_R5 (5) | ||
40 | #define FALCON_REG_R6 (6) | ||
41 | #define FALCON_REG_R7 (7) | ||
42 | #define FALCON_REG_R8 (8) | ||
43 | #define FALCON_REG_R9 (9) | ||
44 | #define FALCON_REG_R10 (10) | ||
45 | #define FALCON_REG_R11 (11) | ||
46 | #define FALCON_REG_R12 (12) | ||
47 | #define FALCON_REG_R13 (13) | ||
48 | #define FALCON_REG_R14 (14) | ||
49 | #define FALCON_REG_R15 (15) | ||
50 | #define FALCON_REG_IV0 (16) | ||
51 | #define FALCON_REG_IV1 (17) | ||
52 | #define FALCON_REG_UNDEFINED (18) | ||
53 | #define FALCON_REG_EV (19) | ||
54 | #define FALCON_REG_SP (20) | ||
55 | #define FALCON_REG_PC (21) | ||
56 | #define FALCON_REG_IMB (22) | ||
57 | #define FALCON_REG_DMB (23) | ||
58 | #define FALCON_REG_CSW (24) | ||
59 | #define FALCON_REG_CCR (25) | ||
60 | #define FALCON_REG_SEC (26) | ||
61 | #define FALCON_REG_CTX (27) | ||
62 | #define FALCON_REG_EXCI (28) | ||
63 | #define FALCON_REG_RSVD0 (29) | ||
64 | #define FALCON_REG_RSVD1 (30) | ||
65 | #define FALCON_REG_RSVD2 (31) | ||
66 | #define FALCON_REG_SIZE (32) | ||
67 | |||
68 | /* | ||
69 | * Falcon HWCFG request read types defines | ||
70 | */ | ||
71 | enum flcn_hwcfg_read { | ||
72 | FALCON_IMEM_SIZE = 0, | ||
73 | FALCON_DMEM_SIZE, | ||
74 | FALCON_CORE_REV, | ||
75 | FALCON_SECURITY_MODEL, | ||
76 | FLACON_MAILBOX_COUNT | ||
77 | }; | ||
78 | |||
79 | /* | ||
80 | * Falcon HWCFG request write types defines | ||
81 | */ | ||
82 | enum flcn_hwcfg_write { | ||
83 | FALCON_STARTCPU = 0, | ||
84 | FALCON_STARTCPU_SECURE, | ||
85 | FALCON_BOOTVEC, | ||
86 | FALCON_ITF_EN | ||
87 | }; | ||
88 | |||
89 | /* | ||
90 | * Falcon sub unit Id Defines | ||
91 | */ | ||
92 | enum flcn_unit_status { | ||
93 | IS_FALCON_IN_RESET = 0x0, | ||
94 | IS_FALCON_CPU_HALTED, | ||
95 | IS_FALCON_IDLE, | ||
96 | IS_FALCON_MEM_SURBBING_DONE | ||
97 | }; | ||
98 | |||
99 | #define FALCON_MEM_SCRUBBING_TIMEOUT_MAX 1000 | ||
100 | #define FALCON_MEM_SCRUBBING_TIMEOUT_DEFAULT 10 | ||
101 | |||
102 | enum flcn_dma_dir { | ||
103 | DMA_TO_FB = 0, | ||
104 | DMA_FROM_FB | ||
105 | }; | ||
106 | |||
107 | enum flcn_mem_type { | ||
108 | MEM_DMEM = 0, | ||
109 | MEM_IMEM | ||
110 | }; | ||
111 | |||
112 | struct nvgpu_falcon_dma_info { | ||
113 | u32 fb_base; | ||
114 | u32 fb_off; | ||
115 | u32 flcn_mem_off; | ||
116 | u32 size_in_bytes; | ||
117 | enum flcn_dma_dir dir; | ||
118 | u32 ctx_dma; | ||
119 | enum flcn_mem_type flcn_mem; | ||
120 | u32 is_wait_complete; | ||
121 | }; | ||
122 | |||
123 | struct gk20a; | ||
124 | struct nvgpu_falcon; | ||
125 | |||
126 | struct nvgpu_falcon_version_ops { | ||
127 | void (*start_cpu_secure)(struct nvgpu_falcon *flcn); | ||
128 | void (*write_dmatrfbase)(struct nvgpu_falcon *flcn, u32 addr); | ||
129 | }; | ||
130 | |||
131 | struct nvgpu_falcon_ops { | ||
132 | void (*reset)(struct nvgpu_falcon *flcn, bool enable); | ||
133 | void (*enable_irq)(struct nvgpu_falcon *flcn, bool enable); | ||
134 | void (*fbif_transcfg)(struct nvgpu_falcon *flcn); | ||
135 | u32 (*read_hwcfg)(struct nvgpu_falcon *flcn, | ||
136 | enum flcn_hwcfg_read cfg_type); | ||
137 | void (*write_hwcfg)(struct nvgpu_falcon *flcn, | ||
138 | enum flcn_hwcfg_write cfg_type, u32 cfg_data); | ||
139 | bool (*get_unit_status)(struct nvgpu_falcon *flcn, | ||
140 | enum flcn_unit_status unit_id); | ||
141 | int (*copy_from_dmem)(struct nvgpu_falcon *flcn, u32 src, u8 *dst, | ||
142 | u32 size, u8 port); | ||
143 | int (*copy_to_dmem)(struct nvgpu_falcon *flcn, u32 dst, u8 *src, | ||
144 | u32 size, u8 port); | ||
145 | int (*copy_from_imem)(struct nvgpu_falcon *flcn, u32 src, u8 *dst, | ||
146 | u32 size, u8 port); | ||
147 | int (*copy_to_imem)(struct nvgpu_falcon *flcn, u32 dst, u8 *src, | ||
148 | u32 size, u8 port); | ||
149 | int (*dma_copy)(struct nvgpu_falcon *flcn, | ||
150 | struct nvgpu_falcon_dma_info *dma_info); | ||
151 | u32 (*mailbox_read)(struct nvgpu_falcon *flcn, u32 mailbox_index); | ||
152 | void (*mailbox_write)(struct nvgpu_falcon *flcn, u32 mailbox_index, | ||
153 | u32 data); | ||
154 | void (*dump_falcon_stats)(struct nvgpu_falcon *flcn); | ||
155 | }; | ||
156 | |||
157 | struct nvgpu_falcon { | ||
158 | struct gk20a *g; | ||
159 | u32 flcn_id; | ||
160 | u32 flcn_base; | ||
161 | u32 flcn_core_rev; | ||
162 | bool isr_enabled; | ||
163 | struct nvgpu_mutex isr_mutex; | ||
164 | struct nvgpu_mutex copy_lock; | ||
165 | struct nvgpu_falcon_ops flcn_ops; | ||
166 | struct nvgpu_falcon_version_ops flcn_vops; | ||
167 | }; | ||
168 | |||
169 | int nvgpu_flcn_wait_idle(struct nvgpu_falcon *flcn); | ||
170 | int nvgpu_flcn_enable_hw(struct nvgpu_falcon *flcn, bool enable); | ||
171 | int nvgpu_flcn_reset(struct nvgpu_falcon *flcn); | ||
172 | void nvgpu_flcn_enable_irq(struct nvgpu_falcon *flcn, bool enable); | ||
173 | void nvgpu_flcn_fbif_transcfg(struct nvgpu_falcon *flcn); | ||
174 | bool nvgpu_flcn_get_unit_status(struct nvgpu_falcon *flcn, | ||
175 | enum flcn_unit_status unit_id); | ||
176 | int nvgpu_flcn_copy_from_mem(struct nvgpu_falcon *flcn, | ||
177 | enum flcn_mem_type mem_type, u32 src, u8 *dst, u32 size, u8 port); | ||
178 | int nvgpu_flcn_copy_to_mem(struct nvgpu_falcon *flcn, | ||
179 | enum flcn_mem_type mem_type, u32 dst, u8 *src, u32 size, u8 port); | ||
180 | int nvgpu_flcn_dma_copy(struct nvgpu_falcon *flcn, | ||
181 | struct nvgpu_falcon_dma_info *dma_info); | ||
182 | u32 nvgpu_flcn_mailbox_read(struct nvgpu_falcon *flcn, u32 mailbox_index); | ||
183 | void nvgpu_flcn_mailbox_write(struct nvgpu_falcon *flcn, u32 mailbox_index, | ||
184 | u32 data); | ||
185 | void nvgpu_flcn_dump_stats(struct nvgpu_falcon *flcn); | ||
186 | |||
187 | void nvgpu_flcn_sw_init(struct gk20a *g, u32 flcn_id); | ||
188 | |||
189 | |||
190 | #endif /* __FALCON_H__ */ | ||