diff options
-rw-r--r-- | drivers/gpu/nvgpu/clk/clk.c | 30 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/clk/clk_domain.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/clk/clk_freq_controller.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/clk/clk_mclk.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/perf/perf.c | 10 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/perf/vfe_var.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/pmgr/pmgrpmu.c | 20 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/therm/thrmpmu.c | 32 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/volt/volt_pmu.c | 13 |
9 files changed, 81 insertions, 36 deletions
diff --git a/drivers/gpu/nvgpu/clk/clk.c b/drivers/gpu/nvgpu/clk/clk.c index 8b36394d..c1b8d5e1 100644 --- a/drivers/gpu/nvgpu/clk/clk.c +++ b/drivers/gpu/nvgpu/clk/clk.c | |||
@@ -49,15 +49,19 @@ int clk_pmu_freq_controller_load(struct gk20a *g, bool bload) | |||
49 | { | 49 | { |
50 | struct pmu_cmd cmd; | 50 | struct pmu_cmd cmd; |
51 | struct pmu_msg msg; | 51 | struct pmu_msg msg; |
52 | struct pmu_payload payload = { {0} }; | 52 | struct pmu_payload payload; |
53 | u32 status; | 53 | u32 status; |
54 | u32 seqdesc; | 54 | u32 seqdesc; |
55 | struct nv_pmu_clk_rpc rpccall = {0}; | 55 | struct nv_pmu_clk_rpc rpccall; |
56 | struct clkrpc_pmucmdhandler_params handler = {0}; | 56 | struct clkrpc_pmucmdhandler_params handler; |
57 | struct nv_pmu_clk_load *clkload; | 57 | struct nv_pmu_clk_load *clkload; |
58 | struct clk_freq_controllers *pclk_freq_controllers; | 58 | struct clk_freq_controllers *pclk_freq_controllers; |
59 | struct ctrl_boardobjgrp_mask_e32 *load_mask; | 59 | struct ctrl_boardobjgrp_mask_e32 *load_mask; |
60 | 60 | ||
61 | memset(&payload, 0, sizeof(struct pmu_payload)); | ||
62 | memset(&rpccall, 0, sizeof(struct nv_pmu_clk_rpc)); | ||
63 | memset(&handler, 0, sizeof(struct clkrpc_pmucmdhandler_params)); | ||
64 | |||
61 | pclk_freq_controllers = &g->clk_pmu.clk_freq_controllers; | 65 | pclk_freq_controllers = &g->clk_pmu.clk_freq_controllers; |
62 | rpccall.function = NV_PMU_CLK_RPC_ID_LOAD; | 66 | rpccall.function = NV_PMU_CLK_RPC_ID_LOAD; |
63 | clkload = &rpccall.params.clk_load; | 67 | clkload = &rpccall.params.clk_load; |
@@ -120,13 +124,17 @@ u32 clk_pmu_vin_load(struct gk20a *g) | |||
120 | { | 124 | { |
121 | struct pmu_cmd cmd; | 125 | struct pmu_cmd cmd; |
122 | struct pmu_msg msg; | 126 | struct pmu_msg msg; |
123 | struct pmu_payload payload = { {0} }; | 127 | struct pmu_payload payload; |
124 | u32 status; | 128 | u32 status; |
125 | u32 seqdesc; | 129 | u32 seqdesc; |
126 | struct nv_pmu_clk_rpc rpccall = {0}; | 130 | struct nv_pmu_clk_rpc rpccall; |
127 | struct clkrpc_pmucmdhandler_params handler = {0}; | 131 | struct clkrpc_pmucmdhandler_params handler; |
128 | struct nv_pmu_clk_load *clkload; | 132 | struct nv_pmu_clk_load *clkload; |
129 | 133 | ||
134 | memset(&payload, 0, sizeof(struct pmu_payload)); | ||
135 | memset(&rpccall, 0, sizeof(struct nv_pmu_clk_rpc)); | ||
136 | memset(&handler, 0, sizeof(struct clkrpc_pmucmdhandler_params)); | ||
137 | |||
130 | rpccall.function = NV_PMU_CLK_RPC_ID_LOAD; | 138 | rpccall.function = NV_PMU_CLK_RPC_ID_LOAD; |
131 | clkload = &rpccall.params.clk_load; | 139 | clkload = &rpccall.params.clk_load; |
132 | clkload->feature = NV_NV_PMU_CLK_LOAD_FEATURE_VIN; | 140 | clkload->feature = NV_NV_PMU_CLK_LOAD_FEATURE_VIN; |
@@ -179,13 +187,17 @@ static u32 clk_pmu_vf_inject(struct gk20a *g, struct set_fll_clk *setfllclk) | |||
179 | { | 187 | { |
180 | struct pmu_cmd cmd; | 188 | struct pmu_cmd cmd; |
181 | struct pmu_msg msg; | 189 | struct pmu_msg msg; |
182 | struct pmu_payload payload = { {0} }; | 190 | struct pmu_payload payload; |
183 | u32 status; | 191 | u32 status; |
184 | u32 seqdesc; | 192 | u32 seqdesc; |
185 | struct nv_pmu_clk_rpc rpccall = {0}; | 193 | struct nv_pmu_clk_rpc rpccall; |
186 | struct clkrpc_pmucmdhandler_params handler = {0}; | 194 | struct clkrpc_pmucmdhandler_params handler; |
187 | struct nv_pmu_clk_vf_change_inject *vfchange; | 195 | struct nv_pmu_clk_vf_change_inject *vfchange; |
188 | 196 | ||
197 | memset(&payload, 0, sizeof(struct pmu_payload)); | ||
198 | memset(&rpccall, 0, sizeof(struct nv_pmu_clk_rpc)); | ||
199 | memset(&handler, 0, sizeof(struct clkrpc_pmucmdhandler_params)); | ||
200 | |||
189 | if ((setfllclk->gpc2clkmhz == 0) || (setfllclk->xbar2clkmhz == 0) || | 201 | if ((setfllclk->gpc2clkmhz == 0) || (setfllclk->xbar2clkmhz == 0) || |
190 | (setfllclk->sys2clkmhz == 0) || (setfllclk->voltuv == 0)) | 202 | (setfllclk->sys2clkmhz == 0) || (setfllclk->voltuv == 0)) |
191 | return -EINVAL; | 203 | return -EINVAL; |
diff --git a/drivers/gpu/nvgpu/clk/clk_domain.c b/drivers/gpu/nvgpu/clk/clk_domain.c index c784bdb4..84ce7371 100644 --- a/drivers/gpu/nvgpu/clk/clk_domain.c +++ b/drivers/gpu/nvgpu/clk/clk_domain.c | |||
@@ -31,7 +31,8 @@ static u32 devinit_get_clocks_table(struct gk20a *g, | |||
31 | static u32 clk_domain_pmudatainit_super(struct gk20a *g, struct boardobj | 31 | static u32 clk_domain_pmudatainit_super(struct gk20a *g, struct boardobj |
32 | *board_obj_ptr, struct nv_pmu_boardobj *ppmudata); | 32 | *board_obj_ptr, struct nv_pmu_boardobj *ppmudata); |
33 | 33 | ||
34 | const struct vbios_clocks_table_1x_hal_clock_entry vbiosclktbl1xhalentry[] = { | 34 | static const struct vbios_clocks_table_1x_hal_clock_entry |
35 | vbiosclktbl1xhalentry[] = { | ||
35 | { clkwhich_gpc2clk, true, }, | 36 | { clkwhich_gpc2clk, true, }, |
36 | { clkwhich_xbar2clk, true, }, | 37 | { clkwhich_xbar2clk, true, }, |
37 | { clkwhich_mclk, false, }, | 38 | { clkwhich_mclk, false, }, |
diff --git a/drivers/gpu/nvgpu/clk/clk_freq_controller.c b/drivers/gpu/nvgpu/clk/clk_freq_controller.c index 61c8b81b..632d7b35 100644 --- a/drivers/gpu/nvgpu/clk/clk_freq_controller.c +++ b/drivers/gpu/nvgpu/clk/clk_freq_controller.c | |||
@@ -144,7 +144,8 @@ static u32 clk_freq_controller_construct_pi(struct gk20a *g, | |||
144 | return status; | 144 | return status; |
145 | } | 145 | } |
146 | 146 | ||
147 | struct clk_freq_controller *clk_clk_freq_controller_construct(struct gk20a *g, | 147 | static struct clk_freq_controller *clk_clk_freq_controller_construct( |
148 | struct gk20a *g, | ||
148 | void *pargs) | 149 | void *pargs) |
149 | { | 150 | { |
150 | struct boardobj *board_obj_ptr = NULL; | 151 | struct boardobj *board_obj_ptr = NULL; |
diff --git a/drivers/gpu/nvgpu/clk/clk_mclk.c b/drivers/gpu/nvgpu/clk/clk_mclk.c index 690f8681..cf04c98c 100644 --- a/drivers/gpu/nvgpu/clk/clk_mclk.c +++ b/drivers/gpu/nvgpu/clk/clk_mclk.c | |||
@@ -2262,7 +2262,7 @@ fail_mclk_mutex: | |||
2262 | int clk_mclkseq_change_mclk_gddr5(struct gk20a *g, u16 val) | 2262 | int clk_mclkseq_change_mclk_gddr5(struct gk20a *g, u16 val) |
2263 | { | 2263 | { |
2264 | struct clk_mclk_state *mclk; | 2264 | struct clk_mclk_state *mclk; |
2265 | struct pmu_payload payload = { {0} }; | 2265 | struct pmu_payload payload; |
2266 | struct nv_pmu_seq_cmd cmd; | 2266 | struct nv_pmu_seq_cmd cmd; |
2267 | struct nv_pmu_seq_cmd_run_script *pseq_cmd; | 2267 | struct nv_pmu_seq_cmd_run_script *pseq_cmd; |
2268 | u32 seqdesc; | 2268 | u32 seqdesc; |
@@ -2277,6 +2277,8 @@ int clk_mclkseq_change_mclk_gddr5(struct gk20a *g, u16 val) | |||
2277 | 2277 | ||
2278 | gk20a_dbg_info(""); | 2278 | gk20a_dbg_info(""); |
2279 | 2279 | ||
2280 | memset(&payload, 0, sizeof(struct pmu_payload)); | ||
2281 | |||
2280 | mclk = &g->clk_pmu.clk_mclk; | 2282 | mclk = &g->clk_pmu.clk_mclk; |
2281 | 2283 | ||
2282 | nvgpu_mutex_acquire(&mclk->mclk_lock); | 2284 | nvgpu_mutex_acquire(&mclk->mclk_lock); |
diff --git a/drivers/gpu/nvgpu/perf/perf.c b/drivers/gpu/nvgpu/perf/perf.c index 871ff753..9adcadb6 100644 --- a/drivers/gpu/nvgpu/perf/perf.c +++ b/drivers/gpu/nvgpu/perf/perf.c | |||
@@ -61,11 +61,15 @@ u32 perf_pmu_vfe_load(struct gk20a *g) | |||
61 | { | 61 | { |
62 | struct pmu_cmd cmd; | 62 | struct pmu_cmd cmd; |
63 | struct pmu_msg msg; | 63 | struct pmu_msg msg; |
64 | struct pmu_payload payload = { {0} }; | 64 | struct pmu_payload payload; |
65 | u32 status; | 65 | u32 status; |
66 | u32 seqdesc; | 66 | u32 seqdesc; |
67 | struct nv_pmu_perf_rpc rpccall = {0}; | 67 | struct nv_pmu_perf_rpc rpccall; |
68 | struct perfrpc_pmucmdhandler_params handler = {0}; | 68 | struct perfrpc_pmucmdhandler_params handler; |
69 | |||
70 | memset(&payload, 0, sizeof(struct pmu_payload)); | ||
71 | memset(&rpccall, 0, sizeof(struct nv_pmu_perf_rpc)); | ||
72 | memset(&handler, 0, sizeof(struct perfrpc_pmucmdhandler_params)); | ||
69 | 73 | ||
70 | /*register call back for future VFE updates*/ | 74 | /*register call back for future VFE updates*/ |
71 | g->ops.perf.handle_pmu_perf_event = pmu_handle_perf_event; | 75 | g->ops.perf.handle_pmu_perf_event = pmu_handle_perf_event; |
diff --git a/drivers/gpu/nvgpu/perf/vfe_var.c b/drivers/gpu/nvgpu/perf/vfe_var.c index 996929c2..c1f87c25 100644 --- a/drivers/gpu/nvgpu/perf/vfe_var.c +++ b/drivers/gpu/nvgpu/perf/vfe_var.c | |||
@@ -161,7 +161,7 @@ u32 vfe_var_pmu_setup(struct gk20a *g) | |||
161 | return status; | 161 | return status; |
162 | } | 162 | } |
163 | 163 | ||
164 | u32 dev_init_get_vfield_info(struct gk20a *g, | 164 | static u32 dev_init_get_vfield_info(struct gk20a *g, |
165 | struct vfe_var_single_sensed_fuse *pvfevar) | 165 | struct vfe_var_single_sensed_fuse *pvfevar) |
166 | { | 166 | { |
167 | u8 *vfieldtableptr = NULL; | 167 | u8 *vfieldtableptr = NULL; |
diff --git a/drivers/gpu/nvgpu/pmgr/pmgrpmu.c b/drivers/gpu/nvgpu/pmgr/pmgrpmu.c index d09becd6..b30dccca 100644 --- a/drivers/gpu/nvgpu/pmgr/pmgrpmu.c +++ b/drivers/gpu/nvgpu/pmgr/pmgrpmu.c | |||
@@ -81,12 +81,16 @@ static u32 pmgr_pmu_set_object(struct gk20a *g, | |||
81 | u16 fb_size, | 81 | u16 fb_size, |
82 | void *pobj) | 82 | void *pobj) |
83 | { | 83 | { |
84 | struct pmu_cmd cmd = { {0} }; | 84 | struct pmu_cmd cmd; |
85 | struct pmu_payload payload = { {0} }; | 85 | struct pmu_payload payload; |
86 | struct nv_pmu_pmgr_cmd_set_object *pcmd; | 86 | struct nv_pmu_pmgr_cmd_set_object *pcmd; |
87 | u32 status; | 87 | u32 status; |
88 | u32 seqdesc; | 88 | u32 seqdesc; |
89 | struct pmgr_pmucmdhandler_params handlerparams = {0}; | 89 | struct pmgr_pmucmdhandler_params handlerparams; |
90 | |||
91 | memset(&payload, 0, sizeof(struct pmu_payload)); | ||
92 | memset(&cmd, 0, sizeof(struct pmu_cmd)); | ||
93 | memset(&handlerparams, 0, sizeof(struct pmgr_pmucmdhandler_params)); | ||
90 | 94 | ||
91 | cmd.hdr.unit_id = PMU_UNIT_PMGR; | 95 | cmd.hdr.unit_id = PMU_UNIT_PMGR; |
92 | cmd.hdr.size = (u32)sizeof(struct nv_pmu_pmgr_cmd_set_object) + | 96 | cmd.hdr.size = (u32)sizeof(struct nv_pmu_pmgr_cmd_set_object) + |
@@ -360,12 +364,16 @@ u32 pmgr_pmu_pwr_devices_query_blocking( | |||
360 | u32 pwr_dev_mask, | 364 | u32 pwr_dev_mask, |
361 | struct nv_pmu_pmgr_pwr_devices_query_payload *ppayload) | 365 | struct nv_pmu_pmgr_pwr_devices_query_payload *ppayload) |
362 | { | 366 | { |
363 | struct pmu_cmd cmd = { {0} }; | 367 | struct pmu_cmd cmd; |
364 | struct pmu_payload payload = { {0} }; | 368 | struct pmu_payload payload; |
365 | struct nv_pmu_pmgr_cmd_pwr_devices_query *pcmd; | 369 | struct nv_pmu_pmgr_cmd_pwr_devices_query *pcmd; |
366 | u32 status; | 370 | u32 status; |
367 | u32 seqdesc; | 371 | u32 seqdesc; |
368 | struct pmgr_pmucmdhandler_params handlerparams = {0}; | 372 | struct pmgr_pmucmdhandler_params handlerparams; |
373 | |||
374 | memset(&payload, 0, sizeof(struct pmu_payload)); | ||
375 | memset(&cmd, 0, sizeof(struct pmu_cmd)); | ||
376 | memset(&handlerparams, 0, sizeof(struct pmgr_pmucmdhandler_params)); | ||
369 | 377 | ||
370 | cmd.hdr.unit_id = PMU_UNIT_PMGR; | 378 | cmd.hdr.unit_id = PMU_UNIT_PMGR; |
371 | cmd.hdr.size = (u32)sizeof(struct nv_pmu_pmgr_cmd_pwr_devices_query) + | 379 | cmd.hdr.size = (u32)sizeof(struct nv_pmu_pmgr_cmd_pwr_devices_query) + |
diff --git a/drivers/gpu/nvgpu/therm/thrmpmu.c b/drivers/gpu/nvgpu/therm/thrmpmu.c index 3d80eff3..84e9871a 100644 --- a/drivers/gpu/nvgpu/therm/thrmpmu.c +++ b/drivers/gpu/nvgpu/therm/thrmpmu.c | |||
@@ -115,11 +115,17 @@ exit: | |||
115 | static u32 therm_set_warn_temp_limit(struct gk20a *g) | 115 | static u32 therm_set_warn_temp_limit(struct gk20a *g) |
116 | { | 116 | { |
117 | u32 seqdesc = 0; | 117 | u32 seqdesc = 0; |
118 | struct pmu_cmd cmd = { {0} }; | 118 | struct pmu_cmd cmd; |
119 | struct pmu_msg msg = { {0} }; | 119 | struct pmu_msg msg; |
120 | struct pmu_payload payload = { {0} }; | 120 | struct pmu_payload payload; |
121 | struct nv_pmu_therm_rpc rpccall = {0}; | 121 | struct nv_pmu_therm_rpc rpccall; |
122 | struct therm_pmucmdhandler_params handlerparams = {0}; | 122 | struct therm_pmucmdhandler_params handlerparams; |
123 | |||
124 | memset(&payload, 0, sizeof(struct pmu_payload)); | ||
125 | memset(&cmd, 0, sizeof(struct pmu_cmd)); | ||
126 | memset(&msg, 0, sizeof(struct pmu_msg)); | ||
127 | memset(&rpccall, 0, sizeof(struct nv_pmu_therm_rpc)); | ||
128 | memset(&handlerparams, 0, sizeof(struct therm_pmucmdhandler_params)); | ||
123 | 129 | ||
124 | rpccall.function = NV_PMU_THERM_RPC_ID_SLCT_EVENT_TEMP_TH_SET; | 130 | rpccall.function = NV_PMU_THERM_RPC_ID_SLCT_EVENT_TEMP_TH_SET; |
125 | rpccall.params.slct_event_temp_th_set.event_id = | 131 | rpccall.params.slct_event_temp_th_set.event_id = |
@@ -178,11 +184,17 @@ static u32 therm_enable_slct_notification_request(struct gk20a *g) | |||
178 | static u32 therm_send_slct_configuration_to_pmu(struct gk20a *g) | 184 | static u32 therm_send_slct_configuration_to_pmu(struct gk20a *g) |
179 | { | 185 | { |
180 | u32 seqdesc = 0; | 186 | u32 seqdesc = 0; |
181 | struct pmu_cmd cmd = { {0} }; | 187 | struct pmu_cmd cmd; |
182 | struct pmu_msg msg = { {0} }; | 188 | struct pmu_msg msg; |
183 | struct pmu_payload payload = { {0} }; | 189 | struct pmu_payload payload; |
184 | struct nv_pmu_therm_rpc rpccall = {0}; | 190 | struct nv_pmu_therm_rpc rpccall; |
185 | struct therm_pmucmdhandler_params handlerparams = {0}; | 191 | struct therm_pmucmdhandler_params handlerparams; |
192 | |||
193 | memset(&payload, 0, sizeof(struct pmu_payload)); | ||
194 | memset(&cmd, 0, sizeof(struct pmu_cmd)); | ||
195 | memset(&msg, 0, sizeof(struct pmu_msg)); | ||
196 | memset(&rpccall, 0, sizeof(struct nv_pmu_therm_rpc)); | ||
197 | memset(&handlerparams, 0, sizeof(struct therm_pmucmdhandler_params)); | ||
186 | 198 | ||
187 | rpccall.function = NV_PMU_THERM_RPC_ID_SLCT; | 199 | rpccall.function = NV_PMU_THERM_RPC_ID_SLCT; |
188 | rpccall.params.slct.mask_enabled = | 200 | rpccall.params.slct.mask_enabled = |
diff --git a/drivers/gpu/nvgpu/volt/volt_pmu.c b/drivers/gpu/nvgpu/volt/volt_pmu.c index dd2a0a63..871afce5 100644 --- a/drivers/gpu/nvgpu/volt/volt_pmu.c +++ b/drivers/gpu/nvgpu/volt/volt_pmu.c | |||
@@ -51,12 +51,17 @@ static void volt_rpc_pmucmdhandler(struct gk20a *g, struct pmu_msg *msg, | |||
51 | static u32 volt_pmu_rpc_execute(struct gk20a *g, | 51 | static u32 volt_pmu_rpc_execute(struct gk20a *g, |
52 | struct nv_pmu_volt_rpc *prpc_call) | 52 | struct nv_pmu_volt_rpc *prpc_call) |
53 | { | 53 | { |
54 | struct pmu_cmd cmd = { { 0 } }; | 54 | struct pmu_cmd cmd; |
55 | struct pmu_msg msg = { { 0 } }; | 55 | struct pmu_msg msg; |
56 | struct pmu_payload payload = { { 0 } }; | 56 | struct pmu_payload payload; |
57 | u32 status = 0; | 57 | u32 status = 0; |
58 | u32 seqdesc; | 58 | u32 seqdesc; |
59 | struct volt_rpc_pmucmdhandler_params handler = {0}; | 59 | struct volt_rpc_pmucmdhandler_params handler; |
60 | |||
61 | memset(&payload, 0, sizeof(struct pmu_payload)); | ||
62 | memset(&cmd, 0, sizeof(struct pmu_cmd)); | ||
63 | memset(&msg, 0, sizeof(struct pmu_msg)); | ||
64 | memset(&handler, 0, sizeof(struct volt_rpc_pmucmdhandler_params)); | ||
60 | 65 | ||
61 | cmd.hdr.unit_id = PMU_UNIT_VOLT; | 66 | cmd.hdr.unit_id = PMU_UNIT_VOLT; |
62 | cmd.hdr.size = (u32)sizeof(struct nv_pmu_volt_cmd) + | 67 | cmd.hdr.size = (u32)sizeof(struct nv_pmu_volt_cmd) + |