diff options
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/clk_gm20b.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c index 44ac4dd0..c4e65767 100644 --- a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c | |||
@@ -20,13 +20,13 @@ | |||
20 | #include <linux/debugfs.h> | 20 | #include <linux/debugfs.h> |
21 | #include <linux/uaccess.h> | 21 | #include <linux/uaccess.h> |
22 | #endif | 22 | #endif |
23 | #include <soc/tegra/fuse.h> | ||
24 | 23 | ||
25 | #include "gk20a/gk20a.h" | 24 | #include "gk20a/gk20a.h" |
26 | #include "gk20a/platform_gk20a.h" | 25 | #include "gk20a/platform_gk20a.h" |
27 | #include "clk_gm20b.h" | 26 | #include "clk_gm20b.h" |
28 | 27 | ||
29 | #include <nvgpu/soc.h> | 28 | #include <nvgpu/soc.h> |
29 | #include <nvgpu/fuse.h> | ||
30 | #include <nvgpu/bug.h> | 30 | #include <nvgpu/bug.h> |
31 | 31 | ||
32 | #include <nvgpu/hw/gm20b/hw_trim_gm20b.h> | 32 | #include <nvgpu/hw/gm20b/hw_trim_gm20b.h> |
@@ -280,12 +280,12 @@ static inline int fuse_get_gpcpll_adc_intercept_uv(u32 val) | |||
280 | return ((val >> 4) & 0x3ff) * 1000 + ((val >> 0) & 0xf) * 100; | 280 | return ((val >> 4) & 0x3ff) * 1000 + ((val >> 0) & 0xf) * 100; |
281 | } | 281 | } |
282 | 282 | ||
283 | static int tegra_fuse_calib_gpcpll_get_adc(int *slope_uv, int *intercept_uv) | 283 | static int nvgpu_fuse_calib_gpcpll_get_adc(int *slope_uv, int *intercept_uv) |
284 | { | 284 | { |
285 | u32 val; | 285 | u32 val; |
286 | int ret; | 286 | int ret; |
287 | 287 | ||
288 | ret = tegra_fuse_readl(FUSE_RESERVED_CALIB, &val); | 288 | ret = nvgpu_tegra_fuse_read(FUSE_RESERVED_CALIB, &val); |
289 | if (ret) | 289 | if (ret) |
290 | return ret; | 290 | return ret; |
291 | 291 | ||
@@ -298,9 +298,9 @@ static int tegra_fuse_calib_gpcpll_get_adc(int *slope_uv, int *intercept_uv) | |||
298 | } | 298 | } |
299 | 299 | ||
300 | #ifdef CONFIG_TEGRA_USE_NA_GPCPLL | 300 | #ifdef CONFIG_TEGRA_USE_NA_GPCPLL |
301 | static bool tegra_fuse_can_use_na_gpcpll(void) | 301 | static bool nvgpu_fuse_can_use_na_gpcpll(void) |
302 | { | 302 | { |
303 | return tegra_sku_info.gpu_speedo_id; | 303 | return nvgpu_tegra_get_gpu_speedo_id(); |
304 | } | 304 | } |
305 | #endif | 305 | #endif |
306 | 306 | ||
@@ -313,7 +313,7 @@ static int clk_config_calibration_params(struct gk20a *g) | |||
313 | int slope, offs; | 313 | int slope, offs; |
314 | struct pll_parms *p = &gpc_pll_params; | 314 | struct pll_parms *p = &gpc_pll_params; |
315 | 315 | ||
316 | if (!tegra_fuse_calib_gpcpll_get_adc(&slope, &offs)) { | 316 | if (!nvgpu_fuse_calib_gpcpll_get_adc(&slope, &offs)) { |
317 | p->uvdet_slope = slope; | 317 | p->uvdet_slope = slope; |
318 | p->uvdet_offs = offs; | 318 | p->uvdet_offs = offs; |
319 | } | 319 | } |
@@ -1182,7 +1182,7 @@ int gm20b_init_clk_setup_sw(struct gk20a *g) | |||
1182 | */ | 1182 | */ |
1183 | clk_config_calibration_params(g); | 1183 | clk_config_calibration_params(g); |
1184 | #ifdef CONFIG_TEGRA_USE_NA_GPCPLL | 1184 | #ifdef CONFIG_TEGRA_USE_NA_GPCPLL |
1185 | if (tegra_fuse_can_use_na_gpcpll()) { | 1185 | if (nvgpu_fuse_can_use_na_gpcpll()) { |
1186 | /* NA mode is supported only at max update rate 38.4 MHz */ | 1186 | /* NA mode is supported only at max update rate 38.4 MHz */ |
1187 | BUG_ON(clk->gpc_pll.clk_in != gpc_pll_params.max_u); | 1187 | BUG_ON(clk->gpc_pll.clk_in != gpc_pll_params.max_u); |
1188 | clk->gpc_pll.mode = GPC_PLL_MODE_DVFS; | 1188 | clk->gpc_pll.mode = GPC_PLL_MODE_DVFS; |