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-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/enabled.h4
-rw-r--r--drivers/gpu/nvgpu/os/linux/ioctl_channel.c69
-rw-r--r--include/uapi/linux/nvgpu.h27
3 files changed, 4 insertions, 96 deletions
diff --git a/drivers/gpu/nvgpu/include/nvgpu/enabled.h b/drivers/gpu/nvgpu/include/nvgpu/enabled.h
index 77b54ab9..ef55dad8 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/enabled.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/enabled.h
@@ -92,9 +92,9 @@ struct gk20a;
92#define NVGPU_HAS_SYNCPOINTS 30 92#define NVGPU_HAS_SYNCPOINTS 30
93/* sync fence FDs are available in, e.g., submit_gpfifo */ 93/* sync fence FDs are available in, e.g., submit_gpfifo */
94#define NVGPU_SUPPORT_SYNC_FENCE_FDS 31 94#define NVGPU_SUPPORT_SYNC_FENCE_FDS 31
95/* NVGPU_IOCTL_CHANNEL_CYCLE_STATS is available */ 95/* NVGPU_DBG_GPU_IOCTL_CYCLE_STATS is available */
96#define NVGPU_SUPPORT_CYCLE_STATS 32 96#define NVGPU_SUPPORT_CYCLE_STATS 32
97/* NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT is available */ 97/* NVGPU_DBG_GPU_IOCTL_CYCLE_STATS_SNAPSHOT is available */
98#define NVGPU_SUPPORT_CYCLE_STATS_SNAPSHOT 33 98#define NVGPU_SUPPORT_CYCLE_STATS_SNAPSHOT 33
99/* Both gpu driver and device support TSG */ 99/* Both gpu driver and device support TSG */
100#define NVGPU_SUPPORT_TSG 34 100#define NVGPU_SUPPORT_TSG 34
diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_channel.c b/drivers/gpu/nvgpu/os/linux/ioctl_channel.c
index da35b93f..0f39cc7a 100644
--- a/drivers/gpu/nvgpu/os/linux/ioctl_channel.c
+++ b/drivers/gpu/nvgpu/os/linux/ioctl_channel.c
@@ -276,47 +276,6 @@ int gk20a_channel_free_cycle_stats_snapshot(struct channel_gk20a *ch)
276 276
277 return ret; 277 return ret;
278} 278}
279
280static int gk20a_channel_cycle_stats_snapshot(struct channel_gk20a *ch,
281 struct nvgpu_cycle_stats_snapshot_args *args)
282{
283 int ret;
284
285 /* is it allowed to handle calls for current GPU? */
286 if (!nvgpu_is_enabled(ch->g, NVGPU_SUPPORT_CYCLE_STATS_SNAPSHOT))
287 return -ENOSYS;
288
289 if (!args->dmabuf_fd)
290 return -EINVAL;
291
292 nvgpu_speculation_barrier();
293 /* handle the command (most frequent cases first) */
294 switch (args->cmd) {
295 case NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT_CMD_FLUSH:
296 ret = gk20a_flush_cycle_stats_snapshot(ch);
297 args->extra = 0;
298 break;
299
300 case NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT_CMD_ATTACH:
301 ret = gk20a_attach_cycle_stats_snapshot(ch,
302 args->dmabuf_fd,
303 args->extra,
304 &args->extra);
305 break;
306
307 case NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT_CMD_DETACH:
308 ret = gk20a_channel_free_cycle_stats_snapshot(ch);
309 args->extra = 0;
310 break;
311
312 default:
313 pr_err("cyclestats: unknown command %u\n", args->cmd);
314 ret = -EINVAL;
315 break;
316 }
317
318 return ret;
319}
320#endif 279#endif
321 280
322static int gk20a_channel_set_wdt_status(struct channel_gk20a *ch, 281static int gk20a_channel_set_wdt_status(struct channel_gk20a *ch,
@@ -1269,20 +1228,6 @@ long gk20a_channel_ioctl(struct file *filp,
1269 (struct nvgpu_set_error_notifier *)buf); 1228 (struct nvgpu_set_error_notifier *)buf);
1270 gk20a_idle(ch->g); 1229 gk20a_idle(ch->g);
1271 break; 1230 break;
1272#ifdef CONFIG_GK20A_CYCLE_STATS
1273 case NVGPU_IOCTL_CHANNEL_CYCLE_STATS:
1274 err = gk20a_busy(ch->g);
1275 if (err) {
1276 dev_err(dev,
1277 "%s: failed to host gk20a for ioctl cmd: 0x%x",
1278 __func__, cmd);
1279 break;
1280 }
1281 err = gk20a_channel_cycle_stats(ch,
1282 ((struct nvgpu_cycle_stats_args *)buf)->dmabuf_fd);
1283 gk20a_idle(ch->g);
1284 break;
1285#endif
1286 case NVGPU_IOCTL_CHANNEL_SET_TIMEOUT: 1231 case NVGPU_IOCTL_CHANNEL_SET_TIMEOUT:
1287 { 1232 {
1288 u32 timeout = 1233 u32 timeout =
@@ -1385,20 +1330,6 @@ long gk20a_channel_ioctl(struct file *filp,
1385 NVGPU_ERR_NOTIFIER_RESETCHANNEL_VERIF_ERROR, true); 1330 NVGPU_ERR_NOTIFIER_RESETCHANNEL_VERIF_ERROR, true);
1386 gk20a_idle(ch->g); 1331 gk20a_idle(ch->g);
1387 break; 1332 break;
1388#ifdef CONFIG_GK20A_CYCLE_STATS
1389 case NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT:
1390 err = gk20a_busy(ch->g);
1391 if (err) {
1392 dev_err(dev,
1393 "%s: failed to host gk20a for ioctl cmd: 0x%x",
1394 __func__, cmd);
1395 break;
1396 }
1397 err = gk20a_channel_cycle_stats_snapshot(ch,
1398 (struct nvgpu_cycle_stats_snapshot_args *)buf);
1399 gk20a_idle(ch->g);
1400 break;
1401#endif
1402 case NVGPU_IOCTL_CHANNEL_WDT: 1333 case NVGPU_IOCTL_CHANNEL_WDT:
1403 err = gk20a_channel_set_wdt_status(ch, 1334 err = gk20a_channel_set_wdt_status(ch,
1404 (struct nvgpu_channel_wdt_args *)buf); 1335 (struct nvgpu_channel_wdt_args *)buf);
diff --git a/include/uapi/linux/nvgpu.h b/include/uapi/linux/nvgpu.h
index 2c130d82..873e787f 100644
--- a/include/uapi/linux/nvgpu.h
+++ b/include/uapi/linux/nvgpu.h
@@ -114,9 +114,9 @@ struct nvgpu_gpu_zbc_query_table_args {
114#define NVGPU_GPU_FLAGS_SUPPORT_SPARSE_ALLOCS (1ULL << 2) 114#define NVGPU_GPU_FLAGS_SUPPORT_SPARSE_ALLOCS (1ULL << 2)
115/* sync fence FDs are available in, e.g., submit_gpfifo */ 115/* sync fence FDs are available in, e.g., submit_gpfifo */
116#define NVGPU_GPU_FLAGS_SUPPORT_SYNC_FENCE_FDS (1ULL << 3) 116#define NVGPU_GPU_FLAGS_SUPPORT_SYNC_FENCE_FDS (1ULL << 3)
117/* NVGPU_IOCTL_CHANNEL_CYCLE_STATS is available */ 117/* NVGPU_DBG_GPU_IOCTL_CYCLE_STATS is available */
118#define NVGPU_GPU_FLAGS_SUPPORT_CYCLE_STATS (1ULL << 4) 118#define NVGPU_GPU_FLAGS_SUPPORT_CYCLE_STATS (1ULL << 4)
119/* NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT is available */ 119/* NVGPU_DBG_GPU_IOCTL_CYCLE_STATS_SNAPSHOT is available */
120#define NVGPU_GPU_FLAGS_SUPPORT_CYCLE_STATS_SNAPSHOT (1ULL << 6) 120#define NVGPU_GPU_FLAGS_SUPPORT_CYCLE_STATS_SNAPSHOT (1ULL << 6)
121/* User-space managed address spaces support */ 121/* User-space managed address spaces support */
122#define NVGPU_GPU_FLAGS_SUPPORT_USERSPACE_MANAGED_AS (1ULL << 7) 122#define NVGPU_GPU_FLAGS_SUPPORT_USERSPACE_MANAGED_AS (1ULL << 7)
@@ -1624,11 +1624,6 @@ struct nvgpu_wait_args {
1624 } condition; /* determined by type field */ 1624 } condition; /* determined by type field */
1625}; 1625};
1626 1626
1627/* cycle stats support */
1628struct nvgpu_cycle_stats_args {
1629 __u32 dmabuf_fd;
1630} __packed;
1631
1632struct nvgpu_set_timeout_args { 1627struct nvgpu_set_timeout_args {
1633 __u32 timeout; 1628 __u32 timeout;
1634} __packed; 1629} __packed;
@@ -1677,20 +1672,6 @@ struct nvgpu_notification {
1677#define NVGPU_CHANNEL_SUBMIT_TIMEOUT 1 1672#define NVGPU_CHANNEL_SUBMIT_TIMEOUT 1
1678}; 1673};
1679 1674
1680/* cycle stats snapshot buffer support for mode E */
1681struct nvgpu_cycle_stats_snapshot_args {
1682 __u32 cmd; /* in: command to handle */
1683 __u32 dmabuf_fd; /* in: dma buffer handler */
1684 __u32 extra; /* in/out: extra payload e.g.*/
1685 /* counter/start perfmon */
1686 __u32 pad0[1];
1687};
1688
1689/* valid commands to control cycle stats shared buffer */
1690#define NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT_CMD_FLUSH 0
1691#define NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT_CMD_ATTACH 1
1692#define NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT_CMD_DETACH 2
1693
1694/* configure watchdog per-channel */ 1675/* configure watchdog per-channel */
1695struct nvgpu_channel_wdt_args { 1676struct nvgpu_channel_wdt_args {
1696 __u32 wdt_status; 1677 __u32 wdt_status;
@@ -1789,8 +1770,6 @@ struct nvgpu_reschedule_runlist_args {
1789 _IOW(NVGPU_IOCTL_MAGIC, 100, struct nvgpu_alloc_gpfifo_args) 1770 _IOW(NVGPU_IOCTL_MAGIC, 100, struct nvgpu_alloc_gpfifo_args)
1790#define NVGPU_IOCTL_CHANNEL_WAIT \ 1771#define NVGPU_IOCTL_CHANNEL_WAIT \
1791 _IOWR(NVGPU_IOCTL_MAGIC, 102, struct nvgpu_wait_args) 1772 _IOWR(NVGPU_IOCTL_MAGIC, 102, struct nvgpu_wait_args)
1792#define NVGPU_IOCTL_CHANNEL_CYCLE_STATS \
1793 _IOWR(NVGPU_IOCTL_MAGIC, 106, struct nvgpu_cycle_stats_args)
1794#define NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO \ 1773#define NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO \
1795 _IOWR(NVGPU_IOCTL_MAGIC, 107, struct nvgpu_submit_gpfifo_args) 1774 _IOWR(NVGPU_IOCTL_MAGIC, 107, struct nvgpu_submit_gpfifo_args)
1796#define NVGPU_IOCTL_CHANNEL_ALLOC_OBJ_CTX \ 1775#define NVGPU_IOCTL_CHANNEL_ALLOC_OBJ_CTX \
@@ -1811,8 +1790,6 @@ struct nvgpu_reschedule_runlist_args {
1811 _IO(NVGPU_IOCTL_MAGIC, 116) 1790 _IO(NVGPU_IOCTL_MAGIC, 116)
1812#define NVGPU_IOCTL_CHANNEL_EVENT_ID_CTRL \ 1791#define NVGPU_IOCTL_CHANNEL_EVENT_ID_CTRL \
1813 _IOWR(NVGPU_IOCTL_MAGIC, 117, struct nvgpu_event_id_ctrl_args) 1792 _IOWR(NVGPU_IOCTL_MAGIC, 117, struct nvgpu_event_id_ctrl_args)
1814#define NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT \
1815 _IOWR(NVGPU_IOCTL_MAGIC, 118, struct nvgpu_cycle_stats_snapshot_args)
1816#define NVGPU_IOCTL_CHANNEL_WDT \ 1793#define NVGPU_IOCTL_CHANNEL_WDT \
1817 _IOW(NVGPU_IOCTL_MAGIC, 119, struct nvgpu_channel_wdt_args) 1794 _IOW(NVGPU_IOCTL_MAGIC, 119, struct nvgpu_channel_wdt_args)
1818#define NVGPU_IOCTL_CHANNEL_SET_RUNLIST_INTERLEAVE \ 1795#define NVGPU_IOCTL_CHANNEL_SET_RUNLIST_INTERLEAVE \