diff options
-rw-r--r-- | drivers/gpu/nvgpu/common/fifo/channel.c | 5 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/fifo/tsg.c | 4 |
2 files changed, 6 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/common/fifo/channel.c b/drivers/gpu/nvgpu/common/fifo/channel.c index 4bea032a..fefd90d8 100644 --- a/drivers/gpu/nvgpu/common/fifo/channel.c +++ b/drivers/gpu/nvgpu/common/fifo/channel.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GK20A Graphics channel | 2 | * GK20A Graphics channel |
3 | * | 3 | * |
4 | * Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2011-2019, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -722,7 +722,8 @@ struct channel_gk20a *gk20a_open_new_channel(struct gk20a *g, | |||
722 | /* set gr host default timeout */ | 722 | /* set gr host default timeout */ |
723 | ch->timeout_ms_max = gk20a_get_gr_idle_timeout(g); | 723 | ch->timeout_ms_max = gk20a_get_gr_idle_timeout(g); |
724 | ch->timeout_debug_dump = true; | 724 | ch->timeout_debug_dump = true; |
725 | ch->ch_timedout = false; | 725 | /* ch is unserviceable until it is bound to tsg */ |
726 | ch->ch_timedout = true; | ||
726 | 727 | ||
727 | /* init kernel watchdog timeout */ | 728 | /* init kernel watchdog timeout */ |
728 | ch->timeout.enabled = true; | 729 | ch->timeout.enabled = true; |
diff --git a/drivers/gpu/nvgpu/common/fifo/tsg.c b/drivers/gpu/nvgpu/common/fifo/tsg.c index e6dfbae6..6d6c322e 100644 --- a/drivers/gpu/nvgpu/common/fifo/tsg.c +++ b/drivers/gpu/nvgpu/common/fifo/tsg.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -134,6 +134,8 @@ int gk20a_tsg_bind_channel(struct tsg_gk20a *tsg, | |||
134 | nvgpu_rwsem_down_write(&tsg->ch_list_lock); | 134 | nvgpu_rwsem_down_write(&tsg->ch_list_lock); |
135 | nvgpu_list_add_tail(&ch->ch_entry, &tsg->ch_list); | 135 | nvgpu_list_add_tail(&ch->ch_entry, &tsg->ch_list); |
136 | ch->tsgid = tsg->tsgid; | 136 | ch->tsgid = tsg->tsgid; |
137 | /* channel is serviceable after it is bound to tsg */ | ||
138 | ch->ch_timedout = false; | ||
137 | nvgpu_rwsem_up_write(&tsg->ch_list_lock); | 139 | nvgpu_rwsem_up_write(&tsg->ch_list_lock); |
138 | 140 | ||
139 | nvgpu_ref_get(&tsg->refcount); | 141 | nvgpu_ref_get(&tsg->refcount); |