diff options
28 files changed, 136 insertions, 35 deletions
diff --git a/drivers/gpu/nvgpu/common/fb/fb_gv100.c b/drivers/gpu/nvgpu/common/fb/fb_gv100.c index 3bfac676..1088ca90 100644 --- a/drivers/gpu/nvgpu/common/fb/fb_gv100.c +++ b/drivers/gpu/nvgpu/common/fb/fb_gv100.c | |||
@@ -39,11 +39,11 @@ | |||
39 | #include <nvgpu/utils.h> | 39 | #include <nvgpu/utils.h> |
40 | #include <nvgpu/timers.h> | 40 | #include <nvgpu/timers.h> |
41 | #include <nvgpu/gk20a.h> | 41 | #include <nvgpu/gk20a.h> |
42 | #include <nvgpu/unit.h> | ||
42 | 43 | ||
43 | #include "fb_gv100.h" | 44 | #include "fb_gv100.h" |
44 | 45 | ||
45 | #include <nvgpu/hw/gv100/hw_fb_gv100.h> | 46 | #include <nvgpu/hw/gv100/hw_fb_gv100.h> |
46 | #include <nvgpu/hw/gv100/hw_mc_gv100.h> | ||
47 | 47 | ||
48 | #define HW_SCRUB_TIMEOUT_DEFAULT 100 /* usec */ | 48 | #define HW_SCRUB_TIMEOUT_DEFAULT 100 /* usec */ |
49 | #define HW_SCRUB_TIMEOUT_MAX 2000000 /* usec */ | 49 | #define HW_SCRUB_TIMEOUT_MAX 2000000 /* usec */ |
@@ -160,7 +160,7 @@ int gv100_fb_memory_unlock(struct gk20a *g) | |||
160 | } | 160 | } |
161 | 161 | ||
162 | /* Enable nvdec */ | 162 | /* Enable nvdec */ |
163 | g->ops.mc.enable(g, mc_enable_nvdec_enabled_f()); | 163 | g->ops.mc.enable(g, g->ops.mc.reset_mask(g, NVGPU_UNIT_NVDEC)); |
164 | 164 | ||
165 | /* nvdec falcon reset */ | 165 | /* nvdec falcon reset */ |
166 | nvgpu_flcn_reset(&g->nvdec_flcn); | 166 | nvgpu_flcn_reset(&g->nvdec_flcn); |
diff --git a/drivers/gpu/nvgpu/common/fb/fb_gv11b.c b/drivers/gpu/nvgpu/common/fb/fb_gv11b.c index a03c7da7..75968ba6 100644 --- a/drivers/gpu/nvgpu/common/fb/fb_gv11b.c +++ b/drivers/gpu/nvgpu/common/fb/fb_gv11b.c | |||
@@ -46,7 +46,6 @@ | |||
46 | #include "fb_gv11b.h" | 46 | #include "fb_gv11b.h" |
47 | 47 | ||
48 | #include <nvgpu/hw/gv11b/hw_fb_gv11b.h> | 48 | #include <nvgpu/hw/gv11b/hw_fb_gv11b.h> |
49 | #include <nvgpu/hw/gv11b/hw_mc_gv11b.h> | ||
50 | #include <nvgpu/hw/gv11b/hw_gmmu_gv11b.h> | 49 | #include <nvgpu/hw/gv11b/hw_gmmu_gv11b.h> |
51 | 50 | ||
52 | static int gv11b_fb_fix_page_fault(struct gk20a *g, | 51 | static int gv11b_fb_fix_page_fault(struct gk20a *g, |
diff --git a/drivers/gpu/nvgpu/common/mc/mc_gm20b.c b/drivers/gpu/nvgpu/common/mc/mc_gm20b.c index c4e682ec..1194be85 100644 --- a/drivers/gpu/nvgpu/common/mc/mc_gm20b.c +++ b/drivers/gpu/nvgpu/common/mc/mc_gm20b.c | |||
@@ -28,6 +28,7 @@ | |||
28 | #include <nvgpu/io.h> | 28 | #include <nvgpu/io.h> |
29 | #include <nvgpu/mc.h> | 29 | #include <nvgpu/mc.h> |
30 | #include <nvgpu/gk20a.h> | 30 | #include <nvgpu/gk20a.h> |
31 | #include <nvgpu/bug.h> | ||
31 | 32 | ||
32 | #include "mc_gm20b.h" | 33 | #include "mc_gm20b.h" |
33 | 34 | ||
@@ -292,3 +293,51 @@ void gm20b_mc_log_pending_intrs(struct gk20a *g) | |||
292 | } | 293 | } |
293 | } | 294 | } |
294 | 295 | ||
296 | u32 gm20b_mc_reset_mask(struct gk20a *g, enum nvgpu_unit unit) | ||
297 | { | ||
298 | u32 mask = 0; | ||
299 | |||
300 | switch(unit) { | ||
301 | case NVGPU_UNIT_FIFO: | ||
302 | mask = mc_enable_pfifo_enabled_f(); | ||
303 | break; | ||
304 | case NVGPU_UNIT_PERFMON: | ||
305 | mask = mc_enable_perfmon_enabled_f(); | ||
306 | break; | ||
307 | case NVGPU_UNIT_GRAPH: | ||
308 | mask = mc_enable_pgraph_enabled_f(); | ||
309 | break; | ||
310 | case NVGPU_UNIT_BLG: | ||
311 | mask = mc_enable_blg_enabled_f(); | ||
312 | break; | ||
313 | case NVGPU_UNIT_PWR: | ||
314 | mask = mc_enable_pwr_enabled_f(); | ||
315 | break; | ||
316 | default: | ||
317 | nvgpu_err(g, "unknown reset unit %d", unit); | ||
318 | BUG(); | ||
319 | break; | ||
320 | } | ||
321 | |||
322 | return mask; | ||
323 | } | ||
324 | |||
325 | bool gm20b_mc_is_enabled(struct gk20a *g, enum nvgpu_unit unit) | ||
326 | { | ||
327 | u32 mask = g->ops.mc.reset_mask(g, unit); | ||
328 | |||
329 | return (nvgpu_readl(g, mc_enable_r()) & mask) != 0U; | ||
330 | } | ||
331 | |||
332 | void gm20b_mc_fb_reset(struct gk20a *g) | ||
333 | { | ||
334 | u32 val; | ||
335 | |||
336 | nvgpu_log_info(g, "reset gk20a fb"); | ||
337 | |||
338 | val = gk20a_readl(g, mc_elpg_enable_r()); | ||
339 | val |= mc_elpg_enable_xbar_enabled_f() | ||
340 | | mc_elpg_enable_pfb_enabled_f() | ||
341 | | mc_elpg_enable_hub_enabled_f(); | ||
342 | gk20a_writel(g, mc_elpg_enable_r(), val); | ||
343 | } | ||
diff --git a/drivers/gpu/nvgpu/common/mc/mc_gm20b.h b/drivers/gpu/nvgpu/common/mc/mc_gm20b.h index 6700a48c..fcf02077 100644 --- a/drivers/gpu/nvgpu/common/mc/mc_gm20b.h +++ b/drivers/gpu/nvgpu/common/mc/mc_gm20b.h | |||
@@ -47,5 +47,8 @@ bool gm20b_mc_is_intr1_pending(struct gk20a *g, | |||
47 | enum nvgpu_unit unit, u32 mc_intr_1); | 47 | enum nvgpu_unit unit, u32 mc_intr_1); |
48 | void gm20b_mc_log_pending_intrs(struct gk20a *g); | 48 | void gm20b_mc_log_pending_intrs(struct gk20a *g); |
49 | void gm20b_mc_handle_intr_nonstall(struct gk20a *g, u32 ops); | 49 | void gm20b_mc_handle_intr_nonstall(struct gk20a *g, u32 ops); |
50 | u32 gm20b_mc_reset_mask(struct gk20a *g, enum nvgpu_unit unit); | ||
51 | bool gm20b_mc_is_enabled(struct gk20a *g, enum nvgpu_unit unit); | ||
52 | void gm20b_mc_fb_reset(struct gk20a *g); | ||
50 | 53 | ||
51 | #endif /* NVGPU_MC_GM20B_H */ | 54 | #endif /* NVGPU_MC_GM20B_H */ |
diff --git a/drivers/gpu/nvgpu/common/mc/mc_gv100.c b/drivers/gpu/nvgpu/common/mc/mc_gv100.c index b67f9bbe..77155d14 100644 --- a/drivers/gpu/nvgpu/common/mc/mc_gv100.c +++ b/drivers/gpu/nvgpu/common/mc/mc_gv100.c | |||
@@ -26,6 +26,8 @@ | |||
26 | #include <nvgpu/io.h> | 26 | #include <nvgpu/io.h> |
27 | #include <nvgpu/mc.h> | 27 | #include <nvgpu/mc.h> |
28 | #include <nvgpu/gk20a.h> | 28 | #include <nvgpu/gk20a.h> |
29 | #include <nvgpu/unit.h> | ||
30 | #include <nvgpu/bug.h> | ||
29 | 31 | ||
30 | #include "mc_gp10b.h" | 32 | #include "mc_gp10b.h" |
31 | #include "mc_gv100.h" | 33 | #include "mc_gv100.h" |
@@ -88,3 +90,35 @@ bool gv100_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 act_eng_id, | |||
88 | 90 | ||
89 | return (mc_intr_0 & (eng_intr_mask | stall_intr)) != 0U; | 91 | return (mc_intr_0 & (eng_intr_mask | stall_intr)) != 0U; |
90 | } | 92 | } |
93 | |||
94 | u32 gv100_mc_reset_mask(struct gk20a *g, enum nvgpu_unit unit) | ||
95 | { | ||
96 | u32 mask = 0; | ||
97 | |||
98 | switch(unit) { | ||
99 | case NVGPU_UNIT_FIFO: | ||
100 | mask = mc_enable_pfifo_enabled_f(); | ||
101 | break; | ||
102 | case NVGPU_UNIT_PERFMON: | ||
103 | mask = mc_enable_perfmon_enabled_f(); | ||
104 | break; | ||
105 | case NVGPU_UNIT_GRAPH: | ||
106 | mask = mc_enable_pgraph_enabled_f(); | ||
107 | break; | ||
108 | case NVGPU_UNIT_BLG: | ||
109 | mask = mc_enable_blg_enabled_f(); | ||
110 | break; | ||
111 | case NVGPU_UNIT_PWR: | ||
112 | mask = mc_enable_pwr_enabled_f(); | ||
113 | break; | ||
114 | case NVGPU_UNIT_NVDEC: | ||
115 | mask = mc_enable_nvdec_enabled_f(); | ||
116 | break; | ||
117 | default: | ||
118 | nvgpu_err(g, "unknown reset unit %d", unit); | ||
119 | BUG(); | ||
120 | break; | ||
121 | } | ||
122 | |||
123 | return mask; | ||
124 | } | ||
diff --git a/drivers/gpu/nvgpu/common/mc/mc_gv100.h b/drivers/gpu/nvgpu/common/mc/mc_gv100.h index c0a16ad9..764d59b1 100644 --- a/drivers/gpu/nvgpu/common/mc/mc_gv100.h +++ b/drivers/gpu/nvgpu/common/mc/mc_gv100.h | |||
@@ -31,4 +31,6 @@ void mc_gv100_intr_enable(struct gk20a *g); | |||
31 | bool gv100_mc_is_intr_nvlink_pending(struct gk20a *g, u32 mc_intr_0); | 31 | bool gv100_mc_is_intr_nvlink_pending(struct gk20a *g, u32 mc_intr_0); |
32 | bool gv100_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 act_eng_id, | 32 | bool gv100_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 act_eng_id, |
33 | u32 *eng_intr_pending); | 33 | u32 *eng_intr_pending); |
34 | u32 gv100_mc_reset_mask(struct gk20a *g, enum nvgpu_unit unit); | ||
35 | |||
34 | #endif | 36 | #endif |
diff --git a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c index 436d3205..6df8f6e4 100644 --- a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c | |||
@@ -39,7 +39,6 @@ | |||
39 | #include <nvgpu/hw/gk20a/hw_ccsr_gk20a.h> | 39 | #include <nvgpu/hw/gk20a/hw_ccsr_gk20a.h> |
40 | #include <nvgpu/hw/gk20a/hw_ram_gk20a.h> | 40 | #include <nvgpu/hw/gk20a/hw_ram_gk20a.h> |
41 | #include <nvgpu/hw/gk20a/hw_top_gk20a.h> | 41 | #include <nvgpu/hw/gk20a/hw_top_gk20a.h> |
42 | #include <nvgpu/hw/gk20a/hw_mc_gk20a.h> | ||
43 | #include <nvgpu/hw/gk20a/hw_gr_gk20a.h> | 42 | #include <nvgpu/hw/gk20a/hw_gr_gk20a.h> |
44 | #include <nvgpu/barrier.h> | 43 | #include <nvgpu/barrier.h> |
45 | 44 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/css_gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/css_gr_gk20a.c index 00d1b196..28a3d495 100644 --- a/drivers/gpu/nvgpu/gk20a/css_gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/css_gr_gk20a.c | |||
@@ -34,12 +34,12 @@ | |||
34 | #include <nvgpu/io.h> | 34 | #include <nvgpu/io.h> |
35 | #include <nvgpu/utils.h> | 35 | #include <nvgpu/utils.h> |
36 | #include <nvgpu/channel.h> | 36 | #include <nvgpu/channel.h> |
37 | #include <nvgpu/unit.h> | ||
37 | 38 | ||
38 | #include "gk20a.h" | 39 | #include "gk20a.h" |
39 | #include "css_gr_gk20a.h" | 40 | #include "css_gr_gk20a.h" |
40 | 41 | ||
41 | #include <nvgpu/hw/gk20a/hw_perf_gk20a.h> | 42 | #include <nvgpu/hw/gk20a/hw_perf_gk20a.h> |
42 | #include <nvgpu/hw/gk20a/hw_mc_gk20a.h> | ||
43 | 43 | ||
44 | /* check client for pointed perfmon ownership */ | 44 | /* check client for pointed perfmon ownership */ |
45 | #define CONTAINS_PERFMON(cl, pm) \ | 45 | #define CONTAINS_PERFMON(cl, pm) \ |
@@ -89,7 +89,7 @@ static void css_hw_reset_streaming(struct gk20a *g) | |||
89 | u32 engine_status; | 89 | u32 engine_status; |
90 | 90 | ||
91 | /* reset the perfmon */ | 91 | /* reset the perfmon */ |
92 | g->ops.mc.reset(g, mc_enable_perfmon_enabled_f()); | 92 | g->ops.mc.reset(g, g->ops.mc.reset_mask(g, NVGPU_UNIT_PERFMON)); |
93 | 93 | ||
94 | /* RBUFEMPTY must be set -- otherwise we'll pick up */ | 94 | /* RBUFEMPTY must be set -- otherwise we'll pick up */ |
95 | /* snapshot that have been queued up from earlier */ | 95 | /* snapshot that have been queued up from earlier */ |
diff --git a/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c b/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c index ef505425..adc13c3d 100644 --- a/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c | |||
@@ -31,6 +31,7 @@ | |||
31 | #include <nvgpu/io.h> | 31 | #include <nvgpu/io.h> |
32 | #include <nvgpu/utils.h> | 32 | #include <nvgpu/utils.h> |
33 | #include <nvgpu/channel.h> | 33 | #include <nvgpu/channel.h> |
34 | #include <nvgpu/unit.h> | ||
34 | 35 | ||
35 | #include "gk20a.h" | 36 | #include "gk20a.h" |
36 | #include "gr_gk20a.h" | 37 | #include "gr_gk20a.h" |
@@ -39,14 +40,13 @@ | |||
39 | 40 | ||
40 | #include <nvgpu/hw/gk20a/hw_gr_gk20a.h> | 41 | #include <nvgpu/hw/gk20a/hw_gr_gk20a.h> |
41 | #include <nvgpu/hw/gk20a/hw_perf_gk20a.h> | 42 | #include <nvgpu/hw/gk20a/hw_perf_gk20a.h> |
42 | #include <nvgpu/hw/gk20a/hw_mc_gk20a.h> | ||
43 | 43 | ||
44 | static void gk20a_perfbuf_reset_streaming(struct gk20a *g) | 44 | static void gk20a_perfbuf_reset_streaming(struct gk20a *g) |
45 | { | 45 | { |
46 | u32 engine_status; | 46 | u32 engine_status; |
47 | u32 num_unread_bytes; | 47 | u32 num_unread_bytes; |
48 | 48 | ||
49 | g->ops.mc.reset(g, mc_enable_perfmon_enabled_f()); | 49 | g->ops.mc.reset(g, g->ops.mc.reset_mask(g, NVGPU_UNIT_PERFMON)); |
50 | 50 | ||
51 | engine_status = gk20a_readl(g, perf_pmasys_enginestatus_r()); | 51 | engine_status = gk20a_readl(g, perf_pmasys_enginestatus_r()); |
52 | WARN_ON(0u == | 52 | WARN_ON(0u == |
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index e1702bd7..3632963a 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | |||
@@ -44,6 +44,7 @@ | |||
44 | #include <nvgpu/io.h> | 44 | #include <nvgpu/io.h> |
45 | #include <nvgpu/utils.h> | 45 | #include <nvgpu/utils.h> |
46 | #include <nvgpu/channel.h> | 46 | #include <nvgpu/channel.h> |
47 | #include <nvgpu/unit.h> | ||
47 | 48 | ||
48 | #include "gk20a.h" | 49 | #include "gk20a.h" |
49 | #include "mm_gk20a.h" | 50 | #include "mm_gk20a.h" |
@@ -53,7 +54,6 @@ | |||
53 | #include <nvgpu/hw/gk20a/hw_ccsr_gk20a.h> | 54 | #include <nvgpu/hw/gk20a/hw_ccsr_gk20a.h> |
54 | #include <nvgpu/hw/gk20a/hw_ram_gk20a.h> | 55 | #include <nvgpu/hw/gk20a/hw_ram_gk20a.h> |
55 | #include <nvgpu/hw/gk20a/hw_top_gk20a.h> | 56 | #include <nvgpu/hw/gk20a/hw_top_gk20a.h> |
56 | #include <nvgpu/hw/gk20a/hw_mc_gk20a.h> | ||
57 | #include <nvgpu/hw/gk20a/hw_gr_gk20a.h> | 57 | #include <nvgpu/hw/gk20a/hw_gr_gk20a.h> |
58 | 58 | ||
59 | #define FECS_METHOD_WFI_RESTORE 0x80000 | 59 | #define FECS_METHOD_WFI_RESTORE 0x80000 |
@@ -822,7 +822,7 @@ int gk20a_init_fifo_reset_enable_hw(struct gk20a *g) | |||
822 | nvgpu_log_fn(g, " "); | 822 | nvgpu_log_fn(g, " "); |
823 | 823 | ||
824 | /* enable pmc pfifo */ | 824 | /* enable pmc pfifo */ |
825 | g->ops.mc.reset(g, mc_enable_pfifo_enabled_f()); | 825 | g->ops.mc.reset(g, g->ops.mc.reset_mask(g, NVGPU_UNIT_FIFO)); |
826 | 826 | ||
827 | if (g->ops.clock_gating.slcg_fifo_load_gating_prod) { | 827 | if (g->ops.clock_gating.slcg_fifo_load_gating_prod) { |
828 | g->ops.clock_gating.slcg_fifo_load_gating_prod(g, | 828 | g->ops.clock_gating.slcg_fifo_load_gating_prod(g, |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 0250e97e..6e63c138 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -42,6 +42,7 @@ | |||
42 | #include <nvgpu/io.h> | 42 | #include <nvgpu/io.h> |
43 | #include <nvgpu/utils.h> | 43 | #include <nvgpu/utils.h> |
44 | #include <nvgpu/channel.h> | 44 | #include <nvgpu/channel.h> |
45 | #include <nvgpu/unit.h> | ||
45 | 46 | ||
46 | #include "gk20a.h" | 47 | #include "gk20a.h" |
47 | #include "gr_gk20a.h" | 48 | #include "gr_gk20a.h" |
@@ -4708,9 +4709,9 @@ static int gk20a_init_gr_prepare(struct gk20a *g) | |||
4708 | u32 err = 0; | 4709 | u32 err = 0; |
4709 | 4710 | ||
4710 | /* reset gr engine */ | 4711 | /* reset gr engine */ |
4711 | g->ops.mc.reset(g, mc_enable_pgraph_enabled_f() | | 4712 | g->ops.mc.reset(g, g->ops.mc.reset_mask(g, NVGPU_UNIT_GRAPH) | |
4712 | mc_enable_blg_enabled_f() | | 4713 | g->ops.mc.reset_mask(g, NVGPU_UNIT_BLG) | |
4713 | mc_enable_perfmon_enabled_f()); | 4714 | g->ops.mc.reset_mask(g, NVGPU_UNIT_PERFMON)); |
4714 | 4715 | ||
4715 | gr_gk20a_load_gating_prod(g); | 4716 | gr_gk20a_load_gating_prod(g); |
4716 | 4717 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c index 6d5bea30..2e57d01e 100644 --- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c | |||
@@ -51,7 +51,6 @@ | |||
51 | #include <nvgpu/hw/gk20a/hw_gmmu_gk20a.h> | 51 | #include <nvgpu/hw/gk20a/hw_gmmu_gk20a.h> |
52 | #include <nvgpu/hw/gk20a/hw_ram_gk20a.h> | 52 | #include <nvgpu/hw/gk20a/hw_ram_gk20a.h> |
53 | #include <nvgpu/hw/gk20a/hw_pram_gk20a.h> | 53 | #include <nvgpu/hw/gk20a/hw_pram_gk20a.h> |
54 | #include <nvgpu/hw/gk20a/hw_mc_gk20a.h> | ||
55 | #include <nvgpu/hw/gk20a/hw_flush_gk20a.h> | 54 | #include <nvgpu/hw/gk20a/hw_flush_gk20a.h> |
56 | 55 | ||
57 | /* | 56 | /* |
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c index f231e088..6eecc4fa 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | |||
@@ -34,6 +34,7 @@ | |||
34 | #include <nvgpu/io.h> | 34 | #include <nvgpu/io.h> |
35 | #include <nvgpu/clk_arb.h> | 35 | #include <nvgpu/clk_arb.h> |
36 | #include <nvgpu/utils.h> | 36 | #include <nvgpu/utils.h> |
37 | #include <nvgpu/unit.h> | ||
37 | 38 | ||
38 | #include "gk20a.h" | 39 | #include "gk20a.h" |
39 | #include "gr_gk20a.h" | 40 | #include "gr_gk20a.h" |
@@ -497,24 +498,21 @@ void gk20a_write_dmatrfbase(struct gk20a *g, u32 addr) | |||
497 | 498 | ||
498 | bool gk20a_pmu_is_engine_in_reset(struct gk20a *g) | 499 | bool gk20a_pmu_is_engine_in_reset(struct gk20a *g) |
499 | { | 500 | { |
500 | u32 pmc_enable; | ||
501 | bool status = false; | 501 | bool status = false; |
502 | 502 | ||
503 | pmc_enable = gk20a_readl(g, mc_enable_r()); | 503 | status = g->ops.mc.is_enabled(g, NVGPU_UNIT_PWR); |
504 | if (mc_enable_pwr_v(pmc_enable) == | ||
505 | mc_enable_pwr_disabled_v()) { | ||
506 | status = true; | ||
507 | } | ||
508 | 504 | ||
509 | return status; | 505 | return status; |
510 | } | 506 | } |
511 | 507 | ||
512 | int gk20a_pmu_engine_reset(struct gk20a *g, bool do_reset) | 508 | int gk20a_pmu_engine_reset(struct gk20a *g, bool do_reset) |
513 | { | 509 | { |
510 | u32 reset_mask = g->ops.mc.reset_mask(g, NVGPU_UNIT_PWR); | ||
511 | |||
514 | if (do_reset) { | 512 | if (do_reset) { |
515 | g->ops.mc.enable(g, mc_enable_pwr_enabled_f()); | 513 | g->ops.mc.enable(g, reset_mask); |
516 | } else { | 514 | } else { |
517 | g->ops.mc.disable(g, mc_enable_pwr_enabled_f()); | 515 | g->ops.mc.disable(g, reset_mask); |
518 | } | 516 | } |
519 | 517 | ||
520 | return 0; | 518 | return 0; |
@@ -659,8 +657,6 @@ void gk20a_pmu_dump_falcon_stats(struct nvgpu_pmu *pmu) | |||
659 | pwr_falcon_exterrstat_valid_true_v()) { | 657 | pwr_falcon_exterrstat_valid_true_v()) { |
660 | nvgpu_err(g, "pwr_falcon_exterraddr_r : 0x%x", | 658 | nvgpu_err(g, "pwr_falcon_exterraddr_r : 0x%x", |
661 | gk20a_readl(g, pwr_falcon_exterraddr_r())); | 659 | gk20a_readl(g, pwr_falcon_exterraddr_r())); |
662 | nvgpu_err(g, "pmc_enable : 0x%x", | ||
663 | gk20a_readl(g, mc_enable_r())); | ||
664 | } | 660 | } |
665 | 661 | ||
666 | /* Print PMU F/W debug prints */ | 662 | /* Print PMU F/W debug prints */ |
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index 55c96274..1037b11b 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c | |||
@@ -592,6 +592,8 @@ static const struct gpu_ops gm20b_ops = { | |||
592 | .reset = gm20b_mc_reset, | 592 | .reset = gm20b_mc_reset, |
593 | .is_intr1_pending = gm20b_mc_is_intr1_pending, | 593 | .is_intr1_pending = gm20b_mc_is_intr1_pending, |
594 | .log_pending_intrs = gm20b_mc_log_pending_intrs, | 594 | .log_pending_intrs = gm20b_mc_log_pending_intrs, |
595 | .reset_mask = gm20b_mc_reset_mask, | ||
596 | .is_enabled = gm20b_mc_is_enabled, | ||
595 | }, | 597 | }, |
596 | .debug = { | 598 | .debug = { |
597 | .show_dump = gk20a_debug_show_dump, | 599 | .show_dump = gk20a_debug_show_dump, |
diff --git a/drivers/gpu/nvgpu/gp106/bios_gp106.c b/drivers/gpu/nvgpu/gp106/bios_gp106.c index f0db87ca..d4b93ded 100644 --- a/drivers/gpu/nvgpu/gp106/bios_gp106.c +++ b/drivers/gpu/nvgpu/gp106/bios_gp106.c | |||
@@ -34,7 +34,6 @@ | |||
34 | #include "gp106/mclk_gp106.h" | 34 | #include "gp106/mclk_gp106.h" |
35 | 35 | ||
36 | #include <nvgpu/hw/gp106/hw_pwr_gp106.h> | 36 | #include <nvgpu/hw/gp106/hw_pwr_gp106.h> |
37 | #include <nvgpu/hw/gp106/hw_mc_gp106.h> | ||
38 | #include <nvgpu/hw/gp106/hw_top_gp106.h> | 37 | #include <nvgpu/hw/gp106/hw_top_gp106.h> |
39 | 38 | ||
40 | #define PMU_BOOT_TIMEOUT_DEFAULT 100 /* usec */ | 39 | #define PMU_BOOT_TIMEOUT_DEFAULT 100 /* usec */ |
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index bbf02aab..23a2177c 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c | |||
@@ -720,6 +720,8 @@ static const struct gpu_ops gp106_ops = { | |||
720 | .reset = gm20b_mc_reset, | 720 | .reset = gm20b_mc_reset, |
721 | .is_intr1_pending = mc_gp10b_is_intr1_pending, | 721 | .is_intr1_pending = mc_gp10b_is_intr1_pending, |
722 | .log_pending_intrs = mc_gp10b_log_pending_intrs, | 722 | .log_pending_intrs = mc_gp10b_log_pending_intrs, |
723 | .reset_mask = gm20b_mc_reset_mask, | ||
724 | .is_enabled = gm20b_mc_is_enabled, | ||
723 | }, | 725 | }, |
724 | .debug = { | 726 | .debug = { |
725 | .show_dump = gk20a_debug_show_dump, | 727 | .show_dump = gk20a_debug_show_dump, |
diff --git a/drivers/gpu/nvgpu/gp106/pmu_gp106.c b/drivers/gpu/nvgpu/gp106/pmu_gp106.c index a95f05f0..d153c818 100644 --- a/drivers/gpu/nvgpu/gp106/pmu_gp106.c +++ b/drivers/gpu/nvgpu/gp106/pmu_gp106.c | |||
@@ -40,7 +40,6 @@ | |||
40 | #include "lpwr/rppg.h" | 40 | #include "lpwr/rppg.h" |
41 | 41 | ||
42 | #include <nvgpu/hw/gp106/hw_psec_gp106.h> | 42 | #include <nvgpu/hw/gp106/hw_psec_gp106.h> |
43 | #include <nvgpu/hw/gp106/hw_mc_gp106.h> | ||
44 | #include <nvgpu/hw/gp106/hw_pwr_gp106.h> | 43 | #include <nvgpu/hw/gp106/hw_pwr_gp106.h> |
45 | 44 | ||
46 | bool gp106_is_pmu_supported(struct gk20a *g) | 45 | bool gp106_is_pmu_supported(struct gk20a *g) |
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index a2658275..0a285a95 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c | |||
@@ -654,6 +654,8 @@ static const struct gpu_ops gp10b_ops = { | |||
654 | .reset = gm20b_mc_reset, | 654 | .reset = gm20b_mc_reset, |
655 | .is_intr1_pending = mc_gp10b_is_intr1_pending, | 655 | .is_intr1_pending = mc_gp10b_is_intr1_pending, |
656 | .log_pending_intrs = mc_gp10b_log_pending_intrs, | 656 | .log_pending_intrs = mc_gp10b_log_pending_intrs, |
657 | .reset_mask = gm20b_mc_reset_mask, | ||
658 | .is_enabled = gm20b_mc_is_enabled, | ||
657 | }, | 659 | }, |
658 | .debug = { | 660 | .debug = { |
659 | .show_dump = gk20a_debug_show_dump, | 661 | .show_dump = gk20a_debug_show_dump, |
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index da89d2b5..aae2bf73 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c | |||
@@ -817,6 +817,8 @@ static const struct gpu_ops gv100_ops = { | |||
817 | .is_intr_nvlink_pending = gv100_mc_is_intr_nvlink_pending, | 817 | .is_intr_nvlink_pending = gv100_mc_is_intr_nvlink_pending, |
818 | .is_stall_and_eng_intr_pending = | 818 | .is_stall_and_eng_intr_pending = |
819 | gv100_mc_is_stall_and_eng_intr_pending, | 819 | gv100_mc_is_stall_and_eng_intr_pending, |
820 | .reset_mask = gv100_mc_reset_mask, | ||
821 | .is_enabled = gm20b_mc_is_enabled, | ||
820 | }, | 822 | }, |
821 | .debug = { | 823 | .debug = { |
822 | .show_dump = gk20a_debug_show_dump, | 824 | .show_dump = gk20a_debug_show_dump, |
diff --git a/drivers/gpu/nvgpu/gv100/nvlink_gv100.c b/drivers/gpu/nvgpu/gv100/nvlink_gv100.c index 7bbac293..822ca6b4 100644 --- a/drivers/gpu/nvgpu/gv100/nvlink_gv100.c +++ b/drivers/gpu/nvgpu/gv100/nvlink_gv100.c | |||
@@ -45,8 +45,6 @@ | |||
45 | #include <nvgpu/hw/gv100/hw_trim_gv100.h> | 45 | #include <nvgpu/hw/gv100/hw_trim_gv100.h> |
46 | #include <nvgpu/hw/gv100/hw_nvtlc_gv100.h> | 46 | #include <nvgpu/hw/gv100/hw_nvtlc_gv100.h> |
47 | 47 | ||
48 | #include <nvgpu/hw/gv100/hw_mc_gv100.h> | ||
49 | |||
50 | #define NVLINK_PLL_ON_TIMEOUT_MS 30 | 48 | #define NVLINK_PLL_ON_TIMEOUT_MS 30 |
51 | #define NVLINK_SUBLINK_TIMEOUT_MS 200 | 49 | #define NVLINK_SUBLINK_TIMEOUT_MS 200 |
52 | /* | 50 | /* |
diff --git a/drivers/gpu/nvgpu/gv11b/css_gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/css_gr_gv11b.c index 1191dad3..b9278a01 100644 --- a/drivers/gpu/nvgpu/gv11b/css_gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/css_gr_gv11b.c | |||
@@ -37,12 +37,12 @@ | |||
37 | #include <nvgpu/utils.h> | 37 | #include <nvgpu/utils.h> |
38 | #include <nvgpu/gk20a.h> | 38 | #include <nvgpu/gk20a.h> |
39 | #include <nvgpu/channel.h> | 39 | #include <nvgpu/channel.h> |
40 | #include <nvgpu/unit.h> | ||
40 | 41 | ||
41 | #include "gk20a/css_gr_gk20a.h" | 42 | #include "gk20a/css_gr_gk20a.h" |
42 | #include "css_gr_gv11b.h" | 43 | #include "css_gr_gv11b.h" |
43 | 44 | ||
44 | #include <nvgpu/hw/gv11b/hw_perf_gv11b.h> | 45 | #include <nvgpu/hw/gv11b/hw_perf_gv11b.h> |
45 | #include <nvgpu/hw/gv11b/hw_mc_gv11b.h> | ||
46 | 46 | ||
47 | 47 | ||
48 | /* reports whether the hw queue overflowed */ | 48 | /* reports whether the hw queue overflowed */ |
@@ -65,7 +65,7 @@ static void gv11b_css_hw_reset_streaming(struct gk20a *g) | |||
65 | u32 engine_status; | 65 | u32 engine_status; |
66 | 66 | ||
67 | /* reset the perfmon */ | 67 | /* reset the perfmon */ |
68 | g->ops.mc.reset(g, mc_enable_perfmon_enabled_f()); | 68 | g->ops.mc.reset(g, g->ops.mc.reset_mask(g, NVGPU_UNIT_PERFMON)); |
69 | 69 | ||
70 | /* RBUFEMPTY must be set -- otherwise we'll pick up */ | 70 | /* RBUFEMPTY must be set -- otherwise we'll pick up */ |
71 | /* snapshot that have been queued up from earlier */ | 71 | /* snapshot that have been queued up from earlier */ |
diff --git a/drivers/gpu/nvgpu/gv11b/dbg_gpu_gv11b.c b/drivers/gpu/nvgpu/gv11b/dbg_gpu_gv11b.c index ec6cce55..2b2410eb 100644 --- a/drivers/gpu/nvgpu/gv11b/dbg_gpu_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/dbg_gpu_gv11b.c | |||
@@ -26,10 +26,10 @@ | |||
26 | #include <nvgpu/io.h> | 26 | #include <nvgpu/io.h> |
27 | #include <nvgpu/utils.h> | 27 | #include <nvgpu/utils.h> |
28 | #include <nvgpu/gk20a.h> | 28 | #include <nvgpu/gk20a.h> |
29 | #include <nvgpu/unit.h> | ||
29 | 30 | ||
30 | #include "gv11b/dbg_gpu_gv11b.h" | 31 | #include "gv11b/dbg_gpu_gv11b.h" |
31 | #include <nvgpu/hw/gv11b/hw_perf_gv11b.h> | 32 | #include <nvgpu/hw/gv11b/hw_perf_gv11b.h> |
32 | #include <nvgpu/hw/gv11b/hw_mc_gv11b.h> | ||
33 | #include <nvgpu/bug.h> | 33 | #include <nvgpu/bug.h> |
34 | 34 | ||
35 | static void gv11b_perfbuf_reset_streaming(struct gk20a *g) | 35 | static void gv11b_perfbuf_reset_streaming(struct gk20a *g) |
@@ -37,7 +37,7 @@ static void gv11b_perfbuf_reset_streaming(struct gk20a *g) | |||
37 | u32 engine_status; | 37 | u32 engine_status; |
38 | u32 num_unread_bytes; | 38 | u32 num_unread_bytes; |
39 | 39 | ||
40 | g->ops.mc.reset(g, mc_enable_perfmon_enabled_f()); | 40 | g->ops.mc.reset(g, g->ops.mc.reset_mask(g, NVGPU_UNIT_PERFMON)); |
41 | 41 | ||
42 | engine_status = gk20a_readl(g, perf_pmasys_enginestatus_r()); | 42 | engine_status = gk20a_readl(g, perf_pmasys_enginestatus_r()); |
43 | WARN_ON(0u == | 43 | WARN_ON(0u == |
diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index fa1836c8..34e9cd5f 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | |||
@@ -41,6 +41,7 @@ | |||
41 | #include <nvgpu/utils.h> | 41 | #include <nvgpu/utils.h> |
42 | #include <nvgpu/gk20a.h> | 42 | #include <nvgpu/gk20a.h> |
43 | #include <nvgpu/channel.h> | 43 | #include <nvgpu/channel.h> |
44 | #include <nvgpu/unit.h> | ||
44 | 45 | ||
45 | #include "gk20a/fifo_gk20a.h" | 46 | #include "gk20a/fifo_gk20a.h" |
46 | 47 | ||
@@ -53,7 +54,6 @@ | |||
53 | #include <nvgpu/hw/gv11b/hw_usermode_gv11b.h> | 54 | #include <nvgpu/hw/gv11b/hw_usermode_gv11b.h> |
54 | #include <nvgpu/hw/gv11b/hw_top_gv11b.h> | 55 | #include <nvgpu/hw/gv11b/hw_top_gv11b.h> |
55 | #include <nvgpu/hw/gv11b/hw_gmmu_gv11b.h> | 56 | #include <nvgpu/hw/gv11b/hw_gmmu_gv11b.h> |
56 | #include <nvgpu/hw/gv11b/hw_mc_gv11b.h> | ||
57 | #include <nvgpu/hw/gv11b/hw_gr_gv11b.h> | 57 | #include <nvgpu/hw/gv11b/hw_gr_gv11b.h> |
58 | 58 | ||
59 | #include "fifo_gv11b.h" | 59 | #include "fifo_gv11b.h" |
@@ -1281,7 +1281,7 @@ int gv11b_init_fifo_reset_enable_hw(struct gk20a *g) | |||
1281 | nvgpu_log_fn(g, " "); | 1281 | nvgpu_log_fn(g, " "); |
1282 | 1282 | ||
1283 | /* enable pmc pfifo */ | 1283 | /* enable pmc pfifo */ |
1284 | g->ops.mc.reset(g, mc_enable_pfifo_enabled_f()); | 1284 | g->ops.mc.reset(g, g->ops.mc.reset_mask(g, NVGPU_UNIT_FIFO)); |
1285 | 1285 | ||
1286 | if (g->ops.clock_gating.slcg_ce2_load_gating_prod) { | 1286 | if (g->ops.clock_gating.slcg_ce2_load_gating_prod) { |
1287 | g->ops.clock_gating.slcg_ce2_load_gating_prod(g, | 1287 | g->ops.clock_gating.slcg_ce2_load_gating_prod(g, |
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index a79071b7..42969805 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c | |||
@@ -759,6 +759,8 @@ static const struct gpu_ops gv11b_ops = { | |||
759 | .is_intr_hub_pending = gv11b_mc_is_intr_hub_pending, | 759 | .is_intr_hub_pending = gv11b_mc_is_intr_hub_pending, |
760 | .is_stall_and_eng_intr_pending = | 760 | .is_stall_and_eng_intr_pending = |
761 | gv11b_mc_is_stall_and_eng_intr_pending, | 761 | gv11b_mc_is_stall_and_eng_intr_pending, |
762 | .reset_mask = gm20b_mc_reset_mask, | ||
763 | .is_enabled = gm20b_mc_is_enabled, | ||
762 | }, | 764 | }, |
763 | .debug = { | 765 | .debug = { |
764 | .show_dump = gk20a_debug_show_dump, | 766 | .show_dump = gk20a_debug_show_dump, |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index 8627fddd..5a9c56e0 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h | |||
@@ -1156,7 +1156,7 @@ struct gpu_ops { | |||
1156 | void (*intr_mask)(struct gk20a *g); | 1156 | void (*intr_mask)(struct gk20a *g); |
1157 | void (*intr_enable)(struct gk20a *g); | 1157 | void (*intr_enable)(struct gk20a *g); |
1158 | void (*intr_unit_config)(struct gk20a *g, | 1158 | void (*intr_unit_config)(struct gk20a *g, |
1159 | bool enable, bool is_stalling, u32 unit); | 1159 | bool enable, bool is_stalling, u32 mask); |
1160 | void (*isr_stall)(struct gk20a *g); | 1160 | void (*isr_stall)(struct gk20a *g); |
1161 | bool (*is_intr_hub_pending)(struct gk20a *g, u32 mc_intr); | 1161 | bool (*is_intr_hub_pending)(struct gk20a *g, u32 mc_intr); |
1162 | bool (*is_intr_nvlink_pending)(struct gk20a *g, u32 mc_intr); | 1162 | bool (*is_intr_nvlink_pending)(struct gk20a *g, u32 mc_intr); |
@@ -1172,9 +1172,11 @@ struct gpu_ops { | |||
1172 | void (*enable)(struct gk20a *g, u32 units); | 1172 | void (*enable)(struct gk20a *g, u32 units); |
1173 | void (*disable)(struct gk20a *g, u32 units); | 1173 | void (*disable)(struct gk20a *g, u32 units); |
1174 | void (*reset)(struct gk20a *g, u32 units); | 1174 | void (*reset)(struct gk20a *g, u32 units); |
1175 | bool (*is_enabled)(struct gk20a *g, enum nvgpu_unit unit); | ||
1175 | bool (*is_intr1_pending)(struct gk20a *g, enum nvgpu_unit unit, u32 mc_intr_1); | 1176 | bool (*is_intr1_pending)(struct gk20a *g, enum nvgpu_unit unit, u32 mc_intr_1); |
1176 | void (*log_pending_intrs)(struct gk20a *g); | 1177 | void (*log_pending_intrs)(struct gk20a *g); |
1177 | void (*fbpa_isr)(struct gk20a *g); | 1178 | void (*fbpa_isr)(struct gk20a *g); |
1179 | u32 (*reset_mask)(struct gk20a *g, enum nvgpu_unit unit); | ||
1178 | } mc; | 1180 | } mc; |
1179 | struct { | 1181 | struct { |
1180 | void (*show_dump)(struct gk20a *g, | 1182 | void (*show_dump)(struct gk20a *g, |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/unit.h b/drivers/gpu/nvgpu/include/nvgpu/unit.h index f919392e..11df652a 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/unit.h +++ b/drivers/gpu/nvgpu/include/nvgpu/unit.h | |||
@@ -31,6 +31,11 @@ | |||
31 | */ | 31 | */ |
32 | enum nvgpu_unit { | 32 | enum nvgpu_unit { |
33 | NVGPU_UNIT_FIFO, | 33 | NVGPU_UNIT_FIFO, |
34 | NVGPU_UNIT_PERFMON, | ||
35 | NVGPU_UNIT_GRAPH, | ||
36 | NVGPU_UNIT_BLG, | ||
37 | NVGPU_UNIT_PWR, | ||
38 | NVGPU_UNIT_NVDEC, | ||
34 | }; | 39 | }; |
35 | 40 | ||
36 | #endif /* NVGPU_UNIT_H */ | 41 | #endif /* NVGPU_UNIT_H */ |
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c index 2b4b3463..61ab3b1b 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c | |||
@@ -493,6 +493,9 @@ static const struct gpu_ops vgpu_gp10b_ops = { | |||
493 | .reset = NULL, | 493 | .reset = NULL, |
494 | .is_intr1_pending = NULL, | 494 | .is_intr1_pending = NULL, |
495 | .log_pending_intrs = NULL, | 495 | .log_pending_intrs = NULL, |
496 | .reset_mask = NULL, | ||
497 | .is_enabled = NULL, | ||
498 | .fb_reset = NULL, | ||
496 | }, | 499 | }, |
497 | .debug = { | 500 | .debug = { |
498 | .show_dump = NULL, | 501 | .show_dump = NULL, |
diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c index c0e1b1bb..a024a0ea 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | |||
@@ -566,6 +566,9 @@ static const struct gpu_ops vgpu_gv11b_ops = { | |||
566 | .is_intr1_pending = NULL, | 566 | .is_intr1_pending = NULL, |
567 | .is_intr_hub_pending = NULL, | 567 | .is_intr_hub_pending = NULL, |
568 | .log_pending_intrs = NULL , | 568 | .log_pending_intrs = NULL , |
569 | .reset_mask = NULL, | ||
570 | .is_enabled = NULL, | ||
571 | .fb_reset = NULL, | ||
569 | }, | 572 | }, |
570 | .debug = { | 573 | .debug = { |
571 | .show_dump = NULL, | 574 | .show_dump = NULL, |