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-rw-r--r-- | include/linux/tegra_vgpu.h | 241 |
1 files changed, 241 insertions, 0 deletions
diff --git a/include/linux/tegra_vgpu.h b/include/linux/tegra_vgpu.h new file mode 100644 index 00000000..93cb3b11 --- /dev/null +++ b/include/linux/tegra_vgpu.h | |||
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1 | /* | ||
2 | * Tegra GPU Virtualization Interfaces to Server | ||
3 | * | ||
4 | * Copyright (c) 2014, NVIDIA Corporation. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms and conditions of the GNU General Public License, | ||
8 | * version 2, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | * | ||
15 | * You should have received a copy of the GNU General Public License | ||
16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
17 | */ | ||
18 | |||
19 | #ifndef __TEGRA_VGPU_H | ||
20 | #define __TEGRA_VGPU_H | ||
21 | |||
22 | enum { | ||
23 | TEGRA_VGPU_MODULE_GPU = 0, | ||
24 | }; | ||
25 | |||
26 | enum { | ||
27 | TEGRA_VGPU_QUEUE_CMD = 2, | ||
28 | TEGRA_VGPU_QUEUE_INTR | ||
29 | }; | ||
30 | |||
31 | enum { | ||
32 | TEGRA_VGPU_CMD_CONNECT = 0, | ||
33 | TEGRA_VGPU_CMD_DISCONNECT, | ||
34 | TEGRA_VGPU_CMD_ABORT, | ||
35 | TEGRA_VGPU_CMD_CHANNEL_ALLOC_HWCTX, | ||
36 | TEGRA_VGPU_CMD_CHANNEL_FREE_HWCTX, | ||
37 | TEGRA_VGPU_CMD_GET_ATTRIBUTE, | ||
38 | TEGRA_VGPU_CMD_MAP_BAR1, | ||
39 | TEGRA_VGPU_CMD_AS_ALLOC_SHARE, | ||
40 | TEGRA_VGPU_CMD_AS_BIND_SHARE, | ||
41 | TEGRA_VGPU_CMD_AS_FREE_SHARE, | ||
42 | TEGRA_VGPU_CMD_AS_MAP, | ||
43 | TEGRA_VGPU_CMD_AS_UNMAP, | ||
44 | TEGRA_VGPU_CMD_AS_INVALIDATE, | ||
45 | TEGRA_VGPU_CMD_CHANNEL_BIND, | ||
46 | TEGRA_VGPU_CMD_CHANNEL_UNBIND, | ||
47 | TEGRA_VGPU_CMD_CHANNEL_DISABLE, | ||
48 | TEGRA_VGPU_CMD_CHANNEL_PREEMPT, | ||
49 | TEGRA_VGPU_CMD_CHANNEL_SETUP_RAMFC, | ||
50 | TEGRA_VGPU_CMD_CHANNEL_ALLOC_GR_CTX, | ||
51 | TEGRA_VGPU_CMD_CHANNEL_FREE_GR_CTX, | ||
52 | TEGRA_VGPU_CMD_CHANNEL_COMMIT_GR_CTX, | ||
53 | TEGRA_VGPU_CMD_CHANNEL_ALLOC_GR_PATCH_CTX, | ||
54 | TEGRA_VGPU_CMD_CHANNEL_FREE_GR_PATCH_CTX, | ||
55 | TEGRA_VGPU_CMD_CHANNEL_MAP_GR_GLOBAL_CTX, | ||
56 | TEGRA_VGPU_CMD_CHANNEL_UNMAP_GR_GLOBAL_CTX, | ||
57 | TEGRA_VGPU_CMD_CHANNEL_COMMIT_GR_GLOBAL_CTX, | ||
58 | TEGRA_VGPU_CMD_CHANNEL_LOAD_GR_GOLDEN_CTX, | ||
59 | TEGRA_VGPU_CMD_CHANNEL_BIND_ZCULL, | ||
60 | TEGRA_VGPU_CMD_CACHE_MAINT, | ||
61 | TEGRA_VGPU_CMD_SUBMIT_RUNLIST, | ||
62 | TEGRA_VGPU_CMD_GET_ZCULL_INFO | ||
63 | }; | ||
64 | |||
65 | struct tegra_vgpu_connect_params { | ||
66 | u32 module; | ||
67 | u64 handle; | ||
68 | }; | ||
69 | |||
70 | struct tegra_vgpu_channel_hwctx_params { | ||
71 | u32 id; | ||
72 | u64 handle; | ||
73 | }; | ||
74 | |||
75 | enum { | ||
76 | TEGRA_VGPU_ATTRIB_NUM_CHANNELS = 0, | ||
77 | TEGRA_VGPU_ATTRIB_GOLDEN_CTX_SIZE, | ||
78 | TEGRA_VGPU_ATTRIB_ZCULL_CTX_SIZE, | ||
79 | TEGRA_VGPU_ATTRIB_COMPTAG_LINES, | ||
80 | TEGRA_VGPU_ATTRIB_GPC_COUNT, | ||
81 | TEGRA_VGPU_ATTRIB_MAX_TPC_PER_GPC_COUNT, | ||
82 | TEGRA_VGPU_ATTRIB_MAX_TPC_COUNT, | ||
83 | TEGRA_VGPU_ATTRIB_PMC_BOOT_0, | ||
84 | TEGRA_VGPU_ATTRIB_L2_SIZE | ||
85 | }; | ||
86 | |||
87 | struct tegra_vgpu_attrib_params { | ||
88 | u32 attrib; | ||
89 | u32 value; | ||
90 | }; | ||
91 | |||
92 | struct tegra_vgpu_as_share_params { | ||
93 | u64 size; | ||
94 | u64 handle; | ||
95 | }; | ||
96 | |||
97 | struct tegra_vgpu_as_bind_share_params { | ||
98 | u64 as_handle; | ||
99 | u64 chan_handle; | ||
100 | }; | ||
101 | |||
102 | enum { | ||
103 | TEGRA_VGPU_MAP_PROT_NONE = 0, | ||
104 | TEGRA_VGPU_MAP_PROT_READ_ONLY, | ||
105 | TEGRA_VGPU_MAP_PROT_WRITE_ONLY | ||
106 | }; | ||
107 | |||
108 | struct tegra_vgpu_as_map_params { | ||
109 | u64 handle; | ||
110 | u64 addr; | ||
111 | u64 gpu_va; | ||
112 | u64 size; | ||
113 | u8 pgsz_idx; | ||
114 | u8 iova; | ||
115 | u8 kind; | ||
116 | u8 cacheable; | ||
117 | u8 clear_ctags; | ||
118 | u8 prot; | ||
119 | u32 ctag_offset; | ||
120 | }; | ||
121 | |||
122 | struct tegra_vgpu_as_invalidate_params { | ||
123 | u64 handle; | ||
124 | }; | ||
125 | |||
126 | struct tegra_vgpu_channel_config_params { | ||
127 | u64 handle; | ||
128 | }; | ||
129 | |||
130 | struct tegra_vgpu_ramfc_params { | ||
131 | u64 handle; | ||
132 | u64 gpfifo_va; | ||
133 | u32 num_entries; | ||
134 | u64 userd_addr; | ||
135 | u8 iova; | ||
136 | }; | ||
137 | |||
138 | struct tegra_vgpu_gr_ctx_params { | ||
139 | u64 handle; | ||
140 | u64 gr_ctx_va; | ||
141 | u64 patch_ctx_va; | ||
142 | u64 cb_va; | ||
143 | u64 attr_va; | ||
144 | u64 page_pool_va; | ||
145 | u64 priv_access_map_va; | ||
146 | u32 class_num; | ||
147 | }; | ||
148 | |||
149 | struct tegra_vgpu_zcull_bind_params { | ||
150 | u64 handle; | ||
151 | u64 zcull_va; | ||
152 | u32 mode; | ||
153 | }; | ||
154 | |||
155 | enum { | ||
156 | TEGRA_VGPU_L2_MAINT_FLUSH = 0, | ||
157 | TEGRA_VGPU_L2_MAINT_INV, | ||
158 | TEGRA_VGPU_L2_MAINT_FLUSH_INV, | ||
159 | TEGRA_VGPU_FB_FLUSH | ||
160 | }; | ||
161 | |||
162 | struct tegra_vgpu_cache_maint_params { | ||
163 | u8 op; | ||
164 | }; | ||
165 | |||
166 | struct tegra_vgpu_runlist_params { | ||
167 | u8 runlist_id; | ||
168 | u32 num_entries; | ||
169 | }; | ||
170 | |||
171 | struct tegra_vgpu_golden_ctx_params { | ||
172 | u32 size; | ||
173 | }; | ||
174 | |||
175 | struct tegra_vgpu_zcull_info_params { | ||
176 | u32 width_align_pixels; | ||
177 | u32 height_align_pixels; | ||
178 | u32 pixel_squares_by_aliquots; | ||
179 | u32 aliquot_total; | ||
180 | u32 region_byte_multiplier; | ||
181 | u32 region_header_size; | ||
182 | u32 subregion_header_size; | ||
183 | u32 subregion_width_align_pixels; | ||
184 | u32 subregion_height_align_pixels; | ||
185 | u32 subregion_count; | ||
186 | }; | ||
187 | |||
188 | struct tegra_vgpu_cmd_msg { | ||
189 | u32 cmd; | ||
190 | int ret; | ||
191 | u64 handle; | ||
192 | union { | ||
193 | struct tegra_vgpu_connect_params connect; | ||
194 | struct tegra_vgpu_channel_hwctx_params channel_hwctx; | ||
195 | struct tegra_vgpu_attrib_params attrib; | ||
196 | struct tegra_vgpu_as_share_params as_share; | ||
197 | struct tegra_vgpu_as_bind_share_params as_bind_share; | ||
198 | struct tegra_vgpu_as_map_params as_map; | ||
199 | struct tegra_vgpu_as_invalidate_params as_invalidate; | ||
200 | struct tegra_vgpu_channel_config_params channel_config; | ||
201 | struct tegra_vgpu_ramfc_params ramfc; | ||
202 | struct tegra_vgpu_gr_ctx_params gr_ctx; | ||
203 | struct tegra_vgpu_zcull_bind_params zcull_bind; | ||
204 | struct tegra_vgpu_cache_maint_params cache_maint; | ||
205 | struct tegra_vgpu_runlist_params runlist; | ||
206 | struct tegra_vgpu_golden_ctx_params golden_ctx; | ||
207 | struct tegra_vgpu_zcull_info_params zcull_info; | ||
208 | } params; | ||
209 | }; | ||
210 | |||
211 | enum { | ||
212 | TEGRA_VGPU_GR_INTR_NOTIFY = 0 | ||
213 | }; | ||
214 | |||
215 | struct tegra_vgpu_gr_intr_info { | ||
216 | u32 type; | ||
217 | u32 chid; | ||
218 | }; | ||
219 | |||
220 | enum { | ||
221 | TEGRA_VGPU_INTR_GR = 0 | ||
222 | }; | ||
223 | |||
224 | enum { | ||
225 | TEGRA_VGPU_EVENT_INTR = 0, | ||
226 | TEGRA_VGPU_EVENT_ABORT | ||
227 | }; | ||
228 | |||
229 | struct tegra_vgpu_intr_msg { | ||
230 | unsigned int event; | ||
231 | u32 unit; | ||
232 | union { | ||
233 | struct tegra_vgpu_gr_intr_info gr_intr; | ||
234 | } info; | ||
235 | }; | ||
236 | |||
237 | #define TEGRA_VGPU_QUEUE_SIZES \ | ||
238 | 512, \ | ||
239 | sizeof(struct tegra_vgpu_intr_msg) | ||
240 | |||
241 | #endif | ||