5 files changed, 289 insertions, 23 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index aeed5838..05ed9270 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -217,6 +217,14 @@ struct gpu_ops {
                                 struct pmu_sequence *seq);
                 void (*set_pmu_cmdline_args_secure_mode)(struct pmu_gk20a *pmu,
                         u32 val);
+                u32 (*get_perfmon_cntr_sz)(struct pmu_gk20a *pmu);
+                void * (*get_perfmon_cntr_ptr)(struct pmu_gk20a *pmu);
+                void (*set_perfmon_cntr_ut)(struct pmu_gk20a *pmu, u16 ut);
+                void (*set_perfmon_cntr_lt)(struct pmu_gk20a *pmu, u16 lt);
+                void (*set_perfmon_cntr_valid)(struct pmu_gk20a *pmu, u8 val);
+                void (*set_perfmon_cntr_index)(struct pmu_gk20a *pmu, u8 val);
+                void (*set_perfmon_cntr_group_id)(struct pmu_gk20a *pmu,
+                                u8 gid);
         } pmu_ver;
         struct {
                 int (*get_netlist_name)(int index, char *name);
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
index c23d83cf..b147c66f 100644
--- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
@@ -44,6 +44,76 @@ static void ap_callback_init_and_enable_ctrl(
                 struct gk20a *g, struct pmu_msg *msg,
                 void *param, u32 seq_desc, u32 status);
 
+static u32 pmu_perfmon_cntr_sz_v0(struct pmu_gk20a *pmu)
+{
+        return sizeof(struct pmu_perfmon_counter_v0);
+}
+
+static u32 pmu_perfmon_cntr_sz_v2(struct pmu_gk20a *pmu)
+{
+        return sizeof(struct pmu_perfmon_counter_v2);
+}
+
+static void *get_perfmon_cntr_ptr_v2(struct pmu_gk20a *pmu)
+{
+        return (void *)(&pmu->perfmon_counter_v2);
+}
+
+static void *get_perfmon_cntr_ptr_v0(struct pmu_gk20a *pmu)
+{
+        return (void *)(&pmu->perfmon_counter_v0);
+}
+
+static void set_perfmon_cntr_ut_v2(struct pmu_gk20a *pmu, u16 ut)
+{
+        pmu->perfmon_counter_v2.upper_threshold = ut;
+}
+
+static void set_perfmon_cntr_ut_v0(struct pmu_gk20a *pmu, u16 ut)
+{
+        pmu->perfmon_counter_v0.upper_threshold = ut;
+}
+
+static void set_perfmon_cntr_lt_v2(struct pmu_gk20a *pmu, u16 lt)
+{
+        pmu->perfmon_counter_v2.lower_threshold = lt;
+}
+
+static void set_perfmon_cntr_lt_v0(struct pmu_gk20a *pmu, u16 lt)
+{
+        pmu->perfmon_counter_v0.lower_threshold = lt;
+}
+
+static void set_perfmon_cntr_valid_v2(struct pmu_gk20a *pmu, u8 valid)
+{
+        pmu->perfmon_counter_v2.valid = valid;
+}
+
+static void set_perfmon_cntr_valid_v0(struct pmu_gk20a *pmu, u8 valid)
+{
+        pmu->perfmon_counter_v0.valid = valid;
+}
+
+static void set_perfmon_cntr_index_v2(struct pmu_gk20a *pmu, u8 index)
+{
+        pmu->perfmon_counter_v2.index = index;
+}
+
+static void set_perfmon_cntr_index_v0(struct pmu_gk20a *pmu, u8 index)
+{
+        pmu->perfmon_counter_v0.index = index;
+}
+
+static void set_perfmon_cntr_group_id_v2(struct pmu_gk20a *pmu, u8 gid)
+{
+        pmu->perfmon_counter_v2.group_id = gid;
+}
+
+static void set_perfmon_cntr_group_id_v0(struct pmu_gk20a *pmu, u8 gid)
+{
+        pmu->perfmon_counter_v0.group_id = gid;
+}
+
 static u32 pmu_cmdline_size_v0(struct pmu_gk20a *pmu)
 {
         return sizeof(struct pmu_cmdline_args_v0);
@@ -54,6 +124,37 @@ static u32 pmu_cmdline_size_v1(struct pmu_gk20a *pmu)
         return sizeof(struct pmu_cmdline_args_v1);
 }
 
+static u32 pmu_cmdline_size_v2(struct pmu_gk20a *pmu)
+{
+        return sizeof(struct pmu_cmdline_args_v2);
+}
+
+static void set_pmu_cmdline_args_cpufreq_v2(struct pmu_gk20a *pmu, u32 freq)
+{
+        pmu->args_v2.cpu_freq_hz = freq;
+}
+static void set_pmu_cmdline_args_secure_mode_v2(struct pmu_gk20a *pmu, u32 val)
+{
+        pmu->args_v2.secure_mode = val;
+}
+
+static void set_pmu_cmdline_args_falctracesize_v2(
+                        struct pmu_gk20a *pmu, u32 size)
+{
+        pmu->args_v2.falc_trace_size = size;
+}
+
+static void set_pmu_cmdline_args_falctracedmabase_v2(struct pmu_gk20a *pmu)
+{
+        pmu->args_v2.falc_trace_dma_base = ((u32)pmu->trace_buf.pmu_va)/0x100;
+}
+
+static void set_pmu_cmdline_args_falctracedmaidx_v2(
+                        struct pmu_gk20a *pmu, u32 idx)
+{
+        pmu->args_v2.falc_trace_dma_idx = idx;
+}
+
 static void set_pmu_cmdline_args_cpufreq_v1(struct pmu_gk20a *pmu, u32 freq)
 {
         pmu->args_v1.cpu_freq_hz = freq;
@@ -69,6 +170,7 @@ static void set_pmu_cmdline_args_falctracesize_v1(
         pmu->args_v1.falc_trace_size = size;
 }
 
+
 void printtrace(struct pmu_gk20a *pmu)
 {
         u32 i = 0, j = 0;
@@ -108,6 +210,11 @@ static void set_pmu_cmdline_args_cpufreq_v0(struct pmu_gk20a *pmu, u32 freq)
         pmu->args_v0.cpu_freq_hz = freq;
 }
 
+static void *get_pmu_cmdline_args_ptr_v2(struct pmu_gk20a *pmu)
+{
+        return (void *)(&pmu->args_v2);
+}
+
 static void *get_pmu_cmdline_args_ptr_v1(struct pmu_gk20a *pmu)
 {
         return (void *)(&pmu->args_v1);
@@ -525,6 +632,7 @@ static void *get_pmu_sequence_out_alloc_ptr_v0(struct pmu_sequence *seq)
 int gk20a_init_pmu(struct pmu_gk20a *pmu)
 {
         struct gk20a *g = gk20a_from_pmu(pmu);
+        struct pmu_v *pv = &g->ops.pmu_ver;
 
         mutex_init(&pmu->elpg_mutex);
         mutex_init(&pmu->isr_mutex);
@@ -532,17 +640,107 @@ int gk20a_init_pmu(struct pmu_gk20a *pmu)
         mutex_init(&pmu->pmu_copy_lock);
         mutex_init(&pmu->pmu_seq_lock);
 
-        pmu->perfmon_counter.index = 3; /* GR & CE2 */
-        pmu->perfmon_counter.group_id = PMU_DOMAIN_GROUP_PSTATE;
-
         pmu->remove_support = gk20a_remove_pmu_support;
 
         switch (pmu->desc->app_version) {
+        case APP_VERSION_GM20B_2:
+                g->ops.pmu_ver.get_perfmon_cntr_ptr = get_perfmon_cntr_ptr_v2;
+                g->ops.pmu_ver.set_perfmon_cntr_ut = set_perfmon_cntr_ut_v2;
+                g->ops.pmu_ver.set_perfmon_cntr_lt = set_perfmon_cntr_lt_v2;
+                g->ops.pmu_ver.set_perfmon_cntr_valid =
+                        set_perfmon_cntr_valid_v2;
+                g->ops.pmu_ver.set_perfmon_cntr_index =
+                        set_perfmon_cntr_index_v2;
+                g->ops.pmu_ver.set_perfmon_cntr_group_id =
+                        set_perfmon_cntr_group_id_v2;
+                g->ops.pmu_ver.get_perfmon_cntr_sz = pmu_perfmon_cntr_sz_v2;
+                g->ops.pmu_ver.cmd_id_zbc_table_update = 16;
+                g->ops.pmu_ver.get_pmu_cmdline_args_size =
+                        pmu_cmdline_size_v2;
+                g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq =
+                        set_pmu_cmdline_args_cpufreq_v2;
+                g->ops.pmu_ver.set_pmu_cmdline_args_secure_mode =
+                        set_pmu_cmdline_args_secure_mode_v2;
+                g->ops.pmu_ver.set_pmu_cmdline_args_trace_size =
+                        set_pmu_cmdline_args_falctracesize_v2;
+                g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_base =
+                        set_pmu_cmdline_args_falctracedmabase_v2;
+                g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_idx =
+                        set_pmu_cmdline_args_falctracedmaidx_v2;
+                g->ops.pmu_ver.get_pmu_cmdline_args_ptr =
+                        get_pmu_cmdline_args_ptr_v2;
+                g->ops.pmu_ver.get_pmu_allocation_struct_size =
+                        get_pmu_allocation_size_v1;
+                g->ops.pmu_ver.set_pmu_allocation_ptr =
+                        set_pmu_allocation_ptr_v1;
+                g->ops.pmu_ver.pmu_allocation_set_dmem_size =
+                        pmu_allocation_set_dmem_size_v1;
+                g->ops.pmu_ver.pmu_allocation_get_dmem_size =
+                        pmu_allocation_get_dmem_size_v1;
+                g->ops.pmu_ver.pmu_allocation_get_dmem_offset =
+                        pmu_allocation_get_dmem_offset_v1;
+                g->ops.pmu_ver.pmu_allocation_get_dmem_offset_addr =
+                        pmu_allocation_get_dmem_offset_addr_v1;
+                g->ops.pmu_ver.pmu_allocation_set_dmem_offset =
+                        pmu_allocation_set_dmem_offset_v1;
+                g->ops.pmu_ver.get_pmu_init_msg_pmu_queue_params =
+                        get_pmu_init_msg_pmu_queue_params_v1;
+                g->ops.pmu_ver.get_pmu_msg_pmu_init_msg_ptr =
+                        get_pmu_msg_pmu_init_msg_ptr_v1;
+                g->ops.pmu_ver.get_pmu_init_msg_pmu_sw_mg_off =
+                        get_pmu_init_msg_pmu_sw_mg_off_v1;
+                g->ops.pmu_ver.get_pmu_init_msg_pmu_sw_mg_size =
+                        get_pmu_init_msg_pmu_sw_mg_size_v1;
+                g->ops.pmu_ver.get_pmu_perfmon_cmd_start_size =
+                        get_pmu_perfmon_cmd_start_size_v1;
+                g->ops.pmu_ver.get_perfmon_cmd_start_offsetofvar =
+                        get_perfmon_cmd_start_offsetofvar_v1;
+                g->ops.pmu_ver.perfmon_start_set_cmd_type =
+                        perfmon_start_set_cmd_type_v1;
+                g->ops.pmu_ver.perfmon_start_set_group_id =
+                        perfmon_start_set_group_id_v1;
+                g->ops.pmu_ver.perfmon_start_set_state_id =
+                        perfmon_start_set_state_id_v1;
+                g->ops.pmu_ver.perfmon_start_set_flags =
+                        perfmon_start_set_flags_v1;
+                g->ops.pmu_ver.perfmon_start_get_flags =
+                        perfmon_start_get_flags_v1;
+                g->ops.pmu_ver.get_pmu_perfmon_cmd_init_size =
+                        get_pmu_perfmon_cmd_init_size_v1;
+                g->ops.pmu_ver.get_perfmon_cmd_init_offsetofvar =
+                        get_perfmon_cmd_init_offsetofvar_v1;
+                g->ops.pmu_ver.perfmon_cmd_init_set_sample_buffer =
+                        perfmon_cmd_init_set_sample_buffer_v1;
+                g->ops.pmu_ver.perfmon_cmd_init_set_dec_cnt =
+                        perfmon_cmd_init_set_dec_cnt_v1;
+                g->ops.pmu_ver.perfmon_cmd_init_set_base_cnt_id =
+                        perfmon_cmd_init_set_base_cnt_id_v1;
+                g->ops.pmu_ver.perfmon_cmd_init_set_samp_period_us =
+                        perfmon_cmd_init_set_samp_period_us_v1;
+                g->ops.pmu_ver.perfmon_cmd_init_set_num_cnt =
+                        perfmon_cmd_init_set_num_cnt_v1;
+                g->ops.pmu_ver.perfmon_cmd_init_set_mov_avg =
+                        perfmon_cmd_init_set_mov_avg_v1;
+                g->ops.pmu_ver.get_pmu_seq_in_a_ptr =
+                        get_pmu_sequence_in_alloc_ptr_v1;
+                g->ops.pmu_ver.get_pmu_seq_out_a_ptr =
+                        get_pmu_sequence_out_alloc_ptr_v1;
+                break;
         case APP_VERSION_GM20B_1:
         case APP_VERSION_GM20B:
         case APP_VERSION_1:
         case APP_VERSION_2:
                 g->ops.pmu_ver.cmd_id_zbc_table_update = 16;
+                g->ops.pmu_ver.get_perfmon_cntr_ptr = get_perfmon_cntr_ptr_v0;
+                g->ops.pmu_ver.set_perfmon_cntr_ut = set_perfmon_cntr_ut_v0;
+                g->ops.pmu_ver.set_perfmon_cntr_lt = set_perfmon_cntr_lt_v0;
+                g->ops.pmu_ver.set_perfmon_cntr_valid =
+                        set_perfmon_cntr_valid_v0;
+                g->ops.pmu_ver.set_perfmon_cntr_index =
+                        set_perfmon_cntr_index_v0;
+                g->ops.pmu_ver.set_perfmon_cntr_group_id =
+                        set_perfmon_cntr_group_id_v0;
+                g->ops.pmu_ver.get_perfmon_cntr_sz = pmu_perfmon_cntr_sz_v0;
                 g->ops.pmu_ver.get_pmu_cmdline_args_size =
                         pmu_cmdline_size_v1;
                 g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq =
@@ -616,6 +814,16 @@ int gk20a_init_pmu(struct pmu_gk20a *pmu)
                 break;
         case APP_VERSION_0:
                 g->ops.pmu_ver.cmd_id_zbc_table_update = 14;
+                g->ops.pmu_ver.get_perfmon_cntr_ptr = get_perfmon_cntr_ptr_v0;
+                g->ops.pmu_ver.set_perfmon_cntr_ut = set_perfmon_cntr_ut_v0;
+                g->ops.pmu_ver.set_perfmon_cntr_lt = set_perfmon_cntr_lt_v0;
+                g->ops.pmu_ver.set_perfmon_cntr_valid =
+                        set_perfmon_cntr_valid_v0;
+                g->ops.pmu_ver.set_perfmon_cntr_index =
+                        set_perfmon_cntr_index_v0;
+                g->ops.pmu_ver.set_perfmon_cntr_group_id =
+                        set_perfmon_cntr_group_id_v0;
+                g->ops.pmu_ver.get_perfmon_cntr_sz = pmu_perfmon_cntr_sz_v0;
                 g->ops.pmu_ver.get_pmu_cmdline_args_size =
                         pmu_cmdline_size_v0;
                 g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq =
@@ -688,6 +896,9 @@ int gk20a_init_pmu(struct pmu_gk20a *pmu)
                 return -EINVAL;
                 break;
         }
+        pv->set_perfmon_cntr_index(pmu, 3); /* GR & CE2 */
+        pv->set_perfmon_cntr_group_id(pmu, PMU_DOMAIN_GROUP_PSTATE);
+
         return 0;
 }
 
@@ -2336,8 +2547,8 @@ static int pmu_init_perfmon(struct pmu_gk20a *pmu)
         pv->perfmon_cmd_init_set_mov_avg(&cmd.cmd.perfmon, 17);
 
         memset(&payload, 0, sizeof(struct pmu_payload));
-        payload.in.buf = &pmu->perfmon_counter;
-        payload.in.size = sizeof(struct pmu_perfmon_counter);
+        payload.in.buf = pv->get_perfmon_cntr_ptr(pmu);
+        payload.in.size = pv->get_perfmon_cntr_sz(pmu);
         payload.in.offset = pv->get_perfmon_cmd_init_offsetofvar(COUNTER_ALLOC);
 
         gk20a_dbg_pmu("cmd post PMU_PERFMON_CMD_ID_INIT");
@@ -2631,13 +2842,13 @@ static int pmu_perfmon_start_sampling(struct pmu_gk20a *pmu)
         memset(&payload, 0, sizeof(struct pmu_payload));
 
         /* TBD: PMU_PERFMON_PCT_TO_INC * 100 */
-        pmu->perfmon_counter.upper_threshold = 3000; /* 30% */
+        pv->set_perfmon_cntr_ut(pmu, 3000); /* 30% */
         /* TBD: PMU_PERFMON_PCT_TO_DEC * 100 */
-        pmu->perfmon_counter.lower_threshold = 1000; /* 10% */
-        pmu->perfmon_counter.valid = true;
+        pv->set_perfmon_cntr_lt(pmu, 1000); /* 10% */
+        pv->set_perfmon_cntr_valid(pmu, true);
 
-        payload.in.buf = &pmu->perfmon_counter;
-        payload.in.size = sizeof(pmu->perfmon_counter);
+        payload.in.buf = pv->get_perfmon_cntr_ptr(pmu);
+        payload.in.size = pv->get_perfmon_cntr_sz(pmu);
         payload.in.offset =
                 pv->get_perfmon_cmd_start_offsetofvar(COUNTER_ALLOC);
 
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
index 828058b7..292aabb0 100644
--- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
@@ -51,6 +51,7 @@
 /* Mapping between AP_CTRLs and Idle counters */
 #define PMU_AP_IDLE_MASK_GRAPHICS       (PMU_AP_IDLE_MASK_HIST_IDX_1)
 
+#define APP_VERSION_GM20B_2 18694072
 #define APP_VERSION_GM20B_1 18547257
 #define APP_VERSION_GM20B 17615280
 #define APP_VERSION_2 18542378
@@ -339,6 +340,17 @@ struct pmu_cmdline_args_v1 {
         struct pmu_mem_v1 gc6_ctx;              /* dmem offset of gc6 context */
 };
 
+struct pmu_cmdline_args_v2 {
+        u32 cpu_freq_hz;                /* Frequency of the clock driving PMU */
+        u32 falc_trace_size;            /* falctrace buffer size (bytes) */
+        u32 falc_trace_dma_base;        /* 256-byte block address */
+        u32 falc_trace_dma_idx;         /* dmaIdx for DMA operations */
+        u8 secure_mode;
+        u8 raise_priv_sec;     /*Raise priv level required for desired
+                                        registers*/
+        struct pmu_mem_v1 gc6_ctx;              /* dmem offset of gc6 context */
+};
+
 #define GK20A_PMU_TRACE_BUFSIZE     0x4000   /* 4K */
 #define GK20A_PMU_DMEM_BLKSIZE2         8
 
@@ -641,13 +653,23 @@ struct pmu_pg_cmd {
 #define PMU_PERFMON_PCT_TO_INC          58
 #define PMU_PERFMON_PCT_TO_DEC          23
 
-struct pmu_perfmon_counter {
+struct pmu_perfmon_counter_v0 {
+        u8 index;
+        u8 flags;
+        u8 group_id;
+        u8 valid;
+        u16 upper_threshold; /* units of 0.01% */
+        u16 lower_threshold; /* units of 0.01% */
+};
+
+struct pmu_perfmon_counter_v2 {
         u8 index;
         u8 flags;
         u8 group_id;
         u8 valid;
         u16 upper_threshold; /* units of 0.01% */
         u16 lower_threshold; /* units of 0.01% */
+        u32 scale;
 };
 
 #define PMU_PERFMON_FLAG_ENABLE_INCREASE        (0x00000001)
@@ -1044,7 +1066,10 @@ struct pmu_gk20a {
         struct mutex elpg_mutex; /* protect elpg enable/disable */
         int elpg_refcnt; /* disable -1, enable +1, <=0 elpg disabled, > 0 elpg enabled */
 
-        struct pmu_perfmon_counter perfmon_counter;
+        union {
+                struct pmu_perfmon_counter_v2 perfmon_counter_v2;
+                struct pmu_perfmon_counter_v0 perfmon_counter_v0;
+        };
         u32 perfmon_state_id[PMU_DOMAIN_GROUP_NUM];
 
         bool initialized;
@@ -1063,6 +1088,7 @@ struct pmu_gk20a {
         union {
                 struct pmu_cmdline_args_v0 args_v0;
                 struct pmu_cmdline_args_v1 args_v1;
+                struct pmu_cmdline_args_v2 args_v2;
         };
         unsigned long perfmon_events_cnt;
         bool perfmon_sampling_enabled;
diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c
index 77f0653e..e5a3e2cd 100644
--- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c
@@ -80,7 +80,7 @@ static void free_blob_res(struct gk20a *g)
 
 int pmu_ucode_details(struct gk20a *g, struct flcn_ucode_img *p_img)
 {
-        const struct firmware *pmu_fw;
+        const struct firmware *pmu_fw, *pmu_desc;
         struct pmu_gk20a *pmu = &g->pmu;
         struct lsf_ucode_desc *lsf_desc;
         int err;
@@ -93,18 +93,28 @@ int pmu_ucode_details(struct gk20a *g, struct flcn_ucode_img *p_img)
         }
         gm20b_dbg_pmu("Loaded PMU ucode in for blob preparation");
 
-        pmu->desc = (struct pmu_ucode_desc *)pmu_fw->data;
-        pmu->ucode_image = (u32 *)((u8 *)pmu->desc +
-                        pmu->desc->descriptor_size);
+        gm20b_dbg_pmu("requesting PMU ucode desc in GM20B\n");
+        pmu_desc = gk20a_request_firmware(g, GM20B_PMU_UCODE_DESC);
+        if (!pmu_desc) {
+                gk20a_err(dev_from_gk20a(g), "failed to load pmu ucode desc!!");
+                gm20b_dbg_pmu("requesting PMU ucode in GM20B failed\n");
+                err = -ENOENT;
+                goto release_img_fw;
+        }
+        pmu->desc = (struct pmu_ucode_desc *)pmu_desc->data;
+        pmu->ucode_image = (u32 *)pmu_fw->data;
+
         err = gk20a_init_pmu(pmu);
         if (err) {
                 gm20b_dbg_pmu("failed to set function pointers\n");
-                return err;
+                goto release_desc;
         }
 
         lsf_desc = kzalloc(sizeof(struct lsf_ucode_desc), GFP_KERNEL);
-        if (!lsf_desc)
-                return -ENOMEM;
+        if (!lsf_desc) {
+                err = -ENOMEM;
+                goto release_desc;
+        }
         lsf_desc->falcon_id = LSF_FALCON_ID_PMU;
 
         p_img->desc = pmu->desc;
@@ -115,6 +125,11 @@ int pmu_ucode_details(struct gk20a *g, struct flcn_ucode_img *p_img)
         p_img->lsf_desc = (struct lsf_ucode_desc *)lsf_desc;
         gm20b_dbg_pmu("requesting PMU ucode in GM20B exit\n");
         return 0;
+release_desc:
+        release_firmware(pmu_desc);
+release_img_fw:
+        release_firmware(pmu_fw);
+        return err;
 }
 
 int fecs_ucode_details(struct gk20a *g, struct flcn_ucode_img *p_img)
@@ -378,10 +393,8 @@ int pmu_populate_loader_cfg(struct gk20a *g,
         g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq(pmu,
                                 clk_get_rate(platform->clk[1]));
         g->ops.pmu_ver.set_pmu_cmdline_args_secure_mode(pmu, 1);
-        pmu_copy_to_dmem(pmu, addr_args,
-                        (u8 *)(g->ops.pmu_ver.get_pmu_cmdline_args_ptr(pmu)),
-                        g->ops.pmu_ver.get_pmu_cmdline_args_size(pmu), 0);
         *p_bl_gen_desc_size = sizeof(p_bl_gen_desc->loader_cfg);
+        g->acr.pmu_args = addr_args;
         return 0;
 }
 
@@ -1026,7 +1039,10 @@ int gm20b_init_pmu_setup_hw1(struct gk20a *g, struct flcn_bl_dmem_desc *desc,
         int err;
 
         gk20a_dbg_fn("");
+        mutex_lock(&pmu->isr_enable_lock);
         pmu_reset(pmu);
+        pmu->isr_enabled = true;
+        mutex_unlock(&pmu->isr_enable_lock);
 
         /* setup apertures - virtual */
         gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE),
@@ -1045,6 +1061,9 @@ int gm20b_init_pmu_setup_hw1(struct gk20a *g, struct flcn_bl_dmem_desc *desc,
                         pwr_fbif_transcfg_mem_type_physical_f() |
                         pwr_fbif_transcfg_target_noncoherent_sysmem_f());
 
+        pmu_copy_to_dmem(pmu, g->acr.pmu_args,
+                        (u8 *)(g->ops.pmu_ver.get_pmu_cmdline_args_ptr(pmu)),
+                        g->ops.pmu_ver.get_pmu_cmdline_args_size(pmu), 0);
         err = bl_bootstrap(pmu, desc, bl_sz);
         if (err)
                 return err;
diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.h b/drivers/gpu/nvgpu/gm20b/acr_gm20b.h
index 073dc135..b186e489 100644
--- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.h
@@ -24,7 +24,8 @@
 #define MAX_SUPPORTED_LSFM 2 /*PMU, FECS, GPCCS*/
 #define LSF_UCODE_DATA_ALIGNMENT 4096
 
-#define GM20B_PMU_UCODE_IMAGE "gpmu_ucode.bin"
+#define GM20B_PMU_UCODE_IMAGE "gpmu_ucode_image.bin"
+#define GM20B_PMU_UCODE_DESC "gpmu_ucode_desc.bin"
 #define GM20B_HSBIN_PMU_UCODE_IMAGE "acr_ucode.bin"
 #define GM20B_HSBIN_PMU_BL_UCODE_IMAGE "pmu_bl.bin"
 
@@ -363,6 +364,7 @@ struct acr_gm20b {
         struct hsflcn_bl_desc *pmu_hsbl_desc;
         struct bin_hdr *hsbin_hdr;
         struct acr_fw_header *fw_hdr;
+        u32 pmu_args;
 };
 
 void gm20b_init_secure_pmu(struct gpu_ops *gops);