4 files changed, 70 insertions, 2 deletions

diff --git a/drivers/gpu/nvgpu/vgpu/gr_vgpu.c b/drivers/gpu/nvgpu/vgpu/gr_vgpu.c
index f1b498ca..02a5e87e 100644
--- a/drivers/gpu/nvgpu/vgpu/gr_vgpu.c
+++ b/drivers/gpu/nvgpu/vgpu/gr_vgpu.c
@@ -1,7 +1,7 @@
 /*
  * Virtualized GPU Graphics
  *
- * Copyright (c) 2014-2016, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -837,6 +837,9 @@ static void vgpu_remove_gr_support(struct gr_gk20a *gr)
 
         gk20a_comptag_allocator_destroy(&gr->comp_tags);
 
+        kfree(gr->sm_error_states);
+        gr->sm_error_states = NULL;
+
         kfree(gr->gpc_tpc_mask);
         gr->gpc_tpc_mask = NULL;
 
@@ -883,6 +886,14 @@ static int vgpu_gr_init_gr_setup_sw(struct gk20a *g)
 
         mutex_init(&gr->ctx_mutex);
 
+        gr->sm_error_states = kzalloc(
+                        sizeof(struct nvgpu_dbg_gpu_sm_error_state_record) *
+                        gr->no_of_sm, GFP_KERNEL);
+        if (!gr->sm_error_states) {
+                err = -ENOMEM;
+                goto clean_up;
+        }
+
         gr->remove_support = vgpu_remove_gr_support;
         gr->sw_ready = true;
 
@@ -1061,6 +1072,44 @@ static int vgpu_gr_update_hwpm_ctxsw_mode(struct gk20a *g,
         return err ? err : msg.ret;
 }
 
+static int vgpu_gr_clear_sm_error_state(struct gk20a *g,
+                struct channel_gk20a *ch, u32 sm_id)
+{
+        struct gr_gk20a *gr = &g->gr;
+
+        mutex_lock(&g->dbg_sessions_lock);
+        memset(&gr->sm_error_states[sm_id], 0, sizeof(*gr->sm_error_states));
+        mutex_unlock(&g->dbg_sessions_lock);
+
+        return 0;
+}
+
+void vgpu_gr_handle_sm_esr_event(struct gk20a *g,
+                        struct tegra_vgpu_sm_esr_info *info)
+{
+        struct nvgpu_dbg_gpu_sm_error_state_record *sm_error_states;
+
+        if (info->sm_id >= g->gr.no_of_sm) {
+                gk20a_err(g->dev, "invalid smd_id %d / %d",
+                        info->sm_id, g->gr.no_of_sm);
+                return;
+        }
+
+        mutex_lock(&g->dbg_sessions_lock);
+
+        sm_error_states = &g->gr.sm_error_states[info->sm_id];
+
+        sm_error_states->hww_global_esr = info->hww_global_esr;
+        sm_error_states->hww_warp_esr = info->hww_warp_esr;
+        sm_error_states->hww_warp_esr_pc = info->hww_warp_esr_pc;
+        sm_error_states->hww_global_esr_report_mask =
+                                info->hww_global_esr_report_mask;
+        sm_error_states->hww_warp_esr_report_mask =
+                                info->hww_warp_esr_report_mask;
+
+        mutex_unlock(&g->dbg_sessions_lock);
+}
+
 void vgpu_init_gr_ops(struct gpu_ops *gops)
 {
         gops->gr.detect_sm_arch = vgpu_gr_detect_sm_arch;
@@ -1082,5 +1131,6 @@ void vgpu_init_gr_ops(struct gpu_ops *gops)
         gops->gr.set_sm_debug_mode = vgpu_gr_set_sm_debug_mode;
         gops->gr.update_smpc_ctxsw_mode = vgpu_gr_update_smpc_ctxsw_mode;
         gops->gr.update_hwpm_ctxsw_mode = vgpu_gr_update_hwpm_ctxsw_mode;
+        gops->gr.clear_sm_error_state = vgpu_gr_clear_sm_error_state;
         gops->gr.dump_gr_regs = NULL;
 }
diff --git a/drivers/gpu/nvgpu/vgpu/vgpu.c b/drivers/gpu/nvgpu/vgpu/vgpu.c
index da79de9d..c3dba7d1 100644
--- a/drivers/gpu/nvgpu/vgpu/vgpu.c
+++ b/drivers/gpu/nvgpu/vgpu/vgpu.c
@@ -128,6 +128,8 @@ static void vgpu_handle_channel_event(struct gk20a *g,
         }
 }
 
+
+
 static int vgpu_intr_thread(void *dev_id)
 {
         struct gk20a *g = dev_id;
@@ -174,6 +176,9 @@ static int vgpu_intr_thread(void *dev_id)
                 case TEGRA_VGPU_EVENT_CHANNEL:
                         vgpu_handle_channel_event(g, &msg->info.channel_event);
                         break;
+                case TEGRA_VGPU_EVENT_SM_ESR:
+                        vgpu_gr_handle_sm_esr_event(g, &msg->info.sm_esr);
+                        break;
                 default:
                         gk20a_err(g->dev, "unknown event %u", msg->event);
                         break;
diff --git a/drivers/gpu/nvgpu/vgpu/vgpu.h b/drivers/gpu/nvgpu/vgpu/vgpu.h
index 4a7a6b6c..e64b31b4 100644
--- a/drivers/gpu/nvgpu/vgpu/vgpu.h
+++ b/drivers/gpu/nvgpu/vgpu/vgpu.h
@@ -1,7 +1,7 @@
 /*
  * Virtualized GPU Interfaces
  *
- * Copyright (c) 2014-2016, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -73,6 +73,8 @@ int vgpu_gr_alloc_gr_ctx(struct gk20a *g,
                         u32 flags);
 void vgpu_gr_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm,
                         struct gr_ctx_desc *gr_ctx);
+void vgpu_gr_handle_sm_esr_event(struct gk20a *g,
+                        struct tegra_vgpu_sm_esr_info *info);
 int vgpu_gr_init_ctx_state(struct gk20a *g);
 int vgpu_fifo_isr(struct gk20a *g, struct tegra_vgpu_fifo_intr_info *info);
 int vgpu_fifo_nonstall_isr(struct gk20a *g,
diff --git a/include/linux/tegra_vgpu.h b/include/linux/tegra_vgpu.h
index 40f92aec..14449242 100644
--- a/include/linux/tegra_vgpu.h
+++ b/include/linux/tegra_vgpu.h
@@ -560,6 +560,15 @@ struct tegra_vgpu_channel_event_info {
         u32 id; /* channel id or tsg id */
 };
 
+struct tegra_vgpu_sm_esr_info {
+        u32 sm_id;
+        u32 hww_global_esr;
+        u32 hww_warp_esr;
+        u64 hww_warp_esr_pc;
+        u32 hww_global_esr_report_mask;
+        u32 hww_warp_esr_report_mask;
+};
+
 enum {
 
         TEGRA_VGPU_INTR_GR = 0,
@@ -575,6 +584,7 @@ enum {
         TEGRA_VGPU_EVENT_ABORT = 1,
         TEGRA_VGPU_EVENT_FECS_TRACE = 2,
         TEGRA_VGPU_EVENT_CHANNEL = 3,
+        TEGRA_VGPU_EVENT_SM_ESR = 4,
 };
 
 struct tegra_vgpu_intr_msg {
@@ -588,6 +598,7 @@ struct tegra_vgpu_intr_msg {
                 struct tegra_vgpu_ce2_nonstall_intr_info ce2_nonstall_intr;
                 struct tegra_vgpu_fecs_trace_event_info fecs_trace;
                 struct tegra_vgpu_channel_event_info channel_event;
+                struct tegra_vgpu_sm_esr_info sm_esr;
                 char padding[32];
         } info;
 };