4 files changed, 7 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/common/linux/ioctl_ctrl.c b/drivers/gpu/nvgpu/common/linux/ioctl_ctrl.c
index f5f467b3..0b449692 100644
--- a/drivers/gpu/nvgpu/common/linux/ioctl_ctrl.c
+++ b/drivers/gpu/nvgpu/common/linux/ioctl_ctrl.c
@@ -176,6 +176,8 @@ static struct nvgpu_flags_mapping flags_mapping[] = {
                 NVGPU_SUPPORT_TSG_SUBCONTEXTS},
         {NVGPU_GPU_FLAGS_SUPPORT_SCG,
                 NVGPU_SUPPORT_SCG},
+        {NVGPU_GPU_FLAGS_SUPPORT_VPR,
+                NVGPU_SUPPORT_VPR},
 };
 
 static u64 nvgpu_ctrl_ioctl_gpu_characteristics_flags(struct gk20a *g)
diff --git a/drivers/gpu/nvgpu/common/linux/platform_gk20a_tegra.c b/drivers/gpu/nvgpu/common/linux/platform_gk20a_tegra.c
index db30fff2..127a8ce9 100644
--- a/drivers/gpu/nvgpu/common/linux/platform_gk20a_tegra.c
+++ b/drivers/gpu/nvgpu/common/linux/platform_gk20a_tegra.c
@@ -667,6 +667,7 @@ void gk20a_tegra_idle(struct device *dev)
 void gk20a_tegra_init_secure_alloc(struct gk20a *g)
 {
         g->ops.secure_alloc = gk20a_tegra_secure_alloc;
+        __nvgpu_set_enabled(g, NVGPU_SUPPORT_VPR, true);
 }
 
 #ifdef CONFIG_COMMON_CLK
diff --git a/drivers/gpu/nvgpu/include/nvgpu/enabled.h b/drivers/gpu/nvgpu/include/nvgpu/enabled.h
index cdfd0c55..e6f9525d 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/enabled.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/enabled.h
@@ -113,6 +113,8 @@ struct gk20a;
 
 #define NVGPU_SEC_SECUREGPCCS                   41
 #define NVGPU_SEC_PRIVSECURITY                  42
+/* VPR is supported */
+#define NVGPU_SUPPORT_VPR                       43
 
 /*
  * Nvlink flags
diff --git a/include/uapi/linux/nvgpu.h b/include/uapi/linux/nvgpu.h
index 41b4eb8d..206832ae 100644
--- a/include/uapi/linux/nvgpu.h
+++ b/include/uapi/linux/nvgpu.h
@@ -156,6 +156,8 @@ struct nvgpu_gpu_zbc_query_table_args {
 #define NVGPU_GPU_FLAGS_SUPPORT_SCG                     (1ULL << 25)
 /* GPU_VA address of a syncpoint is supported */
 #define NVGPU_GPU_FLAGS_SUPPORT_SYNCPOINT_ADDRESS       (1ULL << 26)
+/* VPR is supported */
+#define NVGPU_GPU_FLAGS_SUPPORT_VPR                     (1ULL << 27)
 /* SM LRF ECC is enabled */
 #define NVGPU_GPU_FLAGS_ECC_ENABLED_SM_LRF      (1ULL << 60)
 /* SM SHM ECC is enabled */