diff options
-rw-r--r-- | drivers/gpu/nvgpu/Makefile | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/bus/bus_gk20a.c | 31 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/bus/bus_gk20a.h | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/pramin.c | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pramin_gk20a.c | 73 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pramin_gk20a.h | 36 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/hal_gp106.c | 5 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/hal_gv100.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | 1 |
14 files changed, 52 insertions, 129 deletions
diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 1fc52d73..8f2e72d6 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile | |||
@@ -92,7 +92,6 @@ nvgpu-y += \ | |||
92 | common/clock_gating/gv100_gating_reglist.o \ | 92 | common/clock_gating/gv100_gating_reglist.o \ |
93 | common/clock_gating/gv11b_gating_reglist.o \ | 93 | common/clock_gating/gv11b_gating_reglist.o \ |
94 | gk20a/gk20a.o \ | 94 | gk20a/gk20a.o \ |
95 | gk20a/pramin_gk20a.o \ | ||
96 | gk20a/ce2_gk20a.o \ | 95 | gk20a/ce2_gk20a.o \ |
97 | gk20a/fifo_gk20a.o \ | 96 | gk20a/fifo_gk20a.o \ |
98 | gk20a/channel_gk20a.o \ | 97 | gk20a/channel_gk20a.o \ |
diff --git a/drivers/gpu/nvgpu/common/bus/bus_gk20a.c b/drivers/gpu/nvgpu/common/bus/bus_gk20a.c index 62dd7450..a2c6a3d7 100644 --- a/drivers/gpu/nvgpu/common/bus/bus_gk20a.c +++ b/drivers/gpu/nvgpu/common/bus/bus_gk20a.c | |||
@@ -169,3 +169,34 @@ int gk20a_bus_bar1_bind(struct gk20a *g, struct nvgpu_mem *bar1_inst) | |||
169 | 169 | ||
170 | return 0; | 170 | return 0; |
171 | } | 171 | } |
172 | |||
173 | u32 gk20a_bus_set_bar0_window(struct gk20a *g, struct nvgpu_mem *mem, | ||
174 | struct nvgpu_sgt *sgt, struct nvgpu_sgl *sgl, u32 w) | ||
175 | { | ||
176 | u64 bufbase = nvgpu_sgt_get_phys(g, sgt, sgl); | ||
177 | u64 addr = bufbase + w * sizeof(u32); | ||
178 | u32 hi = (u32)((addr & ~(u64)0xfffff) | ||
179 | >> bus_bar0_window_target_bar0_window_base_shift_v()); | ||
180 | u32 lo = (u32)(addr & 0xfffff); | ||
181 | u32 win = nvgpu_aperture_mask(g, mem, | ||
182 | bus_bar0_window_target_sys_mem_noncoherent_f(), | ||
183 | bus_bar0_window_target_sys_mem_coherent_f(), | ||
184 | bus_bar0_window_target_vid_mem_f()) | | ||
185 | bus_bar0_window_base_f(hi); | ||
186 | |||
187 | nvgpu_log(g, gpu_dbg_mem, | ||
188 | "0x%08x:%08x begin for %p,%p at [%llx,%llx] (sz %llx)", | ||
189 | hi, lo, mem, sgl, bufbase, | ||
190 | bufbase + nvgpu_sgt_get_phys(g, sgt, sgl), | ||
191 | nvgpu_sgt_get_length(sgt, sgl)); | ||
192 | |||
193 | WARN_ON(!bufbase); | ||
194 | |||
195 | if (g->mm.pramin_window != win) { | ||
196 | gk20a_writel(g, bus_bar0_window_r(), win); | ||
197 | gk20a_readl(g, bus_bar0_window_r()); | ||
198 | g->mm.pramin_window = win; | ||
199 | } | ||
200 | |||
201 | return lo; | ||
202 | } | ||
diff --git a/drivers/gpu/nvgpu/common/bus/bus_gk20a.h b/drivers/gpu/nvgpu/common/bus/bus_gk20a.h index 1f81a4b0..fe1cad58 100644 --- a/drivers/gpu/nvgpu/common/bus/bus_gk20a.h +++ b/drivers/gpu/nvgpu/common/bus/bus_gk20a.h | |||
@@ -27,10 +27,16 @@ | |||
27 | struct gk20a; | 27 | struct gk20a; |
28 | struct gpu_ops; | 28 | struct gpu_ops; |
29 | struct nvgpu_mem; | 29 | struct nvgpu_mem; |
30 | struct nvgpu_sgt; | ||
31 | struct nvgpu_sgl; | ||
30 | 32 | ||
31 | void gk20a_bus_isr(struct gk20a *g); | 33 | void gk20a_bus_isr(struct gk20a *g); |
32 | int gk20a_read_ptimer(struct gk20a *g, u64 *value); | 34 | int gk20a_read_ptimer(struct gk20a *g, u64 *value); |
33 | void gk20a_bus_init_hw(struct gk20a *g); | 35 | void gk20a_bus_init_hw(struct gk20a *g); |
34 | int gk20a_bus_bar1_bind(struct gk20a *g, struct nvgpu_mem *bar1_inst); | 36 | int gk20a_bus_bar1_bind(struct gk20a *g, struct nvgpu_mem *bar1_inst); |
37 | u32 gk20a_bus_set_bar0_window(struct gk20a *g, struct nvgpu_mem *mem, | ||
38 | struct nvgpu_sgt *sgt, | ||
39 | struct nvgpu_sgl *sgl, | ||
40 | u32 w); | ||
35 | 41 | ||
36 | #endif /* GK20A_H */ | 42 | #endif /* BUS_GK20A_H */ |
diff --git a/drivers/gpu/nvgpu/common/pramin.c b/drivers/gpu/nvgpu/common/pramin.c index ed961965..4c6a4a0d 100644 --- a/drivers/gpu/nvgpu/common/pramin.c +++ b/drivers/gpu/nvgpu/common/pramin.c | |||
@@ -61,7 +61,8 @@ void nvgpu_pramin_access_batched(struct gk20a *g, struct nvgpu_mem *mem, | |||
61 | while (size) { | 61 | while (size) { |
62 | u32 sgl_len = (u32)nvgpu_sgt_get_length(sgt, sgl); | 62 | u32 sgl_len = (u32)nvgpu_sgt_get_length(sgt, sgl); |
63 | 63 | ||
64 | byteoff = g->ops.pramin.enter(g, mem, sgt, sgl, | 64 | nvgpu_spinlock_acquire(&g->mm.pramin_window_lock); |
65 | byteoff = g->ops.bus.set_bar0_window(g, mem, sgt, sgl, | ||
65 | offset / sizeof(u32)); | 66 | offset / sizeof(u32)); |
66 | start_reg = g->ops.pramin.data032_r(byteoff / sizeof(u32)); | 67 | start_reg = g->ops.pramin.data032_r(byteoff / sizeof(u32)); |
67 | until_end = SZ_1M - (byteoff & (SZ_1M - 1)); | 68 | until_end = SZ_1M - (byteoff & (SZ_1M - 1)); |
@@ -72,7 +73,8 @@ void nvgpu_pramin_access_batched(struct gk20a *g, struct nvgpu_mem *mem, | |||
72 | 73 | ||
73 | /* read back to synchronize accesses */ | 74 | /* read back to synchronize accesses */ |
74 | gk20a_readl(g, start_reg); | 75 | gk20a_readl(g, start_reg); |
75 | g->ops.pramin.exit(g, mem, sgl); | 76 | |
77 | nvgpu_spinlock_release(&g->mm.pramin_window_lock); | ||
76 | 78 | ||
77 | size -= n; | 79 | size -= n; |
78 | 80 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 2d304cff..f6b0b362 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -925,9 +925,6 @@ struct gpu_ops { | |||
925 | struct gr_ctx_buffer_desc *desc, | 925 | struct gr_ctx_buffer_desc *desc, |
926 | size_t size); | 926 | size_t size); |
927 | struct { | 927 | struct { |
928 | u32 (*enter)(struct gk20a *g, struct nvgpu_mem *mem, | ||
929 | struct nvgpu_sgt *sgt, struct nvgpu_sgl *sgl, | ||
930 | u32 w); | ||
931 | void (*exit)(struct gk20a *g, struct nvgpu_mem *mem, | 928 | void (*exit)(struct gk20a *g, struct nvgpu_mem *mem, |
932 | struct nvgpu_sgl *sgl); | 929 | struct nvgpu_sgl *sgl); |
933 | u32 (*data032_r)(u32 i); | 930 | u32 (*data032_r)(u32 i); |
@@ -1128,6 +1125,9 @@ struct gpu_ops { | |||
1128 | u32 source_id, u32 count, | 1125 | u32 source_id, u32 count, |
1129 | struct nvgpu_cpu_time_correlation_sample *); | 1126 | struct nvgpu_cpu_time_correlation_sample *); |
1130 | int (*bar1_bind)(struct gk20a *g, struct nvgpu_mem *bar1_inst); | 1127 | int (*bar1_bind)(struct gk20a *g, struct nvgpu_mem *bar1_inst); |
1128 | u32 (*set_bar0_window)(struct gk20a *g, struct nvgpu_mem *mem, | ||
1129 | struct nvgpu_sgt *sgt, struct nvgpu_sgl *sgl, | ||
1130 | u32 w); | ||
1131 | } bus; | 1131 | } bus; |
1132 | 1132 | ||
1133 | struct { | 1133 | struct { |
diff --git a/drivers/gpu/nvgpu/gk20a/pramin_gk20a.c b/drivers/gpu/nvgpu/gk20a/pramin_gk20a.c deleted file mode 100644 index 8dde61a2..00000000 --- a/drivers/gpu/nvgpu/gk20a/pramin_gk20a.c +++ /dev/null | |||
@@ -1,73 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | #include <nvgpu/page_allocator.h> | ||
24 | #include <nvgpu/bug.h> | ||
25 | |||
26 | #include "gk20a/gk20a.h" | ||
27 | #include "gk20a/mm_gk20a.h" | ||
28 | #include "gk20a/pramin_gk20a.h" | ||
29 | |||
30 | #include <nvgpu/hw/gk20a/hw_bus_gk20a.h> | ||
31 | #include <nvgpu/hw/gk20a/hw_pram_gk20a.h> | ||
32 | |||
33 | /* WARNING: returns pramin_window_lock taken, complement with pramin_exit() */ | ||
34 | u32 gk20a_pramin_enter(struct gk20a *g, struct nvgpu_mem *mem, | ||
35 | struct nvgpu_sgt *sgt, struct nvgpu_sgl *sgl, u32 w) | ||
36 | { | ||
37 | u64 bufbase = nvgpu_sgt_get_phys(g, sgt, sgl); | ||
38 | u64 addr = bufbase + w * sizeof(u32); | ||
39 | u32 hi = (u32)((addr & ~(u64)0xfffff) | ||
40 | >> bus_bar0_window_target_bar0_window_base_shift_v()); | ||
41 | u32 lo = (u32)(addr & 0xfffff); | ||
42 | u32 win = nvgpu_aperture_mask(g, mem, | ||
43 | bus_bar0_window_target_sys_mem_noncoherent_f(), | ||
44 | bus_bar0_window_target_sys_mem_coherent_f(), | ||
45 | bus_bar0_window_target_vid_mem_f()) | | ||
46 | bus_bar0_window_base_f(hi); | ||
47 | |||
48 | nvgpu_log(g, gpu_dbg_mem, | ||
49 | "0x%08x:%08x begin for %p,%p at [%llx,%llx] (sz %llx)", | ||
50 | hi, lo, mem, sgl, bufbase, | ||
51 | bufbase + nvgpu_sgt_get_phys(g, sgt, sgl), | ||
52 | nvgpu_sgt_get_length(sgt, sgl)); | ||
53 | |||
54 | WARN_ON(!bufbase); | ||
55 | |||
56 | nvgpu_spinlock_acquire(&g->mm.pramin_window_lock); | ||
57 | |||
58 | if (g->mm.pramin_window != win) { | ||
59 | gk20a_writel(g, bus_bar0_window_r(), win); | ||
60 | gk20a_readl(g, bus_bar0_window_r()); | ||
61 | g->mm.pramin_window = win; | ||
62 | } | ||
63 | |||
64 | return lo; | ||
65 | } | ||
66 | |||
67 | void gk20a_pramin_exit(struct gk20a *g, struct nvgpu_mem *mem, | ||
68 | struct nvgpu_sgl *sgl) | ||
69 | { | ||
70 | nvgpu_log(g, gpu_dbg_mem, "end for %p,%p", mem, sgl); | ||
71 | |||
72 | nvgpu_spinlock_release(&g->mm.pramin_window_lock); | ||
73 | } | ||
diff --git a/drivers/gpu/nvgpu/gk20a/pramin_gk20a.h b/drivers/gpu/nvgpu/gk20a/pramin_gk20a.h deleted file mode 100644 index a0a28088..00000000 --- a/drivers/gpu/nvgpu/gk20a/pramin_gk20a.h +++ /dev/null | |||
@@ -1,36 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | #ifndef __PRAMIN_GK20A_H__ | ||
24 | #define __PRAMIN_GK20A_H__ | ||
25 | |||
26 | struct gk20a; | ||
27 | struct nvgpu_mem; | ||
28 | struct nvgpu_mem_sgl; | ||
29 | |||
30 | u32 gk20a_pramin_enter(struct gk20a *g, struct nvgpu_mem *mem, | ||
31 | struct nvgpu_sgt *sgt, | ||
32 | struct nvgpu_sgl *sgl, | ||
33 | u32 w); | ||
34 | void gk20a_pramin_exit(struct gk20a *g, struct nvgpu_mem *mem, | ||
35 | struct nvgpu_sgl *sgl); | ||
36 | #endif | ||
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index 970d2d27..ea021d27 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c | |||
@@ -608,6 +608,7 @@ static const struct gpu_ops gm20b_ops = { | |||
608 | .read_ptimer = gk20a_read_ptimer, | 608 | .read_ptimer = gk20a_read_ptimer, |
609 | .get_timestamps_zipper = nvgpu_get_timestamps_zipper, | 609 | .get_timestamps_zipper = nvgpu_get_timestamps_zipper, |
610 | .bar1_bind = gm20b_bus_bar1_bind, | 610 | .bar1_bind = gm20b_bus_bar1_bind, |
611 | .set_bar0_window = gk20a_bus_set_bar0_window, | ||
611 | }, | 612 | }, |
612 | #if defined(CONFIG_GK20A_CYCLE_STATS) | 613 | #if defined(CONFIG_GK20A_CYCLE_STATS) |
613 | .css = { | 614 | .css = { |
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index 6749dba7..1a9c6a74 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c | |||
@@ -31,7 +31,6 @@ | |||
31 | #include "gk20a/mm_gk20a.h" | 31 | #include "gk20a/mm_gk20a.h" |
32 | #include "gk20a/dbg_gpu_gk20a.h" | 32 | #include "gk20a/dbg_gpu_gk20a.h" |
33 | #include "gk20a/css_gr_gk20a.h" | 33 | #include "gk20a/css_gr_gk20a.h" |
34 | #include "gk20a/pramin_gk20a.h" | ||
35 | #include "gk20a/flcn_gk20a.h" | 34 | #include "gk20a/flcn_gk20a.h" |
36 | #include "gk20a/regops_gk20a.h" | 35 | #include "gk20a/regops_gk20a.h" |
37 | #include "gk20a/mc_gk20a.h" | 36 | #include "gk20a/mc_gk20a.h" |
@@ -589,8 +588,6 @@ static const struct gpu_ops gp106_ops = { | |||
589 | .get_kind_pitch = gm20b_get_kind_pitch, | 588 | .get_kind_pitch = gm20b_get_kind_pitch, |
590 | }, | 589 | }, |
591 | .pramin = { | 590 | .pramin = { |
592 | .enter = gk20a_pramin_enter, | ||
593 | .exit = gk20a_pramin_exit, | ||
594 | .data032_r = pram_data032_r, | 591 | .data032_r = pram_data032_r, |
595 | }, | 592 | }, |
596 | .therm = { | 593 | .therm = { |
@@ -726,7 +723,7 @@ static const struct gpu_ops gp106_ops = { | |||
726 | .read_ptimer = gk20a_read_ptimer, | 723 | .read_ptimer = gk20a_read_ptimer, |
727 | .get_timestamps_zipper = nvgpu_get_timestamps_zipper, | 724 | .get_timestamps_zipper = nvgpu_get_timestamps_zipper, |
728 | .bar1_bind = gk20a_bus_bar1_bind, | 725 | .bar1_bind = gk20a_bus_bar1_bind, |
729 | 726 | .set_bar0_window = gk20a_bus_set_bar0_window, | |
730 | }, | 727 | }, |
731 | #if defined(CONFIG_GK20A_CYCLE_STATS) | 728 | #if defined(CONFIG_GK20A_CYCLE_STATS) |
732 | .css = { | 729 | .css = { |
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 47986f1b..defec775 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c | |||
@@ -31,7 +31,6 @@ | |||
31 | #include "gk20a/mm_gk20a.h" | 31 | #include "gk20a/mm_gk20a.h" |
32 | #include "gk20a/dbg_gpu_gk20a.h" | 32 | #include "gk20a/dbg_gpu_gk20a.h" |
33 | #include "gk20a/css_gr_gk20a.h" | 33 | #include "gk20a/css_gr_gk20a.h" |
34 | #include "gk20a/pramin_gk20a.h" | ||
35 | #include "gk20a/flcn_gk20a.h" | 34 | #include "gk20a/flcn_gk20a.h" |
36 | #include "gk20a/regops_gk20a.h" | 35 | #include "gk20a/regops_gk20a.h" |
37 | #include "gk20a/mc_gk20a.h" | 36 | #include "gk20a/mc_gk20a.h" |
@@ -559,8 +558,6 @@ static const struct gpu_ops gp10b_ops = { | |||
559 | .get_kind_pitch = gm20b_get_kind_pitch, | 558 | .get_kind_pitch = gm20b_get_kind_pitch, |
560 | }, | 559 | }, |
561 | .pramin = { | 560 | .pramin = { |
562 | .enter = gk20a_pramin_enter, | ||
563 | .exit = gk20a_pramin_exit, | ||
564 | .data032_r = pram_data032_r, | 561 | .data032_r = pram_data032_r, |
565 | }, | 562 | }, |
566 | .therm = { | 563 | .therm = { |
@@ -656,6 +653,7 @@ static const struct gpu_ops gp10b_ops = { | |||
656 | .read_ptimer = gk20a_read_ptimer, | 653 | .read_ptimer = gk20a_read_ptimer, |
657 | .get_timestamps_zipper = nvgpu_get_timestamps_zipper, | 654 | .get_timestamps_zipper = nvgpu_get_timestamps_zipper, |
658 | .bar1_bind = gk20a_bus_bar1_bind, | 655 | .bar1_bind = gk20a_bus_bar1_bind, |
656 | .set_bar0_window = gk20a_bus_set_bar0_window, | ||
659 | }, | 657 | }, |
660 | #if defined(CONFIG_GK20A_CYCLE_STATS) | 658 | #if defined(CONFIG_GK20A_CYCLE_STATS) |
661 | .css = { | 659 | .css = { |
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 00c992bc..ac68bff3 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c | |||
@@ -31,7 +31,6 @@ | |||
31 | #include "gk20a/css_gr_gk20a.h" | 31 | #include "gk20a/css_gr_gk20a.h" |
32 | #include "gk20a/mc_gk20a.h" | 32 | #include "gk20a/mc_gk20a.h" |
33 | #include "gk20a/dbg_gpu_gk20a.h" | 33 | #include "gk20a/dbg_gpu_gk20a.h" |
34 | #include "gk20a/pramin_gk20a.h" | ||
35 | #include "gk20a/flcn_gk20a.h" | 34 | #include "gk20a/flcn_gk20a.h" |
36 | #include "gk20a/regops_gk20a.h" | 35 | #include "gk20a/regops_gk20a.h" |
37 | #include "gk20a/fb_gk20a.h" | 36 | #include "gk20a/fb_gk20a.h" |
@@ -659,8 +658,6 @@ static const struct gpu_ops gv100_ops = { | |||
659 | .get_flush_retries = gv100_mm_get_flush_retries, | 658 | .get_flush_retries = gv100_mm_get_flush_retries, |
660 | }, | 659 | }, |
661 | .pramin = { | 660 | .pramin = { |
662 | .enter = gk20a_pramin_enter, | ||
663 | .exit = gk20a_pramin_exit, | ||
664 | .data032_r = pram_data032_r, | 661 | .data032_r = pram_data032_r, |
665 | }, | 662 | }, |
666 | .therm = { | 663 | .therm = { |
@@ -796,6 +793,7 @@ static const struct gpu_ops gv100_ops = { | |||
796 | .read_ptimer = gk20a_read_ptimer, | 793 | .read_ptimer = gk20a_read_ptimer, |
797 | .get_timestamps_zipper = nvgpu_get_timestamps_zipper, | 794 | .get_timestamps_zipper = nvgpu_get_timestamps_zipper, |
798 | .bar1_bind = NULL, | 795 | .bar1_bind = NULL, |
796 | .set_bar0_window = gk20a_bus_set_bar0_window, | ||
799 | }, | 797 | }, |
800 | #if defined(CONFIG_GK20A_CYCLE_STATS) | 798 | #if defined(CONFIG_GK20A_CYCLE_STATS) |
801 | .css = { | 799 | .css = { |
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index a191c3fc..6ec3c610 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c | |||
@@ -725,6 +725,7 @@ static const struct gpu_ops gv11b_ops = { | |||
725 | .read_ptimer = gk20a_read_ptimer, | 725 | .read_ptimer = gk20a_read_ptimer, |
726 | .get_timestamps_zipper = nvgpu_get_timestamps_zipper, | 726 | .get_timestamps_zipper = nvgpu_get_timestamps_zipper, |
727 | .bar1_bind = NULL, | 727 | .bar1_bind = NULL, |
728 | .set_bar0_window = gk20a_bus_set_bar0_window, | ||
728 | }, | 729 | }, |
729 | #if defined(CONFIG_GK20A_CYCLE_STATS) | 730 | #if defined(CONFIG_GK20A_CYCLE_STATS) |
730 | .css = { | 731 | .css = { |
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c index f4a87a74..2e12b512 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c | |||
@@ -37,7 +37,6 @@ | |||
37 | #include "vgpu_mm_gp10b.h" | 37 | #include "vgpu_mm_gp10b.h" |
38 | #include "vgpu_fuse_gp10b.h" | 38 | #include "vgpu_fuse_gp10b.h" |
39 | 39 | ||
40 | #include "gk20a/pramin_gk20a.h" | ||
41 | #include "gk20a/flcn_gk20a.h" | 40 | #include "gk20a/flcn_gk20a.h" |
42 | #include "gk20a/mc_gk20a.h" | 41 | #include "gk20a/mc_gk20a.h" |
43 | #include "gk20a/fb_gk20a.h" | 42 | #include "gk20a/fb_gk20a.h" |
@@ -433,8 +432,6 @@ static const struct gpu_ops vgpu_gp10b_ops = { | |||
433 | .get_kind_pitch = gm20b_get_kind_pitch, | 432 | .get_kind_pitch = gm20b_get_kind_pitch, |
434 | }, | 433 | }, |
435 | .pramin = { | 434 | .pramin = { |
436 | .enter = gk20a_pramin_enter, | ||
437 | .exit = gk20a_pramin_exit, | ||
438 | .data032_r = pram_data032_r, | 435 | .data032_r = pram_data032_r, |
439 | }, | 436 | }, |
440 | .therm = { | 437 | .therm = { |
@@ -529,6 +526,7 @@ static const struct gpu_ops vgpu_gp10b_ops = { | |||
529 | .read_ptimer = vgpu_read_ptimer, | 526 | .read_ptimer = vgpu_read_ptimer, |
530 | .get_timestamps_zipper = vgpu_get_timestamps_zipper, | 527 | .get_timestamps_zipper = vgpu_get_timestamps_zipper, |
531 | .bar1_bind = gk20a_bus_bar1_bind, | 528 | .bar1_bind = gk20a_bus_bar1_bind, |
529 | .set_bar0_window = gk20a_bus_set_bar0_window, | ||
532 | }, | 530 | }, |
533 | #if defined(CONFIG_GK20A_CYCLE_STATS) | 531 | #if defined(CONFIG_GK20A_CYCLE_STATS) |
534 | .css = { | 532 | .css = { |
diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c index deecc0d8..0b1aa672 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | |||
@@ -577,6 +577,7 @@ static const struct gpu_ops vgpu_gv11b_ops = { | |||
577 | .read_ptimer = vgpu_read_ptimer, | 577 | .read_ptimer = vgpu_read_ptimer, |
578 | .get_timestamps_zipper = vgpu_get_timestamps_zipper, | 578 | .get_timestamps_zipper = vgpu_get_timestamps_zipper, |
579 | .bar1_bind = NULL, | 579 | .bar1_bind = NULL, |
580 | .set_bar0_window = gk20a_bus_set_bar0_window, | ||
580 | }, | 581 | }, |
581 | #if defined(CONFIG_GK20A_CYCLE_STATS) | 582 | #if defined(CONFIG_GK20A_CYCLE_STATS) |
582 | .css = { | 583 | .css = { |