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-rw-r--r--drivers/gpu/nvgpu/gk20a/ce2_gk20a.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c
index ce23c59a..3a0f20a9 100644
--- a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c
@@ -41,8 +41,6 @@ static u32 ce2_nonblockpipe_isr(struct gk20a *g, u32 fifo_intr)
41{ 41{
42 gk20a_dbg(gpu_dbg_intr, "ce2 non-blocking pipe interrupt\n"); 42 gk20a_dbg(gpu_dbg_intr, "ce2 non-blocking pipe interrupt\n");
43 43
44 /* wake theads waiting in this channel */
45 gk20a_channel_semaphore_wakeup(g);
46 return ce2_intr_status_nonblockpipe_pending_f(); 44 return ce2_intr_status_nonblockpipe_pending_f();
47} 45}
48 46
@@ -81,14 +79,16 @@ void gk20a_ce2_isr(struct gk20a *g)
81void gk20a_ce2_nonstall_isr(struct gk20a *g) 79void gk20a_ce2_nonstall_isr(struct gk20a *g)
82{ 80{
83 u32 ce2_intr = gk20a_readl(g, ce2_intr_status_r()); 81 u32 ce2_intr = gk20a_readl(g, ce2_intr_status_r());
84 u32 clear_intr = 0;
85 82
86 gk20a_dbg(gpu_dbg_intr, "ce2 nonstall isr %08x\n", ce2_intr); 83 gk20a_dbg(gpu_dbg_intr, "ce2 nonstall isr %08x\n", ce2_intr);
87 84
88 if (ce2_intr & ce2_intr_status_nonblockpipe_pending_f()) 85 if (ce2_intr & ce2_intr_status_nonblockpipe_pending_f()) {
89 clear_intr |= ce2_nonblockpipe_isr(g, ce2_intr); 86 gk20a_writel(g, ce2_intr_status_r(),
87 ce2_nonblockpipe_isr(g, ce2_intr));
90 88
91 gk20a_writel(g, ce2_intr_status_r(), clear_intr); 89 /* wake threads waiting in this channel */
90 gk20a_channel_semaphore_wakeup(g);
91 }
92 92
93 return; 93 return;
94} 94}