diff options
-rw-r--r-- | drivers/gpu/nvgpu/gv100/hal_gv100.c | 21 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 21 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_pri_gv11b.h | 7 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 21 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/gk20a.h | 7 |
5 files changed, 61 insertions, 16 deletions
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index be5341b1..5f1a18a0 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c | |||
@@ -243,6 +243,27 @@ static u32 gv100_get_litter_value(struct gk20a *g, int value) | |||
243 | case GPU_LIT_GPC_PRIV_STRIDE: | 243 | case GPU_LIT_GPC_PRIV_STRIDE: |
244 | ret = proj_gpc_priv_stride_v(); | 244 | ret = proj_gpc_priv_stride_v(); |
245 | break; | 245 | break; |
246 | case GPU_LIT_PERFMON_PMMGPCTPCA_DOMAIN_START: | ||
247 | ret = 2; | ||
248 | break; | ||
249 | case GPU_LIT_PERFMON_PMMGPCTPCB_DOMAIN_START: | ||
250 | ret = 9; | ||
251 | break; | ||
252 | case GPU_LIT_PERFMON_PMMGPCTPC_DOMAIN_COUNT: | ||
253 | ret = 7; | ||
254 | break; | ||
255 | case GPU_LIT_PERFMON_PMMFBP_LTC_DOMAIN_START: | ||
256 | ret = 2; | ||
257 | break; | ||
258 | case GPU_LIT_PERFMON_PMMFBP_LTC_DOMAIN_COUNT: | ||
259 | ret = 4; | ||
260 | break; | ||
261 | case GPU_LIT_PERFMON_PMMFBP_ROP_DOMAIN_START: | ||
262 | ret = 6; | ||
263 | break; | ||
264 | case GPU_LIT_PERFMON_PMMFBP_ROP_DOMAIN_COUNT: | ||
265 | ret = 2; | ||
266 | break; | ||
246 | default: | 267 | default: |
247 | nvgpu_err(g, "Missing definition %d", value); | 268 | nvgpu_err(g, "Missing definition %d", value); |
248 | BUG(); | 269 | BUG(); |
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index bb76178e..2e1b4664 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c | |||
@@ -4920,14 +4920,17 @@ int gr_gv11b_create_priv_addr_table(struct gk20a *g, | |||
4920 | u32 offset = 0; | 4920 | u32 offset = 0; |
4921 | 4921 | ||
4922 | if (broadcast_flags & PRI_BROADCAST_FLAGS_PMM_GPCGS_GPCTPCA) { | 4922 | if (broadcast_flags & PRI_BROADCAST_FLAGS_PMM_GPCGS_GPCTPCA) { |
4923 | pmm_domain_start = NV_PERF_PMMGPCTPCA_DOMAIN_START; | 4923 | pmm_domain_start = nvgpu_get_litter_value(g, |
4924 | num_domains = NV_PERF_PMMGPC_NUM_DOMAINS; | 4924 | GPU_LIT_PERFMON_PMMGPCTPCA_DOMAIN_START); |
4925 | num_domains = nvgpu_get_litter_value(g, | ||
4926 | GPU_LIT_PERFMON_PMMGPCTPC_DOMAIN_COUNT); | ||
4925 | offset = PRI_PMMGS_OFFSET_MASK(addr); | 4927 | offset = PRI_PMMGS_OFFSET_MASK(addr); |
4926 | } else if (broadcast_flags & | 4928 | } else if (broadcast_flags & |
4927 | PRI_BROADCAST_FLAGS_PMM_GPCGS_GPCTPCB) { | 4929 | PRI_BROADCAST_FLAGS_PMM_GPCGS_GPCTPCB) { |
4928 | pmm_domain_start = NV_PERF_PMMGPCTPCA_DOMAIN_START + | 4930 | pmm_domain_start = nvgpu_get_litter_value(g, |
4929 | NV_PERF_PMMGPC_NUM_DOMAINS; | 4931 | GPU_LIT_PERFMON_PMMGPCTPCB_DOMAIN_START); |
4930 | num_domains = NV_PERF_PMMGPC_NUM_DOMAINS; | 4932 | num_domains = nvgpu_get_litter_value(g, |
4933 | GPU_LIT_PERFMON_PMMGPCTPC_DOMAIN_COUNT); | ||
4931 | offset = PRI_PMMGS_OFFSET_MASK(addr); | 4934 | offset = PRI_PMMGS_OFFSET_MASK(addr); |
4932 | } else if (broadcast_flags & PRI_BROADCAST_FLAGS_PMM_GPCS) { | 4935 | } else if (broadcast_flags & PRI_BROADCAST_FLAGS_PMM_GPCS) { |
4933 | pmm_domain_start = (addr - | 4936 | pmm_domain_start = (addr - |
@@ -4969,15 +4972,15 @@ int gr_gv11b_create_priv_addr_table(struct gk20a *g, | |||
4969 | gr_gv11b_split_pmm_fbp_broadcast_address(g, | 4972 | gr_gv11b_split_pmm_fbp_broadcast_address(g, |
4970 | PRI_PMMGS_OFFSET_MASK(addr), | 4973 | PRI_PMMGS_OFFSET_MASK(addr), |
4971 | priv_addr_table, &t, | 4974 | priv_addr_table, &t, |
4972 | NV_PERF_PMMFBP_LTC_DOMAIN_START, | 4975 | nvgpu_get_litter_value(g, GPU_LIT_PERFMON_PMMFBP_LTC_DOMAIN_START), |
4973 | NV_PERF_PMMFBP_LTC_NUM_DOMAINS); | 4976 | nvgpu_get_litter_value(g, GPU_LIT_PERFMON_PMMFBP_LTC_DOMAIN_COUNT)); |
4974 | } else if ((addr_type == CTXSW_ADDR_TYPE_ROP) && | 4977 | } else if ((addr_type == CTXSW_ADDR_TYPE_ROP) && |
4975 | (broadcast_flags & PRI_BROADCAST_FLAGS_PMM_FBPGS_ROP)) { | 4978 | (broadcast_flags & PRI_BROADCAST_FLAGS_PMM_FBPGS_ROP)) { |
4976 | gr_gv11b_split_pmm_fbp_broadcast_address(g, | 4979 | gr_gv11b_split_pmm_fbp_broadcast_address(g, |
4977 | PRI_PMMGS_OFFSET_MASK(addr), | 4980 | PRI_PMMGS_OFFSET_MASK(addr), |
4978 | priv_addr_table, &t, | 4981 | priv_addr_table, &t, |
4979 | NV_PERF_PMMFBP_ROP_DOMAIN_START, | 4982 | nvgpu_get_litter_value(g, GPU_LIT_PERFMON_PMMFBP_ROP_DOMAIN_START), |
4980 | NV_PERF_PMMFBP_ROP_NUM_DOMAINS); | 4983 | nvgpu_get_litter_value(g, GPU_LIT_PERFMON_PMMFBP_ROP_DOMAIN_COUNT)); |
4981 | } else if ((addr_type == CTXSW_ADDR_TYPE_FBP) && | 4984 | } else if ((addr_type == CTXSW_ADDR_TYPE_FBP) && |
4982 | (broadcast_flags & PRI_BROADCAST_FLAGS_PMM_FBPS)) { | 4985 | (broadcast_flags & PRI_BROADCAST_FLAGS_PMM_FBPS)) { |
4983 | u32 domain_start; | 4986 | u32 domain_start; |
diff --git a/drivers/gpu/nvgpu/gv11b/gr_pri_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_pri_gv11b.h index 78658bf8..c71f4c9c 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_pri_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_pri_gv11b.h | |||
@@ -37,13 +37,6 @@ | |||
37 | #define NV_PERF_PMMGPC_GPCS 0x00278000 | 37 | #define NV_PERF_PMMGPC_GPCS 0x00278000 |
38 | #define NV_PERF_PMMFBP_FBPS 0x0027C000 | 38 | #define NV_PERF_PMMFBP_FBPS 0x0027C000 |
39 | 39 | ||
40 | #define NV_PERF_PMMGPCTPCA_DOMAIN_START 2 | ||
41 | #define NV_PERF_PMMFBP_LTC_DOMAIN_START 2 | ||
42 | #define NV_PERF_PMMFBP_ROP_DOMAIN_START 6 | ||
43 | #define NV_PERF_PMMGPC_NUM_DOMAINS 7 | ||
44 | #define NV_PERF_PMMFBP_LTC_NUM_DOMAINS 4 | ||
45 | #define NV_PERF_PMMFBP_ROP_NUM_DOMAINS 2 | ||
46 | |||
47 | #define PRI_PMMGS_ADDR_WIDTH 9 | 40 | #define PRI_PMMGS_ADDR_WIDTH 9 |
48 | #define PRI_PMMS_ADDR_WIDTH 14 | 41 | #define PRI_PMMS_ADDR_WIDTH 14 |
49 | 42 | ||
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 468abdd1..cf6a7e2c 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c | |||
@@ -223,6 +223,27 @@ u32 gv11b_get_litter_value(struct gk20a *g, int value) | |||
223 | case GPU_LIT_GPC_PRIV_STRIDE: | 223 | case GPU_LIT_GPC_PRIV_STRIDE: |
224 | ret = proj_gpc_priv_stride_v(); | 224 | ret = proj_gpc_priv_stride_v(); |
225 | break; | 225 | break; |
226 | case GPU_LIT_PERFMON_PMMGPCTPCA_DOMAIN_START: | ||
227 | ret = 2; | ||
228 | break; | ||
229 | case GPU_LIT_PERFMON_PMMGPCTPCB_DOMAIN_START: | ||
230 | ret = 6; | ||
231 | break; | ||
232 | case GPU_LIT_PERFMON_PMMGPCTPC_DOMAIN_COUNT: | ||
233 | ret = 4; | ||
234 | break; | ||
235 | case GPU_LIT_PERFMON_PMMFBP_LTC_DOMAIN_START: | ||
236 | ret = 1; | ||
237 | break; | ||
238 | case GPU_LIT_PERFMON_PMMFBP_LTC_DOMAIN_COUNT: | ||
239 | ret = 2; | ||
240 | break; | ||
241 | case GPU_LIT_PERFMON_PMMFBP_ROP_DOMAIN_START: | ||
242 | ret = 3; | ||
243 | break; | ||
244 | case GPU_LIT_PERFMON_PMMFBP_ROP_DOMAIN_COUNT: | ||
245 | ret = 2; | ||
246 | break; | ||
226 | default: | 247 | default: |
227 | nvgpu_err(g, "Missing definition %d", value); | 248 | nvgpu_err(g, "Missing definition %d", value); |
228 | BUG(); | 249 | BUG(); |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index e1b44b52..a256b01f 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h | |||
@@ -136,6 +136,13 @@ enum gk20a_cbc_op { | |||
136 | #define GPU_LIT_I2M_CLASS 35 | 136 | #define GPU_LIT_I2M_CLASS 35 |
137 | #define GPU_LIT_DMA_COPY_CLASS 36 | 137 | #define GPU_LIT_DMA_COPY_CLASS 36 |
138 | #define GPU_LIT_GPC_PRIV_STRIDE 37 | 138 | #define GPU_LIT_GPC_PRIV_STRIDE 37 |
139 | #define GPU_LIT_PERFMON_PMMGPCTPCA_DOMAIN_START 38 | ||
140 | #define GPU_LIT_PERFMON_PMMGPCTPCB_DOMAIN_START 39 | ||
141 | #define GPU_LIT_PERFMON_PMMGPCTPC_DOMAIN_COUNT 40 | ||
142 | #define GPU_LIT_PERFMON_PMMFBP_LTC_DOMAIN_START 41 | ||
143 | #define GPU_LIT_PERFMON_PMMFBP_LTC_DOMAIN_COUNT 42 | ||
144 | #define GPU_LIT_PERFMON_PMMFBP_ROP_DOMAIN_START 43 | ||
145 | #define GPU_LIT_PERFMON_PMMFBP_ROP_DOMAIN_COUNT 44 | ||
139 | 146 | ||
140 | #define nvgpu_get_litter_value(g, v) (g)->ops.get_litter_value((g), v) | 147 | #define nvgpu_get_litter_value(g, v) (g)->ops.get_litter_value((g), v) |
141 | 148 | ||