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-rw-r--r--drivers/gpu/nvgpu/gk20a/gk20a.h2
-rw-r--r--drivers/gpu/nvgpu/gk20a/gr_gk20a.c18
-rw-r--r--drivers/gpu/nvgpu/gk20a/gr_gk20a.h3
-rw-r--r--drivers/gpu/nvgpu/gm20b/hal_gm20b.c1
-rw-r--r--drivers/gpu/nvgpu/gp106/hal_gp106.c1
-rw-r--r--drivers/gpu/nvgpu/gp10b/hal_gp10b.c1
-rw-r--r--drivers/gpu/nvgpu/gv100/hal_gv100.c1
-rw-r--r--drivers/gpu/nvgpu/gv11b/hal_gv11b.c1
8 files changed, 18 insertions, 10 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 2786340e..84392025 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -443,6 +443,8 @@ struct gpu_ops {
443 struct nvgpu_gr_ctx *gr_ctx); 443 struct nvgpu_gr_ctx *gr_ctx);
444 void (*fecs_host_int_enable)(struct gk20a *g); 444 void (*fecs_host_int_enable)(struct gk20a *g);
445 int (*handle_ssync_hww)(struct gk20a *g); 445 int (*handle_ssync_hww)(struct gk20a *g);
446 void (*set_error_notifier)(struct gk20a *g,
447 struct gr_gk20a_isr_data *isr_data, u32 error_notifier);
446 } gr; 448 } gr;
447 struct { 449 struct {
448 void (*init_hw)(struct gk20a *g); 450 void (*init_hw)(struct gk20a *g);
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 6abc7d41..b37ae8cd 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -5113,7 +5113,7 @@ int gk20a_gr_reset(struct gk20a *g)
5113 return err; 5113 return err;
5114} 5114}
5115 5115
5116static void gk20a_gr_set_error_notifier(struct gk20a *g, 5116void gk20a_gr_set_error_notifier(struct gk20a *g,
5117 struct gr_gk20a_isr_data *isr_data, u32 error_notifier) 5117 struct gr_gk20a_isr_data *isr_data, u32 error_notifier)
5118{ 5118{
5119 struct fifo_gk20a *f = &g->fifo; 5119 struct fifo_gk20a *f = &g->fifo;
@@ -5146,7 +5146,7 @@ static int gk20a_gr_handle_semaphore_timeout_pending(struct gk20a *g,
5146 struct gr_gk20a_isr_data *isr_data) 5146 struct gr_gk20a_isr_data *isr_data)
5147{ 5147{
5148 gk20a_dbg_fn(""); 5148 gk20a_dbg_fn("");
5149 gk20a_gr_set_error_notifier(g, isr_data, 5149 g->ops.gr.set_error_notifier(g, isr_data,
5150 NVGPU_ERR_NOTIFIER_GR_SEMAPHORE_TIMEOUT); 5150 NVGPU_ERR_NOTIFIER_GR_SEMAPHORE_TIMEOUT);
5151 nvgpu_err(g, 5151 nvgpu_err(g,
5152 "gr semaphore timeout"); 5152 "gr semaphore timeout");
@@ -5157,7 +5157,7 @@ static int gk20a_gr_intr_illegal_notify_pending(struct gk20a *g,
5157 struct gr_gk20a_isr_data *isr_data) 5157 struct gr_gk20a_isr_data *isr_data)
5158{ 5158{
5159 gk20a_dbg_fn(""); 5159 gk20a_dbg_fn("");
5160 gk20a_gr_set_error_notifier(g, isr_data, 5160 g->ops.gr.set_error_notifier(g, isr_data,
5161 NVGPU_ERR_NOTIFIER_GR_ILLEGAL_NOTIFY); 5161 NVGPU_ERR_NOTIFIER_GR_ILLEGAL_NOTIFY);
5162 /* This is an unrecoverable error, reset is needed */ 5162 /* This is an unrecoverable error, reset is needed */
5163 nvgpu_err(g, 5163 nvgpu_err(g,
@@ -5172,7 +5172,7 @@ static int gk20a_gr_handle_illegal_method(struct gk20a *g,
5172 isr_data->class_num, isr_data->offset, 5172 isr_data->class_num, isr_data->offset,
5173 isr_data->data_lo); 5173 isr_data->data_lo);
5174 if (ret) { 5174 if (ret) {
5175 gk20a_gr_set_error_notifier(g, isr_data, 5175 g->ops.gr.set_error_notifier(g, isr_data,
5176 NVGPU_ERR_NOTIFIER_GR_ILLEGAL_NOTIFY); 5176 NVGPU_ERR_NOTIFIER_GR_ILLEGAL_NOTIFY);
5177 nvgpu_err(g, "invalid method class 0x%08x" 5177 nvgpu_err(g, "invalid method class 0x%08x"
5178 ", offset 0x%08x address 0x%08x", 5178 ", offset 0x%08x address 0x%08x",
@@ -5185,7 +5185,7 @@ static int gk20a_gr_handle_illegal_class(struct gk20a *g,
5185 struct gr_gk20a_isr_data *isr_data) 5185 struct gr_gk20a_isr_data *isr_data)
5186{ 5186{
5187 gk20a_dbg_fn(""); 5187 gk20a_dbg_fn("");
5188 gk20a_gr_set_error_notifier(g, isr_data, 5188 g->ops.gr.set_error_notifier(g, isr_data,
5189 NVGPU_ERR_NOTIFIER_GR_ERROR_SW_NOTIFY); 5189 NVGPU_ERR_NOTIFIER_GR_ERROR_SW_NOTIFY);
5190 nvgpu_err(g, 5190 nvgpu_err(g,
5191 "invalid class 0x%08x, offset 0x%08x", 5191 "invalid class 0x%08x, offset 0x%08x",
@@ -5203,7 +5203,7 @@ int gk20a_gr_handle_fecs_error(struct gk20a *g, struct channel_gk20a *ch,
5203 return 0; 5203 return 0;
5204 5204
5205 if (gr_fecs_intr & gr_fecs_host_int_status_umimp_firmware_method_f(1)) { 5205 if (gr_fecs_intr & gr_fecs_host_int_status_umimp_firmware_method_f(1)) {
5206 gk20a_gr_set_error_notifier(g, isr_data, 5206 g->ops.gr.set_error_notifier(g, isr_data,
5207 NVGPU_ERR_NOTIFIER_FECS_ERR_UNIMP_FIRMWARE_METHOD); 5207 NVGPU_ERR_NOTIFIER_FECS_ERR_UNIMP_FIRMWARE_METHOD);
5208 nvgpu_err(g, 5208 nvgpu_err(g,
5209 "firmware method error 0x%08x for offset 0x%04x", 5209 "firmware method error 0x%08x for offset 0x%04x",
@@ -5229,7 +5229,7 @@ static int gk20a_gr_handle_class_error(struct gk20a *g,
5229 5229
5230 gr_class_error = 5230 gr_class_error =
5231 gr_class_error_code_v(gk20a_readl(g, gr_class_error_r())); 5231 gr_class_error_code_v(gk20a_readl(g, gr_class_error_r()));
5232 gk20a_gr_set_error_notifier(g, isr_data, 5232 g->ops.gr.set_error_notifier(g, isr_data,
5233 NVGPU_ERR_NOTIFIER_GR_ERROR_SW_NOTIFY); 5233 NVGPU_ERR_NOTIFIER_GR_ERROR_SW_NOTIFY);
5234 nvgpu_err(g, "class error 0x%08x, offset 0x%08x," 5234 nvgpu_err(g, "class error 0x%08x, offset 0x%08x,"
5235 "sub channel 0x%08x mme generated %d," 5235 "sub channel 0x%08x mme generated %d,"
@@ -5258,7 +5258,7 @@ static int gk20a_gr_handle_firmware_method(struct gk20a *g,
5258{ 5258{
5259 gk20a_dbg_fn(""); 5259 gk20a_dbg_fn("");
5260 5260
5261 gk20a_gr_set_error_notifier(g, isr_data, 5261 g->ops.gr.set_error_notifier(g, isr_data,
5262 NVGPU_ERR_NOTIFIER_GR_ERROR_SW_NOTIFY); 5262 NVGPU_ERR_NOTIFIER_GR_ERROR_SW_NOTIFY);
5263 nvgpu_err(g, 5263 nvgpu_err(g,
5264 "firmware method 0x%08x, offset 0x%08x for channel %u", 5264 "firmware method 0x%08x, offset 0x%08x for channel %u",
@@ -6064,7 +6064,7 @@ int gk20a_gr_isr(struct gk20a *g)
6064 6064
6065 if (need_reset) { 6065 if (need_reset) {
6066 nvgpu_err(g, "set gr exception notifier"); 6066 nvgpu_err(g, "set gr exception notifier");
6067 gk20a_gr_set_error_notifier(g, &isr_data, 6067 g->ops.gr.set_error_notifier(g, &isr_data,
6068 NVGPU_ERR_NOTIFIER_GR_EXCEPTION); 6068 NVGPU_ERR_NOTIFIER_GR_EXCEPTION);
6069 } 6069 }
6070 } 6070 }
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
index 3fcba678..d1ba6353 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
@@ -798,5 +798,6 @@ void gk20a_gr_get_ovr_perf_regs(struct gk20a *g, u32 *num_ovr_perf_regs,
798void gk20a_gr_init_ctxsw_hdr_data(struct gk20a *g, 798void gk20a_gr_init_ctxsw_hdr_data(struct gk20a *g,
799 struct nvgpu_mem *mem); 799 struct nvgpu_mem *mem);
800u32 gr_gk20a_get_patch_slots(struct gk20a *g); 800u32 gr_gk20a_get_patch_slots(struct gk20a *g);
801 801void gk20a_gr_set_error_notifier(struct gk20a *g,
802 struct gr_gk20a_isr_data *isr_data, u32 error_notifier);
802#endif /*__GR_GK20A_H__*/ 803#endif /*__GR_GK20A_H__*/
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
index b3efdc8a..7425dc37 100644
--- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
@@ -311,6 +311,7 @@ static const struct gpu_ops gm20b_ops = {
311 .disable_rd_coalesce = gm20a_gr_disable_rd_coalesce, 311 .disable_rd_coalesce = gm20a_gr_disable_rd_coalesce,
312 .init_ctxsw_hdr_data = gk20a_gr_init_ctxsw_hdr_data, 312 .init_ctxsw_hdr_data = gk20a_gr_init_ctxsw_hdr_data,
313 .fecs_host_int_enable = gr_gk20a_fecs_host_int_enable, 313 .fecs_host_int_enable = gr_gk20a_fecs_host_int_enable,
314 .set_error_notifier = gk20a_gr_set_error_notifier,
314 }, 315 },
315 .fb = { 316 .fb = {
316 .reset = fb_gk20a_reset, 317 .reset = fb_gk20a_reset,
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c
index 502a6778..2fa8359e 100644
--- a/drivers/gpu/nvgpu/gp106/hal_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c
@@ -373,6 +373,7 @@ static const struct gpu_ops gp106_ops = {
373 .set_ctxsw_preemption_mode = gr_gp106_set_ctxsw_preemption_mode, 373 .set_ctxsw_preemption_mode = gr_gp106_set_ctxsw_preemption_mode,
374 .load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode, 374 .load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode,
375 .fecs_host_int_enable = gr_gk20a_fecs_host_int_enable, 375 .fecs_host_int_enable = gr_gk20a_fecs_host_int_enable,
376 .set_error_notifier = gk20a_gr_set_error_notifier,
376 }, 377 },
377 .fb = { 378 .fb = {
378 .reset = gp106_fb_reset, 379 .reset = gp106_fb_reset,
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
index 91ebab55..38facd97 100644
--- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
@@ -341,6 +341,7 @@ static const struct gpu_ops gp10b_ops = {
341 gr_gp10b_get_max_gfxp_wfi_timeout_count, 341 gr_gp10b_get_max_gfxp_wfi_timeout_count,
342 .dump_ctxsw_stats = gr_gp10b_dump_ctxsw_stats, 342 .dump_ctxsw_stats = gr_gp10b_dump_ctxsw_stats,
343 .fecs_host_int_enable = gr_gk20a_fecs_host_int_enable, 343 .fecs_host_int_enable = gr_gk20a_fecs_host_int_enable,
344 .set_error_notifier = gk20a_gr_set_error_notifier,
344 }, 345 },
345 .fb = { 346 .fb = {
346 .reset = fb_gk20a_reset, 347 .reset = fb_gk20a_reset,
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c
index c380df8d..449c3f9c 100644
--- a/drivers/gpu/nvgpu/gv100/hal_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c
@@ -426,6 +426,7 @@ static const struct gpu_ops gv100_ops = {
426 .decode_egpc_addr = gv11b_gr_decode_egpc_addr, 426 .decode_egpc_addr = gv11b_gr_decode_egpc_addr,
427 .fecs_host_int_enable = gr_gv11b_fecs_host_int_enable, 427 .fecs_host_int_enable = gr_gv11b_fecs_host_int_enable,
428 .handle_ssync_hww = gr_gv11b_handle_ssync_hww, 428 .handle_ssync_hww = gr_gv11b_handle_ssync_hww,
429 .set_error_notifier = gk20a_gr_set_error_notifier,
429 }, 430 },
430 .fb = { 431 .fb = {
431 .reset = gv100_fb_reset, 432 .reset = gv100_fb_reset,
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
index 5282af05..7ae8898b 100644
--- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
@@ -393,6 +393,7 @@ static const struct gpu_ops gv11b_ops = {
393 .dump_ctxsw_stats = gr_gp10b_dump_ctxsw_stats, 393 .dump_ctxsw_stats = gr_gp10b_dump_ctxsw_stats,
394 .fecs_host_int_enable = gr_gv11b_fecs_host_int_enable, 394 .fecs_host_int_enable = gr_gv11b_fecs_host_int_enable,
395 .handle_ssync_hww = gr_gv11b_handle_ssync_hww, 395 .handle_ssync_hww = gr_gv11b_handle_ssync_hww,
396 .set_error_notifier = gk20a_gr_set_error_notifier,
396 }, 397 },
397 .fb = { 398 .fb = {
398 .reset = gv11b_fb_reset, 399 .reset = gv11b_fb_reset,