diff options
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c | 28 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.c | 22 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 22 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h | 16 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 13 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h | 16 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/mm_gm20b.c | 6 | ||||
-rw-r--r-- | include/uapi/linux/nvgpu.h | 51 |
9 files changed, 172 insertions, 6 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c b/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c index 93831844..3bcbdfd9 100644 --- a/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c | |||
@@ -221,6 +221,30 @@ clean_up: | |||
221 | return err; | 221 | return err; |
222 | } | 222 | } |
223 | 223 | ||
224 | static int gk20a_ctrl_get_tpc_masks(struct gk20a *g, | ||
225 | struct nvgpu_gpu_get_tpc_masks_args *args) | ||
226 | { | ||
227 | struct gr_gk20a *gr = &g->gr; | ||
228 | int err = 0; | ||
229 | const u32 gpc_tpc_mask_size = sizeof(u32) * gr->gpc_count; | ||
230 | |||
231 | if (args->mask_buf_size > 0) { | ||
232 | size_t write_size = gpc_tpc_mask_size; | ||
233 | |||
234 | if (write_size > args->mask_buf_size) | ||
235 | write_size = args->mask_buf_size; | ||
236 | |||
237 | err = copy_to_user((void __user *)(uintptr_t) | ||
238 | args->mask_buf_addr, | ||
239 | gr->gpc_tpc_mask, write_size); | ||
240 | } | ||
241 | |||
242 | if (err == 0) | ||
243 | args->mask_buf_size = gpc_tpc_mask_size; | ||
244 | |||
245 | return err; | ||
246 | } | ||
247 | |||
224 | long gk20a_ctrl_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) | 248 | long gk20a_ctrl_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) |
225 | { | 249 | { |
226 | struct platform_device *dev = filp->private_data; | 250 | struct platform_device *dev = filp->private_data; |
@@ -390,6 +414,10 @@ long gk20a_ctrl_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg | |||
390 | err = gk20a_ctrl_open_tsg(g, | 414 | err = gk20a_ctrl_open_tsg(g, |
391 | (struct nvgpu_gpu_open_tsg_args *)buf); | 415 | (struct nvgpu_gpu_open_tsg_args *)buf); |
392 | break; | 416 | break; |
417 | case NVGPU_GPU_IOCTL_GET_TPC_MASKS: | ||
418 | err = gk20a_ctrl_get_tpc_masks(g, | ||
419 | (struct nvgpu_gpu_get_tpc_masks_args *)buf); | ||
420 | break; | ||
393 | default: | 421 | default: |
394 | dev_dbg(dev_from_gk20a(g), "unrecognized gpu ioctl cmd: 0x%x", cmd); | 422 | dev_dbg(dev_from_gk20a(g), "unrecognized gpu ioctl cmd: 0x%x", cmd); |
395 | err = -ENOTTY; | 423 | err = -ENOTTY; |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c index ef0f6a8c..1bd1c898 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gk20a.c | |||
@@ -1774,13 +1774,33 @@ int gk20a_init_gpu_characteristics(struct gk20a *g) | |||
1774 | gpu->compression_page_size = g->mm.pmu.vm.compression_page_size; | 1774 | gpu->compression_page_size = g->mm.pmu.vm.compression_page_size; |
1775 | gpu->pde_coverage_bit_count = g->mm.pmu.vm.pde_stride_shift; | 1775 | gpu->pde_coverage_bit_count = g->mm.pmu.vm.pde_stride_shift; |
1776 | 1776 | ||
1777 | gpu->available_big_page_sizes = gpu->big_page_size; | ||
1778 | if (g->ops.mm.get_big_page_sizes) | ||
1779 | gpu->available_big_page_sizes |= g->ops.mm.get_big_page_sizes(); | ||
1780 | |||
1777 | gpu->flags = NVGPU_GPU_FLAGS_SUPPORT_PARTIAL_MAPPINGS | 1781 | gpu->flags = NVGPU_GPU_FLAGS_SUPPORT_PARTIAL_MAPPINGS |
1778 | | NVGPU_GPU_FLAGS_SUPPORT_SPARSE_ALLOCS; | 1782 | | NVGPU_GPU_FLAGS_SUPPORT_SPARSE_ALLOCS |
1783 | | NVGPU_GPU_FLAGS_SUPPORT_SYNC_FENCE_FDS; | ||
1779 | 1784 | ||
1780 | if (IS_ENABLED(CONFIG_TEGRA_GK20A) && | 1785 | if (IS_ENABLED(CONFIG_TEGRA_GK20A) && |
1781 | gk20a_platform_has_syncpoints(g->dev)) | 1786 | gk20a_platform_has_syncpoints(g->dev)) |
1782 | gpu->flags |= NVGPU_GPU_FLAGS_HAS_SYNCPOINTS; | 1787 | gpu->flags |= NVGPU_GPU_FLAGS_HAS_SYNCPOINTS; |
1783 | 1788 | ||
1789 | if (IS_ENABLED(CONFIG_GK20A_CYCLE_STATS)) | ||
1790 | gpu->flags |= NVGPU_GPU_FLAGS_SUPPORT_CYCLE_STATS; | ||
1791 | |||
1792 | gpu->gpc_mask = 1; | ||
1793 | |||
1794 | g->ops.gr.detect_sm_arch(g); | ||
1795 | |||
1796 | gpu->gpu_ioctl_nr_last = NVGPU_GPU_IOCTL_LAST; | ||
1797 | gpu->tsg_ioctl_nr_last = NVGPU_TSG_IOCTL_LAST; | ||
1798 | gpu->dbg_gpu_ioctl_nr_last = NVGPU_DBG_GPU_IOCTL_LAST; | ||
1799 | gpu->ioctl_channel_nr_last = NVGPU_IOCTL_CHANNEL_LAST; | ||
1800 | gpu->as_ioctl_nr_last = NVGPU_AS_IOCTL_LAST; | ||
1801 | |||
1802 | gpu->gpu_va_bit_count = 40; | ||
1803 | |||
1784 | gpu->reserved = 0; | 1804 | gpu->reserved = 0; |
1785 | 1805 | ||
1786 | return 0; | 1806 | return 0; |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index a56614ab..3f070a58 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -137,6 +137,7 @@ struct gpu_ops { | |||
137 | struct gr_zcull_info *zcull_params); | 137 | struct gr_zcull_info *zcull_params); |
138 | bool (*is_tpc_addr)(u32 addr); | 138 | bool (*is_tpc_addr)(u32 addr); |
139 | u32 (*get_tpc_num)(u32 addr); | 139 | u32 (*get_tpc_num)(u32 addr); |
140 | void (*detect_sm_arch)(struct gk20a *g); | ||
140 | } gr; | 141 | } gr; |
141 | const char *name; | 142 | const char *name; |
142 | struct { | 143 | struct { |
@@ -304,7 +305,8 @@ struct gpu_ops { | |||
304 | void (*l2_flush)(struct gk20a *g, bool invalidate); | 305 | void (*l2_flush)(struct gk20a *g, bool invalidate); |
305 | void (*tlb_invalidate)(struct vm_gk20a *vm); | 306 | void (*tlb_invalidate)(struct vm_gk20a *vm); |
306 | void (*set_big_page_size)(struct gk20a *g, | 307 | void (*set_big_page_size)(struct gk20a *g, |
307 | void *inst_ptr, int size); | 308 | void *inst_ptr, int size); |
309 | u32 (*get_big_page_sizes)(void); | ||
308 | } mm; | 310 | } mm; |
309 | struct { | 311 | struct { |
310 | int (*prepare_ucode)(struct gk20a *g); | 312 | int (*prepare_ucode)(struct gk20a *g); |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 2c62c790..da257cd4 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -3490,6 +3490,27 @@ int gr_gk20a_get_zcull_info(struct gk20a *g, struct gr_gk20a *gr, | |||
3490 | return 0; | 3490 | return 0; |
3491 | } | 3491 | } |
3492 | 3492 | ||
3493 | static void gr_gk20a_detect_sm_arch(struct gk20a *g) | ||
3494 | { | ||
3495 | u32 v = gk20a_readl(g, gr_gpc0_tpc0_sm_arch_r()); | ||
3496 | |||
3497 | u32 raw_version = gr_gpc0_tpc0_sm_arch_spa_version_v(v); | ||
3498 | u32 version = 0; | ||
3499 | |||
3500 | if (raw_version == gr_gpc0_tpc0_sm_arch_spa_version_smkepler_lp_v()) | ||
3501 | version = 0x320; /* SM 3.2 */ | ||
3502 | else | ||
3503 | gk20a_err(dev_from_gk20a(g), "Unknown SM version 0x%x\n", | ||
3504 | raw_version); | ||
3505 | |||
3506 | /* on Kepler, SM version == SPA version */ | ||
3507 | g->gpu_characteristics.sm_arch_spa_version = version; | ||
3508 | g->gpu_characteristics.sm_arch_sm_version = version; | ||
3509 | |||
3510 | g->gpu_characteristics.sm_arch_warp_count = | ||
3511 | gr_gpc0_tpc0_sm_arch_warp_count_v(v); | ||
3512 | } | ||
3513 | |||
3493 | static int gr_gk20a_add_zbc_color(struct gk20a *g, struct gr_gk20a *gr, | 3514 | static int gr_gk20a_add_zbc_color(struct gk20a *g, struct gr_gk20a *gr, |
3494 | struct zbc_entry *color_val, u32 index) | 3515 | struct zbc_entry *color_val, u32 index) |
3495 | { | 3516 | { |
@@ -7328,5 +7349,6 @@ void gk20a_init_gr_ops(struct gpu_ops *gops) | |||
7328 | gops->gr.get_zcull_info = gr_gk20a_get_zcull_info; | 7349 | gops->gr.get_zcull_info = gr_gk20a_get_zcull_info; |
7329 | gops->gr.is_tpc_addr = gr_gk20a_is_tpc_addr; | 7350 | gops->gr.is_tpc_addr = gr_gk20a_is_tpc_addr; |
7330 | gops->gr.get_tpc_num = gr_gk20a_get_tpc_num; | 7351 | gops->gr.get_tpc_num = gr_gk20a_get_tpc_num; |
7352 | gops->gr.detect_sm_arch = gr_gk20a_detect_sm_arch; | ||
7331 | } | 7353 | } |
7332 | 7354 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h index 3b16df58..f89bb2a4 100644 --- a/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h | |||
@@ -1886,6 +1886,22 @@ static inline u32 gr_gpc0_tpc0_sm_cfg_sm_id_f(u32 v) | |||
1886 | { | 1886 | { |
1887 | return (v & 0xffff) << 0; | 1887 | return (v & 0xffff) << 0; |
1888 | } | 1888 | } |
1889 | static inline u32 gr_gpc0_tpc0_sm_arch_r(void) | ||
1890 | { | ||
1891 | return 0x0050469c; | ||
1892 | } | ||
1893 | static inline u32 gr_gpc0_tpc0_sm_arch_warp_count_v(u32 r) | ||
1894 | { | ||
1895 | return (r >> 0) & 0xff; | ||
1896 | } | ||
1897 | static inline u32 gr_gpc0_tpc0_sm_arch_spa_version_v(u32 r) | ||
1898 | { | ||
1899 | return (r >> 8) & 0xf; | ||
1900 | } | ||
1901 | static inline u32 gr_gpc0_tpc0_sm_arch_spa_version_smkepler_lp_v(void) | ||
1902 | { | ||
1903 | return 0x0000000c; | ||
1904 | } | ||
1889 | static inline u32 gr_gpc0_ppc0_pes_vsc_strem_r(void) | 1905 | static inline u32 gr_gpc0_ppc0_pes_vsc_strem_r(void) |
1890 | { | 1906 | { |
1891 | return 0x00503018; | 1907 | return 0x00503018; |
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index d40e9d52..8f056181 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c | |||
@@ -748,6 +748,18 @@ static int gr_gm20b_load_ctxsw_ucode(struct gk20a *g) | |||
748 | 748 | ||
749 | #endif | 749 | #endif |
750 | 750 | ||
751 | static void gr_gm20b_detect_sm_arch(struct gk20a *g) | ||
752 | { | ||
753 | u32 v = gk20a_readl(g, gr_gpc0_tpc0_sm_arch_r()); | ||
754 | |||
755 | g->gpu_characteristics.sm_arch_spa_version = | ||
756 | gr_gpc0_tpc0_sm_arch_spa_version_v(v); | ||
757 | g->gpu_characteristics.sm_arch_sm_version = | ||
758 | gr_gpc0_tpc0_sm_arch_sm_version_v(v); | ||
759 | g->gpu_characteristics.sm_arch_warp_count = | ||
760 | gr_gpc0_tpc0_sm_arch_warp_count_v(v); | ||
761 | } | ||
762 | |||
751 | void gm20b_init_gr(struct gpu_ops *gops) | 763 | void gm20b_init_gr(struct gpu_ops *gops) |
752 | { | 764 | { |
753 | gops->gr.init_gpc_mmu = gr_gm20b_init_gpc_mmu; | 765 | gops->gr.init_gpc_mmu = gr_gm20b_init_gpc_mmu; |
@@ -781,4 +793,5 @@ void gm20b_init_gr(struct gpu_ops *gops) | |||
781 | gops->gr.get_zcull_info = gr_gk20a_get_zcull_info; | 793 | gops->gr.get_zcull_info = gr_gk20a_get_zcull_info; |
782 | gops->gr.is_tpc_addr = gr_gm20b_is_tpc_addr; | 794 | gops->gr.is_tpc_addr = gr_gm20b_is_tpc_addr; |
783 | gops->gr.get_tpc_num = gr_gm20b_get_tpc_num; | 795 | gops->gr.get_tpc_num = gr_gm20b_get_tpc_num; |
796 | gops->gr.detect_sm_arch = gr_gm20b_detect_sm_arch; | ||
784 | } | 797 | } |
diff --git a/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h index 0dae5896..8e4308a3 100644 --- a/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h | |||
@@ -1878,6 +1878,22 @@ static inline u32 gr_gpc0_tpc0_sm_cfg_sm_id_f(u32 v) | |||
1878 | { | 1878 | { |
1879 | return (v & 0xffff) << 0; | 1879 | return (v & 0xffff) << 0; |
1880 | } | 1880 | } |
1881 | static inline u32 gr_gpc0_tpc0_sm_arch_r(void) | ||
1882 | { | ||
1883 | return 0x0050469c; | ||
1884 | } | ||
1885 | static inline u32 gr_gpc0_tpc0_sm_arch_warp_count_v(u32 r) | ||
1886 | { | ||
1887 | return (r >> 0) & 0xff; | ||
1888 | } | ||
1889 | static inline u32 gr_gpc0_tpc0_sm_arch_spa_version_v(u32 r) | ||
1890 | { | ||
1891 | return (r >> 8) & 0xfff; | ||
1892 | } | ||
1893 | static inline u32 gr_gpc0_tpc0_sm_arch_sm_version_v(u32 r) | ||
1894 | { | ||
1895 | return (r >> 20) & 0xfff; | ||
1896 | } | ||
1881 | static inline u32 gr_gpc0_ppc0_pes_vsc_strem_r(void) | 1897 | static inline u32 gr_gpc0_ppc0_pes_vsc_strem_r(void) |
1882 | { | 1898 | { |
1883 | return 0x00503018; | 1899 | return 0x00503018; |
diff --git a/drivers/gpu/nvgpu/gm20b/mm_gm20b.c b/drivers/gpu/nvgpu/gm20b/mm_gm20b.c index 030701b9..678ef4fd 100644 --- a/drivers/gpu/nvgpu/gm20b/mm_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/mm_gm20b.c | |||
@@ -280,6 +280,11 @@ static void gm20b_mm_set_big_page_size(struct gk20a *g, | |||
280 | gk20a_dbg_fn("done"); | 280 | gk20a_dbg_fn("done"); |
281 | } | 281 | } |
282 | 282 | ||
283 | u32 gm20b_mm_get_big_page_sizes(void) | ||
284 | { | ||
285 | return SZ_64K | SZ_128K; | ||
286 | } | ||
287 | |||
283 | void gm20b_init_mm(struct gpu_ops *gops) | 288 | void gm20b_init_mm(struct gpu_ops *gops) |
284 | { | 289 | { |
285 | gops->mm.set_sparse = gm20b_vm_put_sparse; | 290 | gops->mm.set_sparse = gm20b_vm_put_sparse; |
@@ -295,4 +300,5 @@ void gm20b_init_mm(struct gpu_ops *gops) | |||
295 | gops->mm.l2_flush = gk20a_mm_l2_flush; | 300 | gops->mm.l2_flush = gk20a_mm_l2_flush; |
296 | gops->mm.tlb_invalidate = gk20a_mm_tlb_invalidate; | 301 | gops->mm.tlb_invalidate = gk20a_mm_tlb_invalidate; |
297 | gops->mm.set_big_page_size = gm20b_mm_set_big_page_size; | 302 | gops->mm.set_big_page_size = gm20b_mm_set_big_page_size; |
303 | gops->mm.get_big_page_sizes = gm20b_mm_get_big_page_sizes; | ||
298 | } | 304 | } |
diff --git a/include/uapi/linux/nvgpu.h b/include/uapi/linux/nvgpu.h index 6bde9d41..42673820 100644 --- a/include/uapi/linux/nvgpu.h +++ b/include/uapi/linux/nvgpu.h | |||
@@ -100,6 +100,10 @@ struct nvgpu_gpu_zbc_query_table_args { | |||
100 | #define NVGPU_GPU_FLAGS_SUPPORT_PARTIAL_MAPPINGS (1 << 1) | 100 | #define NVGPU_GPU_FLAGS_SUPPORT_PARTIAL_MAPPINGS (1 << 1) |
101 | /* MAP_BUFFER_EX with sparse allocations */ | 101 | /* MAP_BUFFER_EX with sparse allocations */ |
102 | #define NVGPU_GPU_FLAGS_SUPPORT_SPARSE_ALLOCS (1 << 2) | 102 | #define NVGPU_GPU_FLAGS_SUPPORT_SPARSE_ALLOCS (1 << 2) |
103 | /* sync fence FDs are available in, e.g., submit_gpfifo */ | ||
104 | #define NVGPU_GPU_FLAGS_SUPPORT_SYNC_FENCE_FDS (1 << 3) | ||
105 | /* NVGPU_IOCTL_CHANNEL_CYCLE_STATS is available */ | ||
106 | #define NVGPU_GPU_FLAGS_SUPPORT_CYCLE_STATS (1 << 4) | ||
103 | 107 | ||
104 | struct nvgpu_gpu_characteristics { | 108 | struct nvgpu_gpu_characteristics { |
105 | __u32 arch; | 109 | __u32 arch; |
@@ -111,14 +115,18 @@ struct nvgpu_gpu_characteristics { | |||
111 | __u64 L2_cache_size; /* bytes */ | 115 | __u64 L2_cache_size; /* bytes */ |
112 | __u64 on_board_video_memory_size; /* bytes */ | 116 | __u64 on_board_video_memory_size; /* bytes */ |
113 | 117 | ||
114 | __u32 num_tpc_per_gpc; | 118 | __u32 num_tpc_per_gpc; /* the architectural maximum */ |
115 | __u32 bus_type; | 119 | __u32 bus_type; |
116 | 120 | ||
117 | __u32 big_page_size; | 121 | __u32 big_page_size; /* the default big page size */ |
118 | __u32 compression_page_size; | 122 | __u32 compression_page_size; |
119 | 123 | ||
120 | __u32 pde_coverage_bit_count; | 124 | __u32 pde_coverage_bit_count; |
121 | __u32 reserved; | 125 | |
126 | /* bit N set ==> big page size 2^N is available in | ||
127 | NVGPU_GPU_IOCTL_ALLOC_AS. The default big page size is | ||
128 | always available regardless of this field. */ | ||
129 | __u32 available_big_page_sizes; | ||
122 | 130 | ||
123 | __u64 flags; | 131 | __u64 flags; |
124 | 132 | ||
@@ -129,6 +137,23 @@ struct nvgpu_gpu_characteristics { | |||
129 | __u32 inline_to_memory_class; | 137 | __u32 inline_to_memory_class; |
130 | __u32 dma_copy_class; | 138 | __u32 dma_copy_class; |
131 | 139 | ||
140 | __u32 gpc_mask; /* enabled GPCs */ | ||
141 | |||
142 | __u32 sm_arch_sm_version; /* sm version */ | ||
143 | __u32 sm_arch_spa_version; /* sm instruction set */ | ||
144 | __u32 sm_arch_warp_count; | ||
145 | |||
146 | /* IOCTL interface levels by service. -1 if not supported */ | ||
147 | __s16 gpu_ioctl_nr_last; | ||
148 | __s16 tsg_ioctl_nr_last; | ||
149 | __s16 dbg_gpu_ioctl_nr_last; | ||
150 | __s16 ioctl_channel_nr_last; | ||
151 | __s16 as_ioctl_nr_last; | ||
152 | |||
153 | __u8 gpu_va_bit_count; | ||
154 | |||
155 | __u8 reserved; | ||
156 | |||
132 | /* Notes: | 157 | /* Notes: |
133 | - This struct can be safely appended with new fields. However, always | 158 | - This struct can be safely appended with new fields. However, always |
134 | keep the structure size multiple of 8 and make sure that the binary | 159 | keep the structure size multiple of 8 and make sure that the binary |
@@ -197,6 +222,22 @@ struct nvgpu_gpu_open_tsg_args { | |||
197 | __u32 reserved; /* must be zero */ | 222 | __u32 reserved; /* must be zero */ |
198 | }; | 223 | }; |
199 | 224 | ||
225 | struct nvgpu_gpu_get_tpc_masks_args { | ||
226 | /* [in] TPC mask buffer size reserved by userspace. Should be | ||
227 | at least sizeof(__u32) * fls(gpc_mask) to receive TPC | ||
228 | mask for each GPC. | ||
229 | [out] full kernel buffer size | ||
230 | */ | ||
231 | __u32 mask_buf_size; | ||
232 | __u32 reserved; | ||
233 | |||
234 | /* [in] pointer to TPC mask buffer. It will receive one | ||
235 | 32-bit TPC mask per GPC or 0 if GPC is not enabled or | ||
236 | not present. This parameter is ignored if | ||
237 | mask_buf_size is 0. */ | ||
238 | __u64 mask_buf_addr; | ||
239 | }; | ||
240 | |||
200 | #define NVGPU_GPU_IOCTL_ZCULL_GET_CTX_SIZE \ | 241 | #define NVGPU_GPU_IOCTL_ZCULL_GET_CTX_SIZE \ |
201 | _IOR(NVGPU_GPU_IOCTL_MAGIC, 1, struct nvgpu_gpu_zcull_get_ctx_size_args) | 242 | _IOR(NVGPU_GPU_IOCTL_MAGIC, 1, struct nvgpu_gpu_zcull_get_ctx_size_args) |
202 | #define NVGPU_GPU_IOCTL_ZCULL_GET_INFO \ | 243 | #define NVGPU_GPU_IOCTL_ZCULL_GET_INFO \ |
@@ -215,9 +256,11 @@ struct nvgpu_gpu_open_tsg_args { | |||
215 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 8, struct nvgpu_alloc_as_args) | 256 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 8, struct nvgpu_alloc_as_args) |
216 | #define NVGPU_GPU_IOCTL_OPEN_TSG \ | 257 | #define NVGPU_GPU_IOCTL_OPEN_TSG \ |
217 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 9, struct nvgpu_gpu_open_tsg_args) | 258 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 9, struct nvgpu_gpu_open_tsg_args) |
259 | #define NVGPU_GPU_IOCTL_GET_TPC_MASKS \ | ||
260 | _IOWR(NVGPU_GPU_IOCTL_MAGIC, 10, struct nvgpu_gpu_get_tpc_masks_args) | ||
218 | 261 | ||
219 | #define NVGPU_GPU_IOCTL_LAST \ | 262 | #define NVGPU_GPU_IOCTL_LAST \ |
220 | _IOC_NR(NVGPU_GPU_IOCTL_OPEN_TSG) | 263 | _IOC_NR(NVGPU_GPU_IOCTL_GET_TPC_MASKS) |
221 | #define NVGPU_GPU_IOCTL_MAX_ARG_SIZE \ | 264 | #define NVGPU_GPU_IOCTL_MAX_ARG_SIZE \ |
222 | sizeof(struct nvgpu_gpu_prepare_compressible_read_args) | 265 | sizeof(struct nvgpu_gpu_prepare_compressible_read_args) |
223 | 266 | ||