diff options
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/timers.c | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/pmu/pmu_ipc.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/pmu_gm20b.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/timers.h | 8 |
6 files changed, 11 insertions, 19 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/timers.c b/drivers/gpu/nvgpu/common/linux/timers.c index 2953902e..5786b240 100644 --- a/drivers/gpu/nvgpu/common/linux/timers.c +++ b/drivers/gpu/nvgpu/common/linux/timers.c | |||
@@ -54,12 +54,9 @@ static int nvgpu_timeout_is_pre_silicon(struct nvgpu_timeout *timeout) | |||
54 | * | 54 | * |
55 | * If neither %NVGPU_TIMER_CPU_TIMER or %NVGPU_TIMER_RETRY_TIMER is passed then | 55 | * If neither %NVGPU_TIMER_CPU_TIMER or %NVGPU_TIMER_RETRY_TIMER is passed then |
56 | * a CPU timer is used by default. | 56 | * a CPU timer is used by default. |
57 | * | ||
58 | * A negative duration is interpreted as the maximum possible, which for our | ||
59 | * purposes means infinite wait. | ||
60 | */ | 57 | */ |
61 | int nvgpu_timeout_init(struct gk20a *g, struct nvgpu_timeout *timeout, | 58 | int nvgpu_timeout_init(struct gk20a *g, struct nvgpu_timeout *timeout, |
62 | int duration, unsigned long flags) | 59 | u32 duration, unsigned long flags) |
63 | { | 60 | { |
64 | if (flags & ~NVGPU_TIMER_FLAG_MASK) | 61 | if (flags & ~NVGPU_TIMER_FLAG_MASK) |
65 | return -EINVAL; | 62 | return -EINVAL; |
@@ -69,9 +66,6 @@ int nvgpu_timeout_init(struct gk20a *g, struct nvgpu_timeout *timeout, | |||
69 | timeout->g = g; | 66 | timeout->g = g; |
70 | timeout->flags = flags; | 67 | timeout->flags = flags; |
71 | 68 | ||
72 | if (duration < 0) | ||
73 | duration = INT_MAX; | ||
74 | |||
75 | if (flags & NVGPU_TIMER_RETRY_TIMER) | 69 | if (flags & NVGPU_TIMER_RETRY_TIMER) |
76 | timeout->retries.max = duration; | 70 | timeout->retries.max = duration; |
77 | else | 71 | else |
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c b/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c index 0dbc2df3..6dffdf0f 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c | |||
@@ -453,7 +453,7 @@ static int pmu_write_cmd(struct nvgpu_pmu *pmu, struct pmu_cmd *cmd, | |||
453 | nvgpu_log_fn(g, " "); | 453 | nvgpu_log_fn(g, " "); |
454 | 454 | ||
455 | queue = &pmu->queue[queue_id]; | 455 | queue = &pmu->queue[queue_id]; |
456 | nvgpu_timeout_init(g, &timeout, (int)timeout_ms, NVGPU_TIMER_CPU_TIMER); | 456 | nvgpu_timeout_init(g, &timeout, timeout_ms, NVGPU_TIMER_CPU_TIMER); |
457 | 457 | ||
458 | do { | 458 | do { |
459 | err = pmu_queue_open_write(pmu, queue, cmd->hdr.size); | 459 | err = pmu_queue_open_write(pmu, queue, cmd->hdr.size); |
@@ -878,7 +878,7 @@ int pmu_wait_message_cond(struct nvgpu_pmu *pmu, u32 timeout_ms, | |||
878 | struct nvgpu_timeout timeout; | 878 | struct nvgpu_timeout timeout; |
879 | unsigned long delay = GR_IDLE_CHECK_DEFAULT; | 879 | unsigned long delay = GR_IDLE_CHECK_DEFAULT; |
880 | 880 | ||
881 | nvgpu_timeout_init(g, &timeout, (int)timeout_ms, NVGPU_TIMER_CPU_TIMER); | 881 | nvgpu_timeout_init(g, &timeout, timeout_ms, NVGPU_TIMER_CPU_TIMER); |
882 | 882 | ||
883 | do { | 883 | do { |
884 | if (*var == val) | 884 | if (*var == val) |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index f365ac94..dd5f0d17 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -1287,7 +1287,7 @@ struct gk20a { | |||
1287 | static inline unsigned long gk20a_get_gr_idle_timeout(struct gk20a *g) | 1287 | static inline unsigned long gk20a_get_gr_idle_timeout(struct gk20a *g) |
1288 | { | 1288 | { |
1289 | return g->timeouts_enabled ? | 1289 | return g->timeouts_enabled ? |
1290 | g->gr_idle_timeout_default : MAX_SCHEDULE_TIMEOUT; | 1290 | g->gr_idle_timeout_default : ULONG_MAX; |
1291 | } | 1291 | } |
1292 | 1292 | ||
1293 | enum BAR0_DEBUG_OPERATION { | 1293 | enum BAR0_DEBUG_OPERATION { |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index c5dab0b5..4dfb6ee8 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -344,8 +344,7 @@ int gr_gk20a_wait_idle(struct gk20a *g, unsigned long duration_ms, | |||
344 | 344 | ||
345 | gr_engine_id = gk20a_fifo_get_gr_engine_id(g); | 345 | gr_engine_id = gk20a_fifo_get_gr_engine_id(g); |
346 | 346 | ||
347 | nvgpu_timeout_init(g, &timeout, (int)duration_ms, | 347 | nvgpu_timeout_init(g, &timeout, duration_ms, NVGPU_TIMER_CPU_TIMER); |
348 | NVGPU_TIMER_CPU_TIMER); | ||
349 | 348 | ||
350 | do { | 349 | do { |
351 | /* fmodel: host gets fifo_engine_status(gr) from gr | 350 | /* fmodel: host gets fifo_engine_status(gr) from gr |
@@ -398,8 +397,7 @@ int gr_gk20a_wait_fe_idle(struct gk20a *g, unsigned long duration_ms, | |||
398 | 397 | ||
399 | gk20a_dbg_fn(""); | 398 | gk20a_dbg_fn(""); |
400 | 399 | ||
401 | nvgpu_timeout_init(g, &timeout, (int)duration_ms, | 400 | nvgpu_timeout_init(g, &timeout, duration_ms, NVGPU_TIMER_CPU_TIMER); |
402 | NVGPU_TIMER_CPU_TIMER); | ||
403 | 401 | ||
404 | do { | 402 | do { |
405 | val = gk20a_readl(g, gr_status_r()); | 403 | val = gk20a_readl(g, gr_status_r()); |
diff --git a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c index ee55c8ef..0f99c67e 100644 --- a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c | |||
@@ -184,7 +184,7 @@ static int pmu_gm20b_ctx_wait_lsf_ready(struct gk20a *g, u32 timeout_ms, | |||
184 | gk20a_dbg_fn(""); | 184 | gk20a_dbg_fn(""); |
185 | reg = gk20a_readl(g, gr_fecs_ctxsw_mailbox_r(0)); | 185 | reg = gk20a_readl(g, gr_fecs_ctxsw_mailbox_r(0)); |
186 | 186 | ||
187 | nvgpu_timeout_init(g, &timeout, (int)timeout_ms, NVGPU_TIMER_CPU_TIMER); | 187 | nvgpu_timeout_init(g, &timeout, timeout_ms, NVGPU_TIMER_CPU_TIMER); |
188 | 188 | ||
189 | do { | 189 | do { |
190 | reg = gk20a_readl(g, gr_fecs_ctxsw_mailbox_r(0)); | 190 | reg = gk20a_readl(g, gr_fecs_ctxsw_mailbox_r(0)); |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/timers.h b/drivers/gpu/nvgpu/include/nvgpu/timers.h index 5265437e..482f92b7 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/timers.h +++ b/drivers/gpu/nvgpu/include/nvgpu/timers.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -52,8 +52,8 @@ struct nvgpu_timeout { | |||
52 | union { | 52 | union { |
53 | s64 time; | 53 | s64 time; |
54 | struct { | 54 | struct { |
55 | int max; | 55 | u32 max; |
56 | int attempted; | 56 | u32 attempted; |
57 | } retries; | 57 | } retries; |
58 | }; | 58 | }; |
59 | }; | 59 | }; |
@@ -75,7 +75,7 @@ struct nvgpu_timeout { | |||
75 | NVGPU_TIMER_SILENT_TIMEOUT) | 75 | NVGPU_TIMER_SILENT_TIMEOUT) |
76 | 76 | ||
77 | int nvgpu_timeout_init(struct gk20a *g, struct nvgpu_timeout *timeout, | 77 | int nvgpu_timeout_init(struct gk20a *g, struct nvgpu_timeout *timeout, |
78 | int duration, unsigned long flags); | 78 | u32 duration, unsigned long flags); |
79 | int nvgpu_timeout_peek_expired(struct nvgpu_timeout *timeout); | 79 | int nvgpu_timeout_peek_expired(struct nvgpu_timeout *timeout); |
80 | 80 | ||
81 | #define nvgpu_timeout_expired(__timeout) \ | 81 | #define nvgpu_timeout_expired(__timeout) \ |