diff options
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index f36a3eb6..2d09a840 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | |||
@@ -1031,6 +1031,15 @@ static bool gk20a_fifo_handle_mmu_fault(struct gk20a *g) | |||
1031 | } | 1031 | } |
1032 | 1032 | ||
1033 | if (ch) { | 1033 | if (ch) { |
1034 | /* check if engine reset should be deferred */ | ||
1035 | if (gk20a_fifo_should_defer_engine_reset(g, engine_id, &f, fake_fault)) { | ||
1036 | g->fifo.mmu_fault_engines = fault_id; | ||
1037 | |||
1038 | /* handled during channel free */ | ||
1039 | g->fifo.deferred_reset_pending = true; | ||
1040 | } else | ||
1041 | verbose = gk20a_fifo_set_ctx_mmu_error(g, ch); | ||
1042 | |||
1034 | if (ch->in_use) { | 1043 | if (ch->in_use) { |
1035 | /* disable the channel from hw and increment | 1044 | /* disable the channel from hw and increment |
1036 | * syncpoints */ | 1045 | * syncpoints */ |
@@ -1041,15 +1050,6 @@ static bool gk20a_fifo_handle_mmu_fault(struct gk20a *g) | |||
1041 | runlist->active_channels); | 1050 | runlist->active_channels); |
1042 | } | 1051 | } |
1043 | 1052 | ||
1044 | /* check if engine reset should be deferred */ | ||
1045 | if (gk20a_fifo_should_defer_engine_reset(g, engine_id, &f, fake_fault)) { | ||
1046 | g->fifo.mmu_fault_engines = fault_id; | ||
1047 | |||
1048 | /* handled during channel free */ | ||
1049 | g->fifo.deferred_reset_pending = true; | ||
1050 | } else | ||
1051 | verbose = gk20a_fifo_set_ctx_mmu_error(g, ch); | ||
1052 | |||
1053 | } else if (f.inst_ptr == | 1053 | } else if (f.inst_ptr == |
1054 | g->mm.bar1.inst_block.cpu_pa) { | 1054 | g->mm.bar1.inst_block.cpu_pa) { |
1055 | gk20a_err(dev_from_gk20a(g), "mmu fault from bar1"); | 1055 | gk20a_err(dev_from_gk20a(g), "mmu fault from bar1"); |