diff options
-rw-r--r-- | drivers/gpu/nvgpu/ctrl/ctrlvolt.h | 89 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | 5 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm206/bios_gm206.h | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/pmuif/gpmuifvolt.h | 304 |
4 files changed, 385 insertions, 16 deletions
diff --git a/drivers/gpu/nvgpu/ctrl/ctrlvolt.h b/drivers/gpu/nvgpu/ctrl/ctrlvolt.h index 90a3bd89..04c7c4d1 100644 --- a/drivers/gpu/nvgpu/ctrl/ctrlvolt.h +++ b/drivers/gpu/nvgpu/ctrl/ctrlvolt.h | |||
@@ -15,17 +15,94 @@ | |||
15 | #ifndef _ctrlvolt_h_ | 15 | #ifndef _ctrlvolt_h_ |
16 | #define _ctrlvolt_h_ | 16 | #define _ctrlvolt_h_ |
17 | 17 | ||
18 | #define CTRL_VOLT_VOLT_RAIL_MAX_RAILS \ | 18 | #define CTRL_VOLT_VOLT_RAIL_MAX_RAILS \ |
19 | CTRL_BOARDOBJGRP_E32_MAX_OBJECTS | 19 | CTRL_BOARDOBJGRP_E32_MAX_OBJECTS |
20 | 20 | ||
21 | #include "ctrlperf.h" | 21 | #include "ctrlperf.h" |
22 | #include "ctrlboardobj.h" | 22 | #include "ctrlboardobj.h" |
23 | 23 | ||
24 | #define CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES 0x04 | 24 | #define CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES 0x04 |
25 | #define CTRL_VOLT_VOLT_DEV_VID_VSEL_MAX_ENTRIES (8) | 25 | #define CTRL_VOLT_VOLT_DEV_VID_VSEL_MAX_ENTRIES (8) |
26 | #define CTRL_VOLT_DOMAIN_INVALID 0x00 | 26 | #define CTRL_VOLT_DOMAIN_INVALID 0x00 |
27 | #define CTRL_VOLT_DOMAIN_LOGIC 0x01 | 27 | #define CTRL_VOLT_DOMAIN_LOGIC 0x01 |
28 | #define CLK_PROG_VFE_ENTRY_LOGIC 0x00 | 28 | #define CLK_PROG_VFE_ENTRY_LOGIC 0x00 |
29 | |||
30 | /* | ||
31 | * Macros for Voltage Domain HAL. | ||
32 | */ | ||
33 | #define CTRL_VOLT_DOMAIN_HAL_GP10X_SINGLE_RAIL 0x00 | ||
34 | #define CTRL_VOLT_DOMAIN_HAL_GP10X_SPLIT_RAIL 0x01 | ||
35 | |||
36 | /* | ||
37 | * Macros for Voltage Domains. | ||
38 | */ | ||
39 | #define CTRL_VOLT_DOMAIN_INVALID 0x00 | ||
40 | #define CTRL_VOLT_DOMAIN_LOGIC 0x01 | ||
41 | #define CTRL_VOLT_DOMAIN_SRAM 0x02 | ||
42 | |||
43 | /*! | ||
44 | * Special value corresponding to an invalid Voltage Rail Index. | ||
45 | */ | ||
46 | #define CTRL_VOLT_RAIL_INDEX_INVALID \ | ||
47 | CTRL_BOARDOBJ_IDX_INVALID | ||
48 | |||
49 | /*! | ||
50 | * Special value corresponding to an invalid Voltage Device Index. | ||
51 | */ | ||
52 | #define CTRL_VOLT_DEVICE_INDEX_INVALID \ | ||
53 | CTRL_BOARDOBJ_IDX_INVALID | ||
54 | |||
55 | /*! | ||
56 | * Special value corresponding to an invalid Voltage Policy Index. | ||
57 | */ | ||
58 | #define CTRL_VOLT_POLICY_INDEX_INVALID \ | ||
59 | CTRL_BOARDOBJ_IDX_INVALID | ||
60 | |||
61 | enum nv_pmu_pmgr_pwm_source { | ||
62 | NV_PMU_PMGR_PWM_SOURCE_INVALID = 0, | ||
63 | NV_PMU_PMGR_PWM_SOURCE_THERM_VID_PWM_1 = 5, | ||
64 | NV_PMU_PMGR_PWM_SOURCE_RSVD_0 = 7, | ||
65 | NV_PMU_PMGR_PWM_SOURCE_RSVD_1 = 8, | ||
66 | }; | ||
67 | |||
68 | /*! | ||
69 | * Macros for Voltage Device Types. | ||
70 | */ | ||
71 | #define CTRL_VOLT_DEVICE_TYPE_INVALID 0x00 | ||
72 | #define CTRL_VOLT_DEVICE_TYPE_PWM 0x03 | ||
73 | |||
74 | /* | ||
75 | * Macros for Volt Device Operation types. | ||
76 | */ | ||
77 | #define CTRL_VOLT_DEVICE_OPERATION_TYPE_INVALID 0x00 | ||
78 | #define CTRL_VOLT_DEVICE_OPERATION_TYPE_DEFAULT 0x01 | ||
79 | #define CTRL_VOLT_DEVICE_OPERATION_TYPE_LPWR_STEADY_STATE 0x02 | ||
80 | #define CTRL_VOLT_DEVICE_OPERATION_TYPE_LPWR_SLEEP_STATE 0x03 | ||
81 | |||
82 | /*! | ||
83 | * Macros for Voltage Domains. | ||
84 | */ | ||
85 | #define CTRL_VOLT_DOMAIN_INVALID 0x00 | ||
86 | #define CTRL_VOLT_DOMAIN_LOGIC 0x01 | ||
87 | #define CTRL_VOLT_DOMAIN_SRAM 0x02 | ||
88 | |||
89 | /*! | ||
90 | * Macros for Volt Policy types. | ||
91 | * | ||
92 | * Virtual VOLT_POLICY types are indexed starting from 0xFF. | ||
93 | */ | ||
94 | #define CTRL_VOLT_POLICY_TYPE_INVALID 0x00 | ||
95 | #define CTRL_VOLT_POLICY_TYPE_SINGLE_RAIL 0x01 | ||
96 | #define CTRL_VOLT_POLICY_TYPE_SR_MULTI_STEP 0x02 | ||
97 | #define CTRL_VOLT_POLICY_TYPE_SR_SINGLE_STEP 0x03 | ||
98 | #define CTRL_VOLT_POLICY_TYPE_SPLIT_RAIL 0xFE | ||
99 | #define CTRL_VOLT_POLICY_TYPE_UNKNOWN 0xFF | ||
100 | |||
101 | /*! | ||
102 | * Macros for Volt Policy Client types. | ||
103 | */ | ||
104 | #define CTRL_VOLT_POLICY_CLIENT_INVALID 0x00 | ||
105 | #define CTRL_VOLT_POLICY_CLIENT_PERF_CORE_VF_SEQ 0x01 | ||
29 | 106 | ||
30 | struct ctrl_volt_volt_rail_list_item { | 107 | struct ctrl_volt_volt_rail_list_item { |
31 | u8 rail_idx; | 108 | u8 rail_idx; |
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h index 2903cc9d..18f68558 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | |||
@@ -27,6 +27,7 @@ | |||
27 | #include "pmuif/gpmuifclk.h" | 27 | #include "pmuif/gpmuifclk.h" |
28 | #include "pmuif/gpmuifperf.h" | 28 | #include "pmuif/gpmuifperf.h" |
29 | #include "pmuif/gpmuifpmgr.h" | 29 | #include "pmuif/gpmuifpmgr.h" |
30 | #include "pmuif/gpmuifvolt.h" | ||
30 | 31 | ||
31 | /* defined by pmu hw spec */ | 32 | /* defined by pmu hw spec */ |
32 | #define GK20A_PMU_VA_SIZE (512 * 1024 * 1024) | 33 | #define GK20A_PMU_VA_SIZE (512 * 1024 * 1024) |
@@ -181,6 +182,7 @@ struct pmu_ucode_desc_v1 { | |||
181 | #define PMU_UNIT_FECS_MEM_OVERRIDE (0x1E) | 182 | #define PMU_UNIT_FECS_MEM_OVERRIDE (0x1E) |
182 | #define PMU_UNIT_CLK (0x0D) | 183 | #define PMU_UNIT_CLK (0x0D) |
183 | #define PMU_UNIT_PMGR (0x18) | 184 | #define PMU_UNIT_PMGR (0x18) |
185 | #define PMU_UNIT_VOLT (0x0E) | ||
184 | 186 | ||
185 | #define PMU_UNIT_END (0x23) | 187 | #define PMU_UNIT_END (0x23) |
186 | 188 | ||
@@ -359,6 +361,7 @@ struct pmu_cmd { | |||
359 | struct pmu_lrf_tex_ltc_dram_cmd lrf_tex_ltc_dram; | 361 | struct pmu_lrf_tex_ltc_dram_cmd lrf_tex_ltc_dram; |
360 | struct nv_pmu_boardobj_cmd boardobj; | 362 | struct nv_pmu_boardobj_cmd boardobj; |
361 | struct nv_pmu_perf_cmd perf; | 363 | struct nv_pmu_perf_cmd perf; |
364 | struct nv_pmu_volt_cmd volt; | ||
362 | struct nv_pmu_clk_cmd clk; | 365 | struct nv_pmu_clk_cmd clk; |
363 | struct nv_pmu_pmgr_cmd pmgr; | 366 | struct nv_pmu_pmgr_cmd pmgr; |
364 | } cmd; | 367 | } cmd; |
@@ -375,6 +378,7 @@ struct pmu_msg { | |||
375 | struct pmu_lrf_tex_ltc_dram_msg lrf_tex_ltc_dram; | 378 | struct pmu_lrf_tex_ltc_dram_msg lrf_tex_ltc_dram; |
376 | struct nv_pmu_boardobj_msg boardobj; | 379 | struct nv_pmu_boardobj_msg boardobj; |
377 | struct nv_pmu_perf_msg perf; | 380 | struct nv_pmu_perf_msg perf; |
381 | struct nv_pmu_volt_msg volt; | ||
378 | struct nv_pmu_clk_msg clk; | 382 | struct nv_pmu_clk_msg clk; |
379 | struct nv_pmu_pmgr_msg pmgr; | 383 | struct nv_pmu_pmgr_msg pmgr; |
380 | } msg; | 384 | } msg; |
@@ -812,5 +816,4 @@ int gk20a_pmu_vidmem_surface_alloc(struct gk20a *g, struct mem_desc *mem, | |||
812 | int gk20a_pmu_sysmem_surface_alloc(struct gk20a *g, struct mem_desc *mem, | 816 | int gk20a_pmu_sysmem_surface_alloc(struct gk20a *g, struct mem_desc *mem, |
813 | u32 size); | 817 | u32 size); |
814 | 818 | ||
815 | void print_vbios_table(u8 *msg, u8 *buff, int size); | ||
816 | #endif /*__PMU_GK20A_H__*/ | 819 | #endif /*__PMU_GK20A_H__*/ |
diff --git a/drivers/gpu/nvgpu/gm206/bios_gm206.h b/drivers/gpu/nvgpu/gm206/bios_gm206.h index f8187631..53b82485 100644 --- a/drivers/gpu/nvgpu/gm206/bios_gm206.h +++ b/drivers/gpu/nvgpu/gm206/bios_gm206.h | |||
@@ -40,6 +40,9 @@ enum { | |||
40 | POWER_SENSORS_TABLE = 0xA, | 40 | POWER_SENSORS_TABLE = 0xA, |
41 | POWER_CAPPING_TABLE = 0xB, | 41 | POWER_CAPPING_TABLE = 0xB, |
42 | POWER_TOPOLOGY_TABLE = 0xF, | 42 | POWER_TOPOLOGY_TABLE = 0xF, |
43 | VOLTAGE_RAIL_TABLE = 26, | ||
44 | VOLTAGE_DEVICE_TABLE, | ||
45 | VOLTAGE_POLICY_TABLE, | ||
43 | }; | 46 | }; |
44 | 47 | ||
45 | enum { | 48 | enum { |
diff --git a/drivers/gpu/nvgpu/pmuif/gpmuifvolt.h b/drivers/gpu/nvgpu/pmuif/gpmuifvolt.h index c480b1cf..28e27bb7 100644 --- a/drivers/gpu/nvgpu/pmuif/gpmuifvolt.h +++ b/drivers/gpu/nvgpu/pmuif/gpmuifvolt.h | |||
@@ -13,21 +13,307 @@ | |||
13 | #ifndef _GPMUIFVOLT_H_ | 13 | #ifndef _GPMUIFVOLT_H_ |
14 | #define _GPMUIFVOLT_H_ | 14 | #define _GPMUIFVOLT_H_ |
15 | 15 | ||
16 | #include "gk20a/gk20a.h" | ||
17 | #include "gk20a/pmu_gk20a.h" | ||
18 | #include "pmuif/gpmuifboardobj.h" | ||
19 | #include "gk20a/pmu_common.h" | ||
16 | #include "ctrl/ctrlvolt.h" | 20 | #include "ctrl/ctrlvolt.h" |
17 | 21 | ||
22 | #define NV_PMU_VOLT_VALUE_0V_IN_UV (0) | ||
23 | |||
24 | /* ------------- VOLT_RAIL's GRP_SET defines and structures ------------- */ | ||
25 | |||
26 | #define NV_PMU_VOLT_BOARDOBJGRP_CLASS_ID_VOLT_RAIL 0x00 | ||
27 | #define NV_PMU_VOLT_BOARDOBJGRP_CLASS_ID_VOLT_DEVICE 0x01 | ||
28 | #define NV_PMU_VOLT_BOARDOBJGRP_CLASS_ID_VOLT_POLICY 0x02 | ||
29 | |||
30 | |||
31 | struct nv_pmu_volt_volt_rail_boardobjgrp_set_header { | ||
32 | struct nv_pmu_boardobjgrp_e32 super; | ||
33 | }; | ||
34 | |||
35 | struct nv_pmu_volt_volt_rail_boardobj_set { | ||
36 | |||
37 | struct nv_pmu_boardobj super; | ||
38 | u8 rel_limit_vfe_equ_idx; | ||
39 | u8 alt_rel_limit_vfe_equ_idx; | ||
40 | u8 ov_limit_vfe_equ_idx; | ||
41 | u8 vmin_limit_vfe_equ_idx; | ||
42 | u8 volt_margin_limit_vfe_equ_idx; | ||
43 | u8 pwr_equ_idx; | ||
44 | u8 volt_dev_idx_default; | ||
45 | struct ctrl_boardobjgrp_mask_e32 volt_dev_mask; | ||
46 | s32 volt_delta_uv[CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES]; | ||
47 | }; | ||
48 | |||
49 | union nv_pmu_volt_volt_rail_boardobj_set_union { | ||
50 | struct nv_pmu_boardobj board_obj; | ||
51 | struct nv_pmu_volt_volt_rail_boardobj_set super; | ||
52 | }; | ||
53 | |||
54 | NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(volt, volt_rail); | ||
55 | |||
56 | /* ------------ VOLT_DEVICE's GRP_SET defines and structures ------------ */ | ||
57 | |||
58 | struct nv_pmu_volt_volt_device_boardobjgrp_set_header { | ||
59 | struct nv_pmu_boardobjgrp_e32 super; | ||
60 | }; | ||
61 | |||
62 | struct nv_pmu_volt_volt_device_boardobj_set { | ||
63 | struct nv_pmu_boardobj super; | ||
64 | u32 switch_delay_us; | ||
65 | u32 voltage_min_uv; | ||
66 | u32 voltage_max_uv; | ||
67 | u32 volt_step_uv; | ||
68 | }; | ||
69 | |||
70 | struct nv_pmu_volt_volt_device_vid_boardobj_set { | ||
71 | struct nv_pmu_volt_volt_device_boardobj_set super; | ||
72 | s32 voltage_base_uv; | ||
73 | s32 voltage_offset_scale_uv; | ||
74 | u8 gpio_pin[CTRL_VOLT_VOLT_DEV_VID_VSEL_MAX_ENTRIES]; | ||
75 | u8 vsel_mask; | ||
76 | }; | ||
77 | |||
78 | struct nv_pmu_volt_volt_device_pwm_boardobj_set { | ||
79 | struct nv_pmu_volt_volt_device_boardobj_set super; | ||
80 | u32 raw_period; | ||
81 | s32 voltage_base_uv; | ||
82 | s32 voltage_offset_scale_uv; | ||
83 | enum nv_pmu_pmgr_pwm_source pwm_source; | ||
84 | }; | ||
85 | |||
86 | union nv_pmu_volt_volt_device_boardobj_set_union { | ||
87 | struct nv_pmu_boardobj board_obj; | ||
88 | struct nv_pmu_volt_volt_device_boardobj_set super; | ||
89 | struct nv_pmu_volt_volt_device_vid_boardobj_set vid; | ||
90 | struct nv_pmu_volt_volt_device_pwm_boardobj_set pwm; | ||
91 | }; | ||
92 | |||
93 | NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(volt, volt_device); | ||
94 | |||
95 | /* ------------ VOLT_POLICY's GRP_SET defines and structures ------------ */ | ||
96 | struct nv_pmu_volt_volt_policy_boardobjgrp_set_header { | ||
97 | |||
98 | struct nv_pmu_boardobjgrp_e32 super; | ||
99 | }; | ||
100 | |||
101 | struct nv_pmu_volt_volt_policy_boardobj_set { | ||
102 | struct nv_pmu_boardobj super; | ||
103 | }; | ||
104 | struct nv_pmu_volt_volt_policy_sr_boardobj_set { | ||
105 | struct nv_pmu_volt_volt_policy_boardobj_set super; | ||
106 | u8 rail_idx; | ||
107 | }; | ||
108 | |||
109 | struct nv_pmu_volt_volt_policy_splt_r_boardobj_set { | ||
110 | struct nv_pmu_volt_volt_policy_boardobj_set super; | ||
111 | u8 rail_idx_master; | ||
112 | u8 rail_idx_slave; | ||
113 | u8 delta_min_vfe_equ_idx; | ||
114 | u8 delta_max_vfe_equ_idx; | ||
115 | s32 offset_delta_min_uv; | ||
116 | s32 offset_delta_max_uv; | ||
117 | }; | ||
118 | |||
119 | struct nv_pmu_volt_volt_policy_srms_boardobj_set { | ||
120 | struct nv_pmu_volt_volt_policy_splt_r_boardobj_set super; | ||
121 | u16 inter_switch_delayus; | ||
122 | }; | ||
123 | |||
124 | /* sr - > single_rail */ | ||
125 | struct nv_pmu_volt_volt_policy_srss_boardobj_set { | ||
126 | struct nv_pmu_volt_volt_policy_splt_r_boardobj_set super; | ||
127 | }; | ||
128 | |||
129 | union nv_pmu_volt_volt_policy_boardobj_set_union { | ||
130 | struct nv_pmu_boardobj board_obj; | ||
131 | struct nv_pmu_volt_volt_policy_boardobj_set super; | ||
132 | struct nv_pmu_volt_volt_policy_sr_boardobj_set single_rail; | ||
133 | struct nv_pmu_volt_volt_policy_splt_r_boardobj_set split_rail; | ||
134 | struct nv_pmu_volt_volt_policy_srms_boardobj_set | ||
135 | split_rail_m_s; | ||
136 | struct nv_pmu_volt_volt_policy_srss_boardobj_set | ||
137 | split_rail_s_s; | ||
138 | }; | ||
139 | |||
140 | NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(volt, volt_policy); | ||
141 | |||
142 | /* ----------- VOLT_RAIL's GRP_GET_STATUS defines and structures ----------- */ | ||
143 | struct nv_pmu_volt_volt_rail_boardobjgrp_get_status_header { | ||
144 | struct nv_pmu_boardobjgrp_e32 super; | ||
145 | }; | ||
146 | |||
147 | struct nv_pmu_volt_volt_rail_boardobj_get_status { | ||
148 | struct nv_pmu_boardobj_query super; | ||
149 | u32 curr_volt_defaultu_v; | ||
150 | u32 rel_limitu_v; | ||
151 | u32 alt_rel_limitu_v; | ||
152 | u32 ov_limitu_v; | ||
153 | u32 max_limitu_v; | ||
154 | u32 vmin_limitu_v; | ||
155 | s32 volt_margin_limitu_v; | ||
156 | u32 rsvd; | ||
157 | }; | ||
158 | |||
159 | union nv_pmu_volt_volt_rail_boardobj_get_status_union { | ||
160 | struct nv_pmu_boardobj_query board_obj; | ||
161 | struct nv_pmu_volt_volt_rail_boardobj_get_status super; | ||
162 | }; | ||
163 | |||
164 | NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(volt, volt_rail); | ||
165 | |||
166 | /* ---------- VOLT_DEVICE's GRP_GET_STATUS defines and structures ---------- */ | ||
167 | struct nv_pmu_volt_volt_device_boardobjgrp_get_status_header { | ||
168 | struct nv_pmu_boardobjgrp_e32 super; | ||
169 | }; | ||
170 | |||
171 | struct nv_pmu_volt_volt_device_boardobj_get_status { | ||
172 | struct nv_pmu_boardobj_query super; | ||
173 | }; | ||
174 | |||
175 | union nv_pmu_volt_volt_device_boardobj_get_status_union { | ||
176 | struct nv_pmu_boardobj_query board_obj; | ||
177 | struct nv_pmu_volt_volt_device_boardobj_get_status super; | ||
178 | }; | ||
179 | |||
180 | NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(volt, volt_device); | ||
181 | |||
182 | /* ---------- VOLT_POLICY's GRP_GET_STATUS defines and structures ---------- */ | ||
183 | struct nv_pmu_volt_volt_policy_boardobjgrp_get_status_header { | ||
184 | struct nv_pmu_boardobjgrp_e32 super; | ||
185 | }; | ||
186 | |||
187 | struct nv_pmu_volt_volt_policy_boardobj_get_status { | ||
188 | struct nv_pmu_boardobj_query super; | ||
189 | u32 offset_volt_requ_v; | ||
190 | u32 offset_volt_curru_v; | ||
191 | }; | ||
192 | |||
193 | struct nv_pmu_volt_volt_policy_sr_boardobj_get_status { | ||
194 | struct nv_pmu_volt_volt_policy_boardobj_get_status super; | ||
195 | u32 curr_voltu_v; | ||
196 | }; | ||
197 | |||
198 | struct nv_pmu_volt_volt_policy_splt_r_boardobj_get_status { | ||
199 | struct nv_pmu_volt_volt_policy_boardobj_get_status super; | ||
200 | s32 delta_minu_v; | ||
201 | s32 delta_maxu_v; | ||
202 | s32 orig_delta_minu_v; | ||
203 | s32 orig_delta_maxu_v; | ||
204 | u32 curr_volt_masteru_v; | ||
205 | u32 curr_volt_slaveu_v; | ||
206 | bool b_violation; | ||
207 | }; | ||
208 | |||
209 | /* srms -> split_rail_multi_step */ | ||
210 | struct nv_pmu_volt_volt_policy_srms_boardobj_get_status { | ||
211 | struct nv_pmu_volt_volt_policy_splt_r_boardobj_get_status super; | ||
212 | }; | ||
213 | |||
214 | /* srss -> split_rail_single_step */ | ||
215 | struct nv_pmu_volt_volt_policy_srss_boardobj_get_status { | ||
216 | struct nv_pmu_volt_volt_policy_splt_r_boardobj_get_status super; | ||
217 | }; | ||
218 | |||
219 | union nv_pmu_volt_volt_policy_boardobj_get_status_union { | ||
220 | struct nv_pmu_boardobj_query board_obj; | ||
221 | struct nv_pmu_volt_volt_policy_boardobj_get_status super; | ||
222 | struct nv_pmu_volt_volt_policy_sr_boardobj_get_status single_rail; | ||
223 | struct nv_pmu_volt_volt_policy_splt_r_boardobj_get_status split_rail; | ||
224 | struct nv_pmu_volt_volt_policy_srms_boardobj_get_status | ||
225 | split_rail_m_s; | ||
226 | struct nv_pmu_volt_volt_policy_srss_boardobj_get_status | ||
227 | split_rail_s_s; | ||
228 | }; | ||
229 | |||
230 | NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(volt, volt_policy); | ||
231 | |||
232 | struct nv_pmu_volt_policy_voltage_data { | ||
233 | u8 policy_idx; | ||
234 | struct ctrl_perf_volt_rail_list | ||
235 | rail_list; | ||
236 | }; | ||
237 | |||
238 | struct nv_pmu_volt_rail_get_voltage { | ||
239 | u8 rail_idx; | ||
240 | u32 voltage_uv; | ||
241 | }; | ||
242 | |||
243 | #define NV_PMU_VOLT_CMD_ID_BOARDOBJ_GRP_SET (0x00000000) | ||
244 | #define NV_PMU_VOLT_CMD_ID_RPC (0x00000001) | ||
245 | #define NV_PMU_VOLT_CMD_ID_BOARDOBJ_GRP_GET_STATUS (0x00000002) | ||
246 | |||
18 | /*! | 247 | /*! |
19 | * Structure containing the number of voltage rails and the list of rail items | 248 | * PMU VOLT RPC calls. |
20 | * @ref CTRL_PERF_VOLT_RAIL_LIST_ITEM. | ||
21 | */ | 249 | */ |
250 | #define NV_PMU_VOLT_RPC_ID_LOAD (0x00000000) | ||
251 | #define NV_PMU_VOLT_RPC_ID_VOLT_POLICY_SET_VOLTAGE (0x00000002) | ||
252 | #define NV_PMU_VOLT_RPC_ID_VOLT_RAIL_GET_VOLTAGE (0x00000003) | ||
253 | |||
254 | struct nv_pmu_volt_cmd_rpc { | ||
255 | u8 cmd_type; | ||
256 | u8 pad[3]; | ||
257 | struct nv_pmu_allocation request; | ||
258 | }; | ||
259 | |||
260 | #define NV_PMU_VOLT_CMD_RPC_ALLOC_OFFSET \ | ||
261 | offsetof(struct nv_pmu_volt_cmd_rpc, request) | ||
262 | |||
263 | struct nv_pmu_volt_cmd { | ||
264 | union { | ||
265 | u8 cmd_type; | ||
266 | struct nv_pmu_boardobj_cmd_grp grp_set; | ||
267 | struct nv_pmu_volt_cmd_rpc rpc; | ||
268 | struct nv_pmu_boardobj_cmd_grp grp_get_status; | ||
269 | }; | ||
270 | }; | ||
271 | |||
272 | struct nv_pmu_volt_rpc { | ||
273 | u8 function; | ||
274 | bool b_supported; | ||
275 | bool b_success; | ||
276 | flcn_status flcn_status; | ||
277 | union { | ||
278 | struct nv_pmu_volt_policy_voltage_data volt_policy_voltage_data; | ||
279 | struct nv_pmu_volt_rail_get_voltage volt_rail_get_voltage; | ||
280 | } params; | ||
281 | }; | ||
282 | |||
283 | /*! | ||
284 | * VOLT MSG ID definitions | ||
285 | */ | ||
286 | #define NV_PMU_VOLT_MSG_ID_BOARDOBJ_GRP_SET (0x00000000) | ||
287 | #define NV_PMU_VOLT_MSG_ID_RPC (0x00000001) | ||
288 | #define NV_PMU_VOLT_MSG_ID_BOARDOBJ_GRP_GET_STATUS (0x00000002) | ||
289 | |||
290 | /*! | ||
291 | * Message carrying the result of the VOLT RPC execution. | ||
292 | */ | ||
293 | struct nv_pmu_volt_msg_rpc { | ||
294 | u8 msg_type; | ||
295 | u8 rsvd[3]; | ||
296 | struct nv_pmu_allocation response; | ||
297 | }; | ||
298 | |||
299 | #define NV_PMU_VOLT_MSG_RPC_ALLOC_OFFSET \ | ||
300 | offsetof(struct nv_pmu_volt_msg_rpc, response) | ||
301 | |||
302 | struct nv_pmu_volt_msg { | ||
303 | union { | ||
304 | u8 msg_type; | ||
305 | struct nv_pmu_boardobj_msg_grp grp_set; | ||
306 | struct nv_pmu_volt_msg_rpc rpc; | ||
307 | struct nv_pmu_boardobj_msg_grp grp_get_status; | ||
308 | }; | ||
309 | }; | ||
310 | |||
311 | #define NV_PMU_VF_INJECT_MAX_VOLT_RAILS (2) | ||
312 | |||
22 | struct nv_pmu_volt_volt_rail_list { | 313 | struct nv_pmu_volt_volt_rail_list { |
23 | /*! | ||
24 | * Number of VOLT_RAILs that require the voltage change. | ||
25 | */ | ||
26 | u8 num_rails; | 314 | u8 num_rails; |
27 | /*! | 315 | struct ctrl_perf_volt_rail_list_item |
28 | * List of @ref CTRL_PERF_VOLT_RAIL_LIST_ITEM entries. | 316 | rails[NV_PMU_VF_INJECT_MAX_VOLT_RAILS]; |
29 | */ | ||
30 | struct ctrl_perf_volt_rail_list_item rails[2]; | ||
31 | }; | 317 | }; |
32 | 318 | ||
33 | #endif /* _GPMUIFVOLT_H_*/ | 319 | #endif /* _GPMUIFVOLT_H_*/ |