diff options
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 16 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 14 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/gr_gp10b.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 1 |
7 files changed, 34 insertions, 4 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index adc630e6..8ac82428 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -415,6 +415,9 @@ struct gpu_ops { | |||
415 | u32 gpc, u32 tpc, u32 sm); | 415 | u32 gpc, u32 tpc, u32 sm); |
416 | void (*resume_all_sms)(struct gk20a *g); | 416 | void (*resume_all_sms)(struct gk20a *g); |
417 | void (*disable_rd_coalesce)(struct gk20a *g); | 417 | void (*disable_rd_coalesce)(struct gk20a *g); |
418 | void (*init_ctxsw_hdr_data)(struct gk20a *g, | ||
419 | struct nvgpu_mem *mem); | ||
420 | |||
418 | } gr; | 421 | } gr; |
419 | struct { | 422 | struct { |
420 | void (*init_hw)(struct gk20a *g); | 423 | void (*init_hw)(struct gk20a *g); |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 833a3ab9..82c9fa89 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -1821,6 +1821,15 @@ cleanup_pm_buf: | |||
1821 | return ret; | 1821 | return ret; |
1822 | } | 1822 | } |
1823 | 1823 | ||
1824 | void gk20a_gr_init_ctxsw_hdr_data(struct gk20a *g, | ||
1825 | struct nvgpu_mem *mem) | ||
1826 | { | ||
1827 | nvgpu_mem_wr(g, mem, | ||
1828 | ctxsw_prog_main_image_num_save_ops_o(), 0); | ||
1829 | nvgpu_mem_wr(g, mem, | ||
1830 | ctxsw_prog_main_image_num_restore_ops_o(), 0); | ||
1831 | } | ||
1832 | |||
1824 | /* load saved fresh copy of gloden image into channel gr_ctx */ | 1833 | /* load saved fresh copy of gloden image into channel gr_ctx */ |
1825 | int gr_gk20a_load_golden_ctx_image(struct gk20a *g, | 1834 | int gr_gk20a_load_golden_ctx_image(struct gk20a *g, |
1826 | struct channel_gk20a *c) | 1835 | struct channel_gk20a *c) |
@@ -1860,12 +1869,11 @@ int gr_gk20a_load_golden_ctx_image(struct gk20a *g, | |||
1860 | nvgpu_mem_wr_n(g, mem, 0, | 1869 | nvgpu_mem_wr_n(g, mem, 0, |
1861 | gr->ctx_vars.local_golden_image, | 1870 | gr->ctx_vars.local_golden_image, |
1862 | gr->ctx_vars.golden_image_size); | 1871 | gr->ctx_vars.golden_image_size); |
1863 | nvgpu_mem_wr(g, mem, | ||
1864 | ctxsw_prog_main_image_num_save_ops_o(), 0); | ||
1865 | nvgpu_mem_wr(g, mem, | ||
1866 | ctxsw_prog_main_image_num_restore_ops_o(), 0); | ||
1867 | } | 1872 | } |
1868 | 1873 | ||
1874 | if (g->ops.gr.init_ctxsw_hdr_data) | ||
1875 | g->ops.gr.init_ctxsw_hdr_data(g, mem); | ||
1876 | |||
1869 | if (g->ops.gr.enable_cde_in_fecs && c->cde) | 1877 | if (g->ops.gr.enable_cde_in_fecs && c->cde) |
1870 | g->ops.gr.enable_cde_in_fecs(g, mem); | 1878 | g->ops.gr.enable_cde_in_fecs(g, mem); |
1871 | 1879 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index c69d9df9..2d2bd15e 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h | |||
@@ -737,6 +737,8 @@ void gk20a_gr_get_esr_sm_sel(struct gk20a *g, u32 gpc, u32 tpc, | |||
737 | void gk20a_gr_init_ovr_sm_dsm_perf(void); | 737 | void gk20a_gr_init_ovr_sm_dsm_perf(void); |
738 | void gk20a_gr_get_ovr_perf_regs(struct gk20a *g, u32 *num_ovr_perf_regs, | 738 | void gk20a_gr_get_ovr_perf_regs(struct gk20a *g, u32 *num_ovr_perf_regs, |
739 | u32 **ovr_perf_regs); | 739 | u32 **ovr_perf_regs); |
740 | void gk20a_gr_init_ctxsw_hdr_data(struct gk20a *g, | ||
741 | struct nvgpu_mem *mem); | ||
740 | 742 | ||
741 | static inline const char *gr_gk20a_graphics_preempt_mode_name(u32 graphics_preempt_mode) | 743 | static inline const char *gr_gk20a_graphics_preempt_mode_name(u32 graphics_preempt_mode) |
742 | { | 744 | { |
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index 9ff9fdd7..f71c70f5 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c | |||
@@ -283,6 +283,7 @@ static const struct gpu_ops gm20b_ops = { | |||
283 | .init_ovr_sm_dsm_perf = gk20a_gr_init_ovr_sm_dsm_perf, | 283 | .init_ovr_sm_dsm_perf = gk20a_gr_init_ovr_sm_dsm_perf, |
284 | .get_ovr_perf_regs = gk20a_gr_get_ovr_perf_regs, | 284 | .get_ovr_perf_regs = gk20a_gr_get_ovr_perf_regs, |
285 | .disable_rd_coalesce = gm20a_gr_disable_rd_coalesce, | 285 | .disable_rd_coalesce = gm20a_gr_disable_rd_coalesce, |
286 | .init_ctxsw_hdr_data = gk20a_gr_init_ctxsw_hdr_data, | ||
286 | }, | 287 | }, |
287 | .fb = { | 288 | .fb = { |
288 | .reset = fb_gk20a_reset, | 289 | .reset = fb_gk20a_reset, |
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index ee7118e7..d3e45f55 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c | |||
@@ -2379,3 +2379,17 @@ int gr_gp10b_set_czf_bypass(struct gk20a *g, struct channel_gk20a *ch) | |||
2379 | 2379 | ||
2380 | return __gr_gk20a_exec_ctx_ops(ch, &ops, 1, 1, 0, false); | 2380 | return __gr_gk20a_exec_ctx_ops(ch, &ops, 1, 1, 0, false); |
2381 | } | 2381 | } |
2382 | |||
2383 | void gr_gp10b_init_ctxsw_hdr_data(struct gk20a *g, struct nvgpu_mem *mem) | ||
2384 | { | ||
2385 | gk20a_gr_init_ctxsw_hdr_data(g, mem); | ||
2386 | |||
2387 | nvgpu_mem_wr(g, mem, | ||
2388 | ctxsw_prog_main_image_num_wfi_save_ops_o(), 0); | ||
2389 | nvgpu_mem_wr(g, mem, | ||
2390 | ctxsw_prog_main_image_num_cta_save_ops_o(), 0); | ||
2391 | nvgpu_mem_wr(g, mem, | ||
2392 | ctxsw_prog_main_image_num_gfxp_save_ops_o(), 0); | ||
2393 | nvgpu_mem_wr(g, mem, | ||
2394 | ctxsw_prog_main_image_num_cilp_save_ops_o(), 0); | ||
2395 | } | ||
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h index ce1ca01f..4d7673da 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h | |||
@@ -133,6 +133,7 @@ int gr_gp10b_init_preemption_state(struct gk20a *g); | |||
133 | void gr_gp10b_set_preemption_buffer_va(struct gk20a *g, | 133 | void gr_gp10b_set_preemption_buffer_va(struct gk20a *g, |
134 | struct nvgpu_mem *mem, u64 gpu_va); | 134 | struct nvgpu_mem *mem, u64 gpu_va); |
135 | int gr_gp10b_set_czf_bypass(struct gk20a *g, struct channel_gk20a *ch); | 135 | int gr_gp10b_set_czf_bypass(struct gk20a *g, struct channel_gk20a *ch); |
136 | void gr_gp10b_init_ctxsw_hdr_data(struct gk20a *g, struct nvgpu_mem *mem); | ||
136 | 137 | ||
137 | struct gr_t18x { | 138 | struct gr_t18x { |
138 | struct { | 139 | struct { |
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 4dae79e1..018f30d9 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c | |||
@@ -302,6 +302,7 @@ static const struct gpu_ops gp10b_ops = { | |||
302 | .set_bes_crop_debug3 = gr_gp10b_set_bes_crop_debug3, | 302 | .set_bes_crop_debug3 = gr_gp10b_set_bes_crop_debug3, |
303 | .create_gr_sysfs = gr_gp10b_create_sysfs, | 303 | .create_gr_sysfs = gr_gp10b_create_sysfs, |
304 | .set_ctxsw_preemption_mode = gr_gp10b_set_ctxsw_preemption_mode, | 304 | .set_ctxsw_preemption_mode = gr_gp10b_set_ctxsw_preemption_mode, |
305 | .init_ctxsw_hdr_data = gr_gp10b_init_ctxsw_hdr_data, | ||
305 | }, | 306 | }, |
306 | .fb = { | 307 | .fb = { |
307 | .reset = fb_gk20a_reset, | 308 | .reset = fb_gk20a_reset, |