diff options
-rw-r--r-- | drivers/gpu/nvgpu/clk/clk_arb.c | 5 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/clk_gp106.c | 59 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/clk_gp106.h | 7 |
3 files changed, 56 insertions, 15 deletions
diff --git a/drivers/gpu/nvgpu/clk/clk_arb.c b/drivers/gpu/nvgpu/clk/clk_arb.c index f868100b..1f7c2aea 100644 --- a/drivers/gpu/nvgpu/clk/clk_arb.c +++ b/drivers/gpu/nvgpu/clk/clk_arb.c | |||
@@ -925,8 +925,9 @@ int nvgpu_clk_arb_get_arbiter_actual_mhz(struct gk20a *g, | |||
925 | int nvgpu_clk_arb_get_arbiter_effective_mhz(struct gk20a *g, | 925 | int nvgpu_clk_arb_get_arbiter_effective_mhz(struct gk20a *g, |
926 | u32 api_domain, u16 *freq_mhz) | 926 | u32 api_domain, u16 *freq_mhz) |
927 | { | 927 | { |
928 | /* TODO: measure clocks from counters */ | 928 | |
929 | return nvgpu_clk_arb_get_arbiter_actual_mhz(g, api_domain, freq_mhz); | 929 | *freq_mhz = g->ops.clk.get_rate(g, api_domain); |
930 | return 0; | ||
930 | } | 931 | } |
931 | 932 | ||
932 | int nvgpu_clk_arb_get_arbiter_clk_range(struct gk20a *g, u32 api_domain, | 933 | int nvgpu_clk_arb_get_arbiter_clk_range(struct gk20a *g, u32 api_domain, |
diff --git a/drivers/gpu/nvgpu/gp106/clk_gp106.c b/drivers/gpu/nvgpu/gp106/clk_gp106.c index 85dde69f..2a32690d 100644 --- a/drivers/gpu/nvgpu/gp106/clk_gp106.c +++ b/drivers/gpu/nvgpu/gp106/clk_gp106.c | |||
@@ -39,10 +39,37 @@ static int clk_gp106_debugfs_init(struct gk20a *g); | |||
39 | #define NUM_NAMEMAPS 4 | 39 | #define NUM_NAMEMAPS 4 |
40 | #define XTAL4X_KHZ 108000 | 40 | #define XTAL4X_KHZ 108000 |
41 | 41 | ||
42 | |||
43 | static u32 gp106_get_rate_cntr(struct gk20a *g, struct namemap_cfg *); | ||
44 | static u16 gp106_clk_get_rate(struct gk20a *g, u32 api_domain); | ||
42 | static u32 gp106_crystal_clk_hz(struct gk20a *g) | 45 | static u32 gp106_crystal_clk_hz(struct gk20a *g) |
43 | { | 46 | { |
44 | return (XTAL4X_KHZ * 1000); | 47 | return (XTAL4X_KHZ * 1000); |
45 | } | 48 | } |
49 | |||
50 | static u16 gp106_clk_get_rate(struct gk20a *g, u32 api_domain) | ||
51 | { | ||
52 | struct clk_gk20a *clk = &g->clk; | ||
53 | u32 freq_khz; | ||
54 | int i; | ||
55 | struct namemap_cfg *c = NULL; | ||
56 | |||
57 | for (i = 0; i < clk->namemap_num; i++) { | ||
58 | if (api_domain == clk->namemap_xlat_table[i]) { | ||
59 | c = &clk->clk_namemap[i]; | ||
60 | break; | ||
61 | } | ||
62 | } | ||
63 | |||
64 | if (!c) | ||
65 | return 0; | ||
66 | |||
67 | freq_khz = c->is_counter ? c->scale * gp106_get_rate_cntr(g, c) : | ||
68 | 0; /* TODO: PLL read */ | ||
69 | |||
70 | return (u16) freq_khz/1000; | ||
71 | } | ||
72 | |||
46 | static int gp106_init_clk_support(struct gk20a *g) { | 73 | static int gp106_init_clk_support(struct gk20a *g) { |
47 | struct clk_gk20a *clk = &g->clk; | 74 | struct clk_gk20a *clk = &g->clk; |
48 | u32 err = 0; | 75 | u32 err = 0; |
@@ -57,6 +84,14 @@ static int gp106_init_clk_support(struct gk20a *g) { | |||
57 | if (!clk->clk_namemap) | 84 | if (!clk->clk_namemap) |
58 | return -ENOMEM; | 85 | return -ENOMEM; |
59 | 86 | ||
87 | clk->namemap_xlat_table = kcalloc(NUM_NAMEMAPS, sizeof(u32), | ||
88 | GFP_KERNEL); | ||
89 | |||
90 | if (!clk->namemap_xlat_table) { | ||
91 | kfree(clk->clk_namemap); | ||
92 | return -ENOMEM; | ||
93 | } | ||
94 | |||
60 | clk->clk_namemap[0] = (struct namemap_cfg) { | 95 | clk->clk_namemap[0] = (struct namemap_cfg) { |
61 | .namemap = CLK_NAMEMAP_INDEX_GPC2CLK, | 96 | .namemap = CLK_NAMEMAP_INDEX_GPC2CLK, |
62 | .is_enable = 1, | 97 | .is_enable = 1, |
@@ -66,8 +101,10 @@ static int gp106_init_clk_support(struct gk20a *g) { | |||
66 | .cntr.reg_ctrl_idx = | 101 | .cntr.reg_ctrl_idx = |
67 | trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_source_gpc2clk_f(), | 102 | trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_source_gpc2clk_f(), |
68 | .cntr.reg_cntr_addr = trim_gpc_bcast_clk_cntr_ncgpcclk_cnt_r(), | 103 | .cntr.reg_cntr_addr = trim_gpc_bcast_clk_cntr_ncgpcclk_cnt_r(), |
69 | .name = "gpc2clk" | 104 | .name = "gpc2clk", |
105 | .scale = 1 | ||
70 | }; | 106 | }; |
107 | clk->namemap_xlat_table[0] = CTRL_CLK_DOMAIN_GPC2CLK; | ||
71 | clk->clk_namemap[1] = (struct namemap_cfg) { | 108 | clk->clk_namemap[1] = (struct namemap_cfg) { |
72 | .namemap = CLK_NAMEMAP_INDEX_SYS2CLK, | 109 | .namemap = CLK_NAMEMAP_INDEX_SYS2CLK, |
73 | .is_enable = 1, | 110 | .is_enable = 1, |
@@ -76,8 +113,10 @@ static int gp106_init_clk_support(struct gk20a *g) { | |||
76 | .cntr.reg_ctrl_addr = trim_sys_clk_cntr_ncsyspll_cfg_r(), | 113 | .cntr.reg_ctrl_addr = trim_sys_clk_cntr_ncsyspll_cfg_r(), |
77 | .cntr.reg_ctrl_idx = trim_sys_clk_cntr_ncsyspll_cfg_source_sys2clk_f(), | 114 | .cntr.reg_ctrl_idx = trim_sys_clk_cntr_ncsyspll_cfg_source_sys2clk_f(), |
78 | .cntr.reg_cntr_addr = trim_sys_clk_cntr_ncsyspll_cnt_r(), | 115 | .cntr.reg_cntr_addr = trim_sys_clk_cntr_ncsyspll_cnt_r(), |
79 | .name = "sys2clk" | 116 | .name = "sys2clk", |
117 | .scale = 1 | ||
80 | }; | 118 | }; |
119 | clk->namemap_xlat_table[1] = CTRL_CLK_DOMAIN_SYS2CLK; | ||
81 | clk->clk_namemap[2] = (struct namemap_cfg) { | 120 | clk->clk_namemap[2] = (struct namemap_cfg) { |
82 | .namemap = CLK_NAMEMAP_INDEX_XBAR2CLK, | 121 | .namemap = CLK_NAMEMAP_INDEX_XBAR2CLK, |
83 | .is_enable = 1, | 122 | .is_enable = 1, |
@@ -86,8 +125,10 @@ static int gp106_init_clk_support(struct gk20a *g) { | |||
86 | .cntr.reg_ctrl_addr = trim_sys_clk_cntr_ncltcpll_cfg_r(), | 125 | .cntr.reg_ctrl_addr = trim_sys_clk_cntr_ncltcpll_cfg_r(), |
87 | .cntr.reg_ctrl_idx = trim_sys_clk_cntr_ncltcpll_cfg_source_xbar2clk_f(), | 126 | .cntr.reg_ctrl_idx = trim_sys_clk_cntr_ncltcpll_cfg_source_xbar2clk_f(), |
88 | .cntr.reg_cntr_addr = trim_sys_clk_cntr_ncltcpll_cnt_r(), | 127 | .cntr.reg_cntr_addr = trim_sys_clk_cntr_ncltcpll_cnt_r(), |
89 | .name = "xbar2clk" | 128 | .name = "xbar2clk", |
129 | .scale = 1 | ||
90 | }; | 130 | }; |
131 | clk->namemap_xlat_table[2] = CTRL_CLK_DOMAIN_XBAR2CLK; | ||
91 | clk->clk_namemap[3] = (struct namemap_cfg) { | 132 | clk->clk_namemap[3] = (struct namemap_cfg) { |
92 | .namemap = CLK_NAMEMAP_INDEX_DRAMCLK, | 133 | .namemap = CLK_NAMEMAP_INDEX_DRAMCLK, |
93 | .is_enable = 1, | 134 | .is_enable = 1, |
@@ -97,8 +138,10 @@ static int gp106_init_clk_support(struct gk20a *g) { | |||
97 | .cntr.reg_ctrl_idx = | 138 | .cntr.reg_ctrl_idx = |
98 | trim_fbpa_bcast_clk_cntr_ncltcclk_cfg_source_dramdiv4_rec_clk1_f(), | 139 | trim_fbpa_bcast_clk_cntr_ncltcclk_cfg_source_dramdiv4_rec_clk1_f(), |
99 | .cntr.reg_cntr_addr = trim_fbpa_bcast_clk_cntr_ncltcclk_cnt_r(), | 140 | .cntr.reg_cntr_addr = trim_fbpa_bcast_clk_cntr_ncltcclk_cnt_r(), |
100 | .name = "dramdiv2_rec_clk1" | 141 | .name = "dramdiv2_rec_clk1", |
142 | .scale = 2 | ||
101 | }; | 143 | }; |
144 | clk->namemap_xlat_table[3] = CTRL_CLK_DOMAIN_MCLK; | ||
102 | 145 | ||
103 | clk->namemap_num = NUM_NAMEMAPS; | 146 | clk->namemap_num = NUM_NAMEMAPS; |
104 | 147 | ||
@@ -113,10 +156,6 @@ static int gp106_init_clk_support(struct gk20a *g) { | |||
113 | return err; | 156 | return err; |
114 | } | 157 | } |
115 | 158 | ||
116 | #ifdef CONFIG_DEBUG_FS | ||
117 | typedef struct namemap_cfg namemap_cfg_t; | ||
118 | static u32 gp106_get_rate_cntr(struct gk20a *, struct namemap_cfg *); | ||
119 | |||
120 | static u32 gp106_get_rate_cntr(struct gk20a *g, struct namemap_cfg *c) { | 159 | static u32 gp106_get_rate_cntr(struct gk20a *g, struct namemap_cfg *c) { |
121 | u32 save_reg; | 160 | u32 save_reg; |
122 | u32 retries; | 161 | u32 retries; |
@@ -180,6 +219,7 @@ read_err: | |||
180 | 219 | ||
181 | } | 220 | } |
182 | 221 | ||
222 | #ifdef CONFIG_DEBUG_FS | ||
183 | static int gp106_get_rate_show(void *data , u64 *val) { | 223 | static int gp106_get_rate_show(void *data , u64 *val) { |
184 | struct namemap_cfg *c = (struct namemap_cfg *) data; | 224 | struct namemap_cfg *c = (struct namemap_cfg *) data; |
185 | struct gk20a *g = c->g; | 225 | struct gk20a *g = c->g; |
@@ -222,12 +262,11 @@ err_out: | |||
222 | debugfs_remove_recursive(clocks_root); | 262 | debugfs_remove_recursive(clocks_root); |
223 | return -ENOMEM; | 263 | return -ENOMEM; |
224 | } | 264 | } |
225 | |||
226 | #endif /* CONFIG_DEBUG_FS */ | 265 | #endif /* CONFIG_DEBUG_FS */ |
227 | 266 | ||
228 | void gp106_init_clk_ops(struct gpu_ops *gops) { | 267 | void gp106_init_clk_ops(struct gpu_ops *gops) { |
229 | gops->clk.init_clk_support = gp106_init_clk_support; | 268 | gops->clk.init_clk_support = gp106_init_clk_support; |
230 | gops->clk.get_crystal_clk_hz = gp106_crystal_clk_hz; | 269 | gops->clk.get_crystal_clk_hz = gp106_crystal_clk_hz; |
270 | gops->clk.get_rate = gp106_clk_get_rate; | ||
231 | } | 271 | } |
232 | 272 | ||
233 | |||
diff --git a/drivers/gpu/nvgpu/gp106/clk_gp106.h b/drivers/gpu/nvgpu/gp106/clk_gp106.h index a50819aa..7df4b974 100644 --- a/drivers/gpu/nvgpu/gp106/clk_gp106.h +++ b/drivers/gpu/nvgpu/gp106/clk_gp106.h | |||
@@ -26,9 +26,9 @@ | |||
26 | #define CLK_DEFAULT_CNTRL_SETTLE_RETRIES 10 | 26 | #define CLK_DEFAULT_CNTRL_SETTLE_RETRIES 10 |
27 | #define CLK_DEFAULT_CNTRL_SETTLE_USECS 5 | 27 | #define CLK_DEFAULT_CNTRL_SETTLE_USECS 5 |
28 | 28 | ||
29 | #define XTAL_CNTR_CLKS 2700 /* 100usec at 27KHz XTAL */ | 29 | #define XTAL_CNTR_CLKS 27000 /* 1000usec at 27KHz XTAL */ |
30 | #define XTAL_CNTR_DELAY 110 /* leave 10 extra usec */ | 30 | #define XTAL_CNTR_DELAY 1000 /* we need acuracy up to the ms */ |
31 | #define XTAL_SCALE_TO_KHZ 10 | 31 | #define XTAL_SCALE_TO_KHZ 1 |
32 | 32 | ||
33 | 33 | ||
34 | 34 | ||
@@ -47,6 +47,7 @@ struct namemap_cfg { | |||
47 | /* Todo */ | 47 | /* Todo */ |
48 | } pll; | 48 | } pll; |
49 | }; | 49 | }; |
50 | u32 scale; | ||
50 | char name[24]; | 51 | char name[24]; |
51 | }; | 52 | }; |
52 | 53 | ||