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-rw-r--r--drivers/gpu/nvgpu/gp10b/mm_gp10b.c21
1 files changed, 10 insertions, 11 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c
index b998ed4d..1aba16c4 100644
--- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c
@@ -170,6 +170,7 @@ static int update_gmmu_pde3_locked(struct vm_gk20a *vm,
170 170
171 pde_v[0] |= gmmu_new_pde_aperture_video_memory_f(); 171 pde_v[0] |= gmmu_new_pde_aperture_video_memory_f();
172 pde_v[0] |= gmmu_new_pde_address_sys_f(u64_lo32(pte_addr)); 172 pde_v[0] |= gmmu_new_pde_address_sys_f(u64_lo32(pte_addr));
173 pde_v[0] |= gmmu_new_pde_vol_true_f();
173 174
174 pde = pde3_from_index(parent, i); 175 pde = pde3_from_index(parent, i);
175 176
@@ -259,24 +260,22 @@ static int update_gmmu_pte_locked(struct vm_gk20a *vm,
259 260
260 if (*iova) { 261 if (*iova) {
261 if (unmapped_pte) 262 if (unmapped_pte)
262 pte_w[0] = gmmu_new_pte_valid_false_f() | 263 pte_w[0] = gmmu_new_pte_valid_false_f();
263 gmmu_new_pte_address_sys_f(*iova
264 >> gmmu_new_pte_address_shift_v());
265 else 264 else
266 pte_w[0] = gmmu_new_pte_valid_true_f() | 265 pte_w[0] = gmmu_new_pte_valid_true_f();
267 gmmu_new_pte_address_sys_f(*iova 266 pte_w[0] |= gmmu_new_pte_aperture_video_memory_f() |
268 >> gmmu_new_pte_address_shift_v()); 267 gmmu_new_pte_address_sys_f(*iova
268 >> gmmu_new_pte_address_shift_v());
269 269
270 pte_w[1] = gmmu_new_pte_aperture_video_memory_f() | 270 pte_w[1] = gmmu_new_pte_kind_f(kind_v) |
271 gmmu_new_pte_kind_f(kind_v) | 271 gmmu_new_pte_comptagline_f(*ctag / SZ_128K);
272 gmmu_new_pte_comptagline_f(*ctag / SZ_128K);
273 272
274 if (rw_flag == gk20a_mem_flag_read_only) 273 if (rw_flag == gk20a_mem_flag_read_only)
275 pte_w[0] |= gmmu_new_pte_read_only_true_f(); 274 pte_w[0] |= gmmu_new_pte_read_only_true_f();
276 if (unmapped_pte && !cacheable) 275 if (unmapped_pte && !cacheable)
277 pte_w[0] |= gmmu_new_pte_read_only_true_f(); 276 pte_w[0] |= gmmu_new_pte_read_only_true_f();
278 else if (!cacheable) 277 else if (!cacheable)
279 pte_w[1] |= gmmu_new_pte_vol_true_f(); 278 pte_w[0] |= gmmu_new_pte_vol_true_f();
280 279
281 gk20a_dbg(gpu_dbg_pte, "pte=%d iova=0x%llx kind=%d" 280 gk20a_dbg(gpu_dbg_pte, "pte=%d iova=0x%llx kind=%d"
282 " ctag=%d vol=%d" 281 " ctag=%d vol=%d"
@@ -289,7 +288,7 @@ static int update_gmmu_pte_locked(struct vm_gk20a *vm,
289 *ctag += page_size; 288 *ctag += page_size;
290 } else if (sparse) { 289 } else if (sparse) {
291 pte_w[0] = gmmu_new_pte_valid_false_f(); 290 pte_w[0] = gmmu_new_pte_valid_false_f();
292 pte_w[1] |= gmmu_new_pte_vol_true_f(); 291 pte_w[0] |= gmmu_new_pte_vol_true_f();
293 } else { 292 } else {
294 gk20a_dbg(gpu_dbg_pte, "pte_cur=%d [0x0,0x0]", i); 293 gk20a_dbg(gpu_dbg_pte, "pte_cur=%d [0x0,0x0]", i);
295 } 294 }