diff options
-rw-r--r-- | drivers/gpu/nvgpu/common/fb/fb_gv100.c | 20 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/acr_gm20b.c | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/pmu_gm20b.c | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/pmu_gm20b.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/hal_gp106.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/hal_gv100.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 1 |
10 files changed, 29 insertions, 12 deletions
diff --git a/drivers/gpu/nvgpu/common/fb/fb_gv100.c b/drivers/gpu/nvgpu/common/fb/fb_gv100.c index ce51a2c6..848d6efb 100644 --- a/drivers/gpu/nvgpu/common/fb/fb_gv100.c +++ b/drivers/gpu/nvgpu/common/fb/fb_gv100.c | |||
@@ -104,11 +104,20 @@ void gv100_fb_disable_hub_intr(struct gk20a *g) | |||
104 | * @brief Patch signatures into ucode image | 104 | * @brief Patch signatures into ucode image |
105 | */ | 105 | */ |
106 | static int gv100_fb_acr_ucode_patch_sig(struct gk20a *g, | 106 | static int gv100_fb_acr_ucode_patch_sig(struct gk20a *g, |
107 | unsigned int *p_img, | 107 | u32 *p_img, |
108 | unsigned int *p_sig, | 108 | u32 *p_prod_sig, |
109 | unsigned int *p_patch_loc, | 109 | u32 *p_dbg_sig, |
110 | unsigned int *p_patch_ind) | 110 | u32 *p_patch_loc, |
111 | u32 *p_patch_ind) | ||
111 | { | 112 | { |
113 | u32 *p_sig; | ||
114 | |||
115 | if (!g->ops.pmu.is_debug_mode_enabled(g)) { | ||
116 | p_sig = p_prod_sig; | ||
117 | } else { | ||
118 | p_sig = p_dbg_sig; | ||
119 | } | ||
120 | |||
112 | /* Patching logic. We have just one location to patch. */ | 121 | /* Patching logic. We have just one location to patch. */ |
113 | p_img[(*p_patch_loc>>2)] = p_sig[(*p_patch_ind<<2)]; | 122 | p_img[(*p_patch_loc>>2)] = p_sig[(*p_patch_ind<<2)]; |
114 | p_img[(*p_patch_loc>>2)+1U] = p_sig[(*p_patch_ind<<2)+1U]; | 123 | p_img[(*p_patch_loc>>2)+1U] = p_sig[(*p_patch_ind<<2)+1U]; |
@@ -158,9 +167,10 @@ int gv100_fb_memory_unlock(struct gk20a *g) | |||
158 | mem_unlock_ucode = (u32 *)(mem_unlock_fw->data + | 167 | mem_unlock_ucode = (u32 *)(mem_unlock_fw->data + |
159 | hsbin_hdr->data_offset); | 168 | hsbin_hdr->data_offset); |
160 | 169 | ||
161 | /* Patch Ucode singnatures */ | 170 | /* Patch Ucode signatures */ |
162 | if (gv100_fb_acr_ucode_patch_sig(g, mem_unlock_ucode, | 171 | if (gv100_fb_acr_ucode_patch_sig(g, mem_unlock_ucode, |
163 | (u32 *)(mem_unlock_fw->data + fw_hdr->sig_prod_offset), | 172 | (u32 *)(mem_unlock_fw->data + fw_hdr->sig_prod_offset), |
173 | (u32 *)(mem_unlock_fw->data + fw_hdr->sig_dbg_offset), | ||
164 | (u32 *)(mem_unlock_fw->data + fw_hdr->patch_loc), | 174 | (u32 *)(mem_unlock_fw->data + fw_hdr->patch_loc), |
165 | (u32 *)(mem_unlock_fw->data + fw_hdr->patch_sig)) < 0) { | 175 | (u32 *)(mem_unlock_fw->data + fw_hdr->patch_sig)) < 0) { |
166 | nvgpu_err(g, "mem unlock patch signatures fail"); | 176 | nvgpu_err(g, "mem unlock patch signatures fail"); |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 93a5bb23..ac1226fc 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -1075,6 +1075,7 @@ struct gpu_ops { | |||
1075 | u32 (*get_irqdest)(struct gk20a *g); | 1075 | u32 (*get_irqdest)(struct gk20a *g); |
1076 | int (*alloc_super_surface)(struct gk20a *g, | 1076 | int (*alloc_super_surface)(struct gk20a *g, |
1077 | struct nvgpu_mem *super_surface, u32 size); | 1077 | struct nvgpu_mem *super_surface, u32 size); |
1078 | bool (*is_debug_mode_enabled)(struct gk20a *g); | ||
1078 | } pmu; | 1079 | } pmu; |
1079 | struct { | 1080 | struct { |
1080 | int (*init_debugfs)(struct gk20a *g); | 1081 | int (*init_debugfs)(struct gk20a *g); |
diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c index 9725ebe7..24112dd3 100644 --- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c | |||
@@ -1141,12 +1141,6 @@ err_release_acr_fw: | |||
1141 | return err; | 1141 | return err; |
1142 | } | 1142 | } |
1143 | 1143 | ||
1144 | static u8 pmu_is_debug_mode_en(struct gk20a *g) | ||
1145 | { | ||
1146 | u32 ctl_stat = gk20a_readl(g, pwr_pmu_scpctl_stat_r()); | ||
1147 | return pwr_pmu_scpctl_stat_debug_mode_v(ctl_stat); | ||
1148 | } | ||
1149 | |||
1150 | /* | 1144 | /* |
1151 | * @brief Patch signatures into ucode image | 1145 | * @brief Patch signatures into ucode image |
1152 | */ | 1146 | */ |
@@ -1160,7 +1154,7 @@ int acr_ucode_patch_sig(struct gk20a *g, | |||
1160 | unsigned int i, *p_sig; | 1154 | unsigned int i, *p_sig; |
1161 | nvgpu_pmu_dbg(g, " "); | 1155 | nvgpu_pmu_dbg(g, " "); |
1162 | 1156 | ||
1163 | if (!pmu_is_debug_mode_en(g)) { | 1157 | if (!g->ops.pmu.is_debug_mode_enabled(g)) { |
1164 | p_sig = p_prod_sig; | 1158 | p_sig = p_prod_sig; |
1165 | nvgpu_pmu_dbg(g, "PRODUCTION MODE\n"); | 1159 | nvgpu_pmu_dbg(g, "PRODUCTION MODE\n"); |
1166 | } else { | 1160 | } else { |
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index 835d18d4..a2b23cca 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c | |||
@@ -550,6 +550,7 @@ static const struct gpu_ops gm20b_ops = { | |||
550 | .reset_engine = gk20a_pmu_engine_reset, | 550 | .reset_engine = gk20a_pmu_engine_reset, |
551 | .is_engine_in_reset = gk20a_pmu_is_engine_in_reset, | 551 | .is_engine_in_reset = gk20a_pmu_is_engine_in_reset, |
552 | .get_irqdest = gk20a_pmu_get_irqdest, | 552 | .get_irqdest = gk20a_pmu_get_irqdest, |
553 | .is_debug_mode_enabled = gm20b_pmu_is_debug_mode_en, | ||
553 | }, | 554 | }, |
554 | .clk = { | 555 | .clk = { |
555 | .init_clk_support = gm20b_init_clk_support, | 556 | .init_clk_support = gm20b_init_clk_support, |
diff --git a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c index 38970f73..a46f8807 100644 --- a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c | |||
@@ -271,3 +271,9 @@ void pmu_dump_security_fuses_gm20b(struct gk20a *g) | |||
271 | nvgpu_tegra_fuse_read_gcplex_config_fuse(g, &val); | 271 | nvgpu_tegra_fuse_read_gcplex_config_fuse(g, &val); |
272 | nvgpu_err(g, "FUSE_GCPLEX_CONFIG_FUSE_0: 0x%x", val); | 272 | nvgpu_err(g, "FUSE_GCPLEX_CONFIG_FUSE_0: 0x%x", val); |
273 | } | 273 | } |
274 | |||
275 | bool gm20b_pmu_is_debug_mode_en(struct gk20a *g) | ||
276 | { | ||
277 | u32 ctl_stat = gk20a_readl(g, pwr_pmu_scpctl_stat_r()); | ||
278 | return pwr_pmu_scpctl_stat_debug_mode_v(ctl_stat) != 0U; | ||
279 | } | ||
diff --git a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.h b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.h index ec50fb06..1923c047 100644 --- a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.h | |||
@@ -33,5 +33,6 @@ void pmu_dump_security_fuses_gm20b(struct gk20a *g); | |||
33 | void gm20b_pmu_load_lsf(struct gk20a *g, u32 falcon_id, u32 flags); | 33 | void gm20b_pmu_load_lsf(struct gk20a *g, u32 falcon_id, u32 flags); |
34 | int gm20b_pmu_init_acr(struct gk20a *g); | 34 | int gm20b_pmu_init_acr(struct gk20a *g); |
35 | void gm20b_write_dmatrfbase(struct gk20a *g, u32 addr); | 35 | void gm20b_write_dmatrfbase(struct gk20a *g, u32 addr); |
36 | bool gm20b_pmu_is_debug_mode_en(struct gk20a *g); | ||
36 | 37 | ||
37 | #endif /*__PMU_GM20B_H_*/ | 38 | #endif /*__PMU_GM20B_H_*/ |
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index 54648f56..78a3ea63 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c | |||
@@ -668,6 +668,7 @@ static const struct gpu_ops gp106_ops = { | |||
668 | .pmu_lpwr_enable_pg = nvgpu_lpwr_enable_pg, | 668 | .pmu_lpwr_enable_pg = nvgpu_lpwr_enable_pg, |
669 | .get_irqdest = gk20a_pmu_get_irqdest, | 669 | .get_irqdest = gk20a_pmu_get_irqdest, |
670 | .alloc_super_surface = NULL, | 670 | .alloc_super_surface = NULL, |
671 | .is_debug_mode_enabled = gm20b_pmu_is_debug_mode_en, | ||
671 | }, | 672 | }, |
672 | .clk = { | 673 | .clk = { |
673 | .init_clk_support = gp106_init_clk_support, | 674 | .init_clk_support = gp106_init_clk_support, |
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 8412092a..f4ae1314 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c | |||
@@ -610,6 +610,7 @@ static const struct gpu_ops gp10b_ops = { | |||
610 | .reset_engine = gk20a_pmu_engine_reset, | 610 | .reset_engine = gk20a_pmu_engine_reset, |
611 | .is_engine_in_reset = gk20a_pmu_is_engine_in_reset, | 611 | .is_engine_in_reset = gk20a_pmu_is_engine_in_reset, |
612 | .get_irqdest = gk20a_pmu_get_irqdest, | 612 | .get_irqdest = gk20a_pmu_get_irqdest, |
613 | .is_debug_mode_enabled = gm20b_pmu_is_debug_mode_en, | ||
613 | }, | 614 | }, |
614 | .regops = { | 615 | .regops = { |
615 | .exec_regops = exec_regops_gk20a, | 616 | .exec_regops = exec_regops_gk20a, |
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 789fe8d9..339d7813 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c | |||
@@ -764,6 +764,7 @@ static const struct gpu_ops gv100_ops = { | |||
764 | .pmu_get_queue_tail = pwr_pmu_queue_tail_r, | 764 | .pmu_get_queue_tail = pwr_pmu_queue_tail_r, |
765 | .get_irqdest = gk20a_pmu_get_irqdest, | 765 | .get_irqdest = gk20a_pmu_get_irqdest, |
766 | .alloc_super_surface = nvgpu_pmu_super_surface_alloc, | 766 | .alloc_super_surface = nvgpu_pmu_super_surface_alloc, |
767 | .is_debug_mode_enabled = gm20b_pmu_is_debug_mode_en, | ||
767 | }, | 768 | }, |
768 | .clk = { | 769 | .clk = { |
769 | .init_clk_support = gp106_init_clk_support, | 770 | .init_clk_support = gp106_init_clk_support, |
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index a295f774..ff9fc8c6 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c | |||
@@ -706,6 +706,7 @@ static const struct gpu_ops gv11b_ops = { | |||
706 | .is_pmu_supported = gv11b_is_pmu_supported, | 706 | .is_pmu_supported = gv11b_is_pmu_supported, |
707 | .get_irqdest = gv11b_pmu_get_irqdest, | 707 | .get_irqdest = gv11b_pmu_get_irqdest, |
708 | .handle_ext_irq = gv11b_pmu_handle_ext_irq, | 708 | .handle_ext_irq = gv11b_pmu_handle_ext_irq, |
709 | .is_debug_mode_enabled = gm20b_pmu_is_debug_mode_en, | ||
709 | }, | 710 | }, |
710 | .regops = { | 711 | .regops = { |
711 | .exec_regops = exec_regops_gk20a, | 712 | .exec_regops = exec_regops_gk20a, |