diff options
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | 35 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | 34 |
2 files changed, 35 insertions, 34 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c index 77c5da0a..2236e76c 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | |||
@@ -31,6 +31,10 @@ | |||
31 | #include "hw_pwr_gk20a.h" | 31 | #include "hw_pwr_gk20a.h" |
32 | #include "hw_top_gk20a.h" | 32 | #include "hw_top_gk20a.h" |
33 | 33 | ||
34 | #ifdef CONFIG_ARCH_TEGRA_18x_SOC | ||
35 | #include "nvgpu_gpuid_t18x.h" | ||
36 | #endif | ||
37 | |||
34 | #define GK20A_PMU_UCODE_IMAGE "gpmu_ucode.bin" | 38 | #define GK20A_PMU_UCODE_IMAGE "gpmu_ucode.bin" |
35 | 39 | ||
36 | #define gk20a_dbg_pmu(fmt, arg...) \ | 40 | #define gk20a_dbg_pmu(fmt, arg...) \ |
@@ -2810,6 +2814,30 @@ static int pmu_init_powergating(struct gk20a *g) | |||
2810 | return 0; | 2814 | return 0; |
2811 | } | 2815 | } |
2812 | 2816 | ||
2817 | static u8 get_perfmon_id(struct pmu_gk20a *pmu) | ||
2818 | { | ||
2819 | struct gk20a *g = gk20a_from_pmu(pmu); | ||
2820 | u32 ver = g->gpu_characteristics.arch + g->gpu_characteristics.impl; | ||
2821 | u8 unit_id; | ||
2822 | |||
2823 | switch (ver) { | ||
2824 | case GK20A_GPUID_GK20A: | ||
2825 | case GK20A_GPUID_GM20B: | ||
2826 | unit_id = PMU_UNIT_PERFMON; | ||
2827 | break; | ||
2828 | #if defined(CONFIG_ARCH_TEGRA_18x_SOC) | ||
2829 | case TEGRA_18x_GPUID: | ||
2830 | unit_id = PMU_UNIT_PERFMON_T18X; | ||
2831 | break; | ||
2832 | #endif | ||
2833 | default: | ||
2834 | gk20a_err(&g->dev->dev, "no support for %x", ver); | ||
2835 | BUG(); | ||
2836 | } | ||
2837 | |||
2838 | return unit_id; | ||
2839 | } | ||
2840 | |||
2813 | static int pmu_init_perfmon(struct pmu_gk20a *pmu) | 2841 | static int pmu_init_perfmon(struct pmu_gk20a *pmu) |
2814 | { | 2842 | { |
2815 | struct gk20a *g = gk20a_from_pmu(pmu); | 2843 | struct gk20a *g = gk20a_from_pmu(pmu); |
@@ -2878,7 +2906,7 @@ static int pmu_init_perfmon(struct pmu_gk20a *pmu) | |||
2878 | 2906 | ||
2879 | /* init PERFMON */ | 2907 | /* init PERFMON */ |
2880 | memset(&cmd, 0, sizeof(struct pmu_cmd)); | 2908 | memset(&cmd, 0, sizeof(struct pmu_cmd)); |
2881 | cmd.hdr.unit_id = PMU_UNIT_PERFMON; | 2909 | cmd.hdr.unit_id = get_perfmon_id(pmu); |
2882 | cmd.hdr.size = PMU_CMD_HDR_SIZE + pv->get_pmu_perfmon_cmd_init_size(); | 2910 | cmd.hdr.size = PMU_CMD_HDR_SIZE + pv->get_pmu_perfmon_cmd_init_size(); |
2883 | cmd.cmd.perfmon.cmd_type = PMU_PERFMON_CMD_ID_INIT; | 2911 | cmd.cmd.perfmon.cmd_type = PMU_PERFMON_CMD_ID_INIT; |
2884 | /* buffer to save counter values for pmu perfmon */ | 2912 | /* buffer to save counter values for pmu perfmon */ |
@@ -3185,7 +3213,7 @@ static int pmu_perfmon_start_sampling(struct pmu_gk20a *pmu) | |||
3185 | 3213 | ||
3186 | /* PERFMON Start */ | 3214 | /* PERFMON Start */ |
3187 | memset(&cmd, 0, sizeof(struct pmu_cmd)); | 3215 | memset(&cmd, 0, sizeof(struct pmu_cmd)); |
3188 | cmd.hdr.unit_id = PMU_UNIT_PERFMON; | 3216 | cmd.hdr.unit_id = get_perfmon_id(pmu); |
3189 | cmd.hdr.size = PMU_CMD_HDR_SIZE + pv->get_pmu_perfmon_cmd_start_size(); | 3217 | cmd.hdr.size = PMU_CMD_HDR_SIZE + pv->get_pmu_perfmon_cmd_start_size(); |
3190 | pv->perfmon_start_set_cmd_type(&cmd.cmd.perfmon, | 3218 | pv->perfmon_start_set_cmd_type(&cmd.cmd.perfmon, |
3191 | PMU_PERFMON_CMD_ID_START); | 3219 | PMU_PERFMON_CMD_ID_START); |
@@ -3227,7 +3255,7 @@ static int pmu_perfmon_stop_sampling(struct pmu_gk20a *pmu) | |||
3227 | 3255 | ||
3228 | /* PERFMON Stop */ | 3256 | /* PERFMON Stop */ |
3229 | memset(&cmd, 0, sizeof(struct pmu_cmd)); | 3257 | memset(&cmd, 0, sizeof(struct pmu_cmd)); |
3230 | cmd.hdr.unit_id = PMU_UNIT_PERFMON; | 3258 | cmd.hdr.unit_id = get_perfmon_id(pmu); |
3231 | cmd.hdr.size = PMU_CMD_HDR_SIZE + sizeof(struct pmu_perfmon_cmd_stop); | 3259 | cmd.hdr.size = PMU_CMD_HDR_SIZE + sizeof(struct pmu_perfmon_cmd_stop); |
3232 | cmd.cmd.perfmon.stop.cmd_type = PMU_PERFMON_CMD_ID_STOP; | 3260 | cmd.cmd.perfmon.stop.cmd_type = PMU_PERFMON_CMD_ID_STOP; |
3233 | 3261 | ||
@@ -3278,6 +3306,7 @@ static int pmu_handle_event(struct pmu_gk20a *pmu, struct pmu_msg *msg) | |||
3278 | 3306 | ||
3279 | switch (msg->hdr.unit_id) { | 3307 | switch (msg->hdr.unit_id) { |
3280 | case PMU_UNIT_PERFMON: | 3308 | case PMU_UNIT_PERFMON: |
3309 | case PMU_UNIT_PERFMON_T18X: | ||
3281 | err = pmu_handle_perfmon_event(pmu, &msg->msg.perfmon); | 3310 | err = pmu_handle_perfmon_event(pmu, &msg->msg.perfmon); |
3282 | break; | 3311 | break; |
3283 | default: | 3312 | default: |
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h index 6676c2e5..3dd16ec4 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | |||
@@ -428,40 +428,12 @@ struct pmu_ucode_desc { | |||
428 | }; | 428 | }; |
429 | 429 | ||
430 | #define PMU_UNIT_REWIND (0x00) | 430 | #define PMU_UNIT_REWIND (0x00) |
431 | #define PMU_UNIT_I2C (0x01) | 431 | #define PMU_UNIT_PG (0x03) |
432 | #define PMU_UNIT_SEQ (0x02) | ||
433 | #define PMU_UNIT_PG (0x03) | ||
434 | #define PMU_UNIT_AVAILABLE1 (0x04) | ||
435 | #define PMU_UNIT_AVAILABLE2 (0x05) | ||
436 | #define PMU_UNIT_MEM (0x06) | ||
437 | #define PMU_UNIT_INIT (0x07) | 432 | #define PMU_UNIT_INIT (0x07) |
438 | #define PMU_UNIT_FBBA (0x08) | ||
439 | #define PMU_UNIT_DIDLE (0x09) | ||
440 | #define PMU_UNIT_ACR (0x0A) | 433 | #define PMU_UNIT_ACR (0x0A) |
441 | #define PMU_UNIT_AVAILABLE4 (0x0B) | 434 | #define PMU_UNIT_PERFMON_T18X (0x11) |
442 | #define PMU_UNIT_HDCP_MAIN (0x0C) | ||
443 | #define PMU_UNIT_HDCP_V (0x0D) | ||
444 | #define PMU_UNIT_HDCP_SRM (0x0E) | ||
445 | #define PMU_UNIT_NVDPS (0x0F) | ||
446 | #define PMU_UNIT_DEINIT (0x10) | ||
447 | #define PMU_UNIT_AVAILABLE5 (0x11) | ||
448 | #define PMU_UNIT_PERFMON (0x12) | 435 | #define PMU_UNIT_PERFMON (0x12) |
449 | #define PMU_UNIT_FAN (0x13) | 436 | #define PMU_UNIT_RC (0x1F) |
450 | #define PMU_UNIT_PBI (0x14) | ||
451 | #define PMU_UNIT_ISOBLIT (0x15) | ||
452 | #define PMU_UNIT_DETACH (0x16) | ||
453 | #define PMU_UNIT_DISP (0x17) | ||
454 | #define PMU_UNIT_HDCP (0x18) | ||
455 | #define PMU_UNIT_REGCACHE (0x19) | ||
456 | #define PMU_UNIT_SYSMON (0x1A) | ||
457 | #define PMU_UNIT_THERM (0x1B) | ||
458 | #define PMU_UNIT_PMGR (0x1C) | ||
459 | #define PMU_UNIT_PERF (0x1D) | ||
460 | #define PMU_UNIT_PCM (0x1E) | ||
461 | #define PMU_UNIT_RC (0x1F) | ||
462 | #define PMU_UNIT_NULL (0x20) | ||
463 | #define PMU_UNIT_LOGGER (0x21) | ||
464 | #define PMU_UNIT_SMBPBI (0x22) | ||
465 | #define PMU_UNIT_END (0x23) | 437 | #define PMU_UNIT_END (0x23) |
466 | 438 | ||
467 | #define PMU_UNIT_TEST_START (0xFE) | 439 | #define PMU_UNIT_TEST_START (0xFE) |