2 files changed, 477 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
index d12c5987..9d9dbb4b 100644
--- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
@@ -192,6 +192,38 @@ static void set_pmu_cmdline_args_falctracedmaidx_v4(
         pmu->args_v4.falc_trace_dma_idx = idx;
 }
 
+static u32 pmu_cmdline_size_v5(struct pmu_gk20a *pmu)
+{
+        return sizeof(struct pmu_cmdline_args_v5);
+}
+
+static void set_pmu_cmdline_args_cpufreq_v5(struct pmu_gk20a *pmu, u32 freq)
+{
+        pmu->args_v5.cpu_freq_hz = 204000000;
+}
+static void set_pmu_cmdline_args_secure_mode_v5(struct pmu_gk20a *pmu, u32 val)
+{
+        pmu->args_v5.secure_mode = val;
+}
+
+static void set_pmu_cmdline_args_falctracesize_v5(
+                        struct pmu_gk20a *pmu, u32 size)
+{
+        pmu->args_v5.trace_buf.params |= (size & 0x0FFF);
+}
+
+static void set_pmu_cmdline_args_falctracedmabase_v5(struct pmu_gk20a *pmu)
+{
+        pmu->args_v5.trace_buf.address.lo = ((u32)pmu->trace_buf.gpu_va)/0x100;
+        pmu->args_v5.trace_buf.address.hi = 0;
+}
+
+static void set_pmu_cmdline_args_falctracedmaidx_v5(
+                        struct pmu_gk20a *pmu, u32 idx)
+{
+        pmu->args_v5.trace_buf.params |= (idx << 24);
+}
+
 static u32 pmu_cmdline_size_v3(struct pmu_gk20a *pmu)
 {
         return sizeof(struct pmu_cmdline_args_v3);
@@ -315,6 +347,10 @@ static void *get_pmu_cmdline_args_ptr_v2(struct pmu_gk20a *pmu)
         return (void *)(&pmu->args_v2);
 }
 
+static void *get_pmu_cmdline_args_ptr_v5(struct pmu_gk20a *pmu)
+{
+        return (void *)(&pmu->args_v5);
+}
 static void *get_pmu_cmdline_args_ptr_v1(struct pmu_gk20a *pmu)
 {
         return (void *)(&pmu->args_v1);
@@ -325,6 +361,11 @@ static void *get_pmu_cmdline_args_ptr_v0(struct pmu_gk20a *pmu)
         return (void *)(&pmu->args_v0);
 }
 
+static u32 get_pmu_allocation_size_v3(struct pmu_gk20a *pmu)
+{
+        return sizeof(struct pmu_allocation_v3);
+}
+
 static u32 get_pmu_allocation_size_v2(struct pmu_gk20a *pmu)
 {
         return sizeof(struct pmu_allocation_v2);
@@ -340,6 +381,14 @@ static u32 get_pmu_allocation_size_v0(struct pmu_gk20a *pmu)
         return sizeof(struct pmu_allocation_v0);
 }
 
+static void set_pmu_allocation_ptr_v3(struct pmu_gk20a *pmu,
+        void **pmu_alloc_ptr, void *assign_ptr)
+{
+        struct pmu_allocation_v3 **pmu_a_ptr =
+                (struct pmu_allocation_v3 **)pmu_alloc_ptr;
+        *pmu_a_ptr = (struct pmu_allocation_v3 *)assign_ptr;
+}
+
 static void set_pmu_allocation_ptr_v2(struct pmu_gk20a *pmu,
         void **pmu_alloc_ptr, void *assign_ptr)
 {
@@ -364,6 +413,14 @@ static void set_pmu_allocation_ptr_v0(struct pmu_gk20a *pmu,
         *pmu_a_ptr = (struct pmu_allocation_v0 *)assign_ptr;
 }
 
+static void pmu_allocation_set_dmem_size_v3(struct pmu_gk20a *pmu,
+        void *pmu_alloc_ptr, u16 size)
+{
+        struct pmu_allocation_v3 *pmu_a_ptr =
+                (struct pmu_allocation_v3 *)pmu_alloc_ptr;
+        pmu_a_ptr->alloc.dmem.size = size;
+}
+
 static void pmu_allocation_set_dmem_size_v2(struct pmu_gk20a *pmu,
         void *pmu_alloc_ptr, u16 size)
 {
@@ -388,6 +445,14 @@ static void pmu_allocation_set_dmem_size_v0(struct pmu_gk20a *pmu,
         pmu_a_ptr->alloc.dmem.size = size;
 }
 
+static u16 pmu_allocation_get_dmem_size_v3(struct pmu_gk20a *pmu,
+        void *pmu_alloc_ptr)
+{
+        struct pmu_allocation_v3 *pmu_a_ptr =
+                (struct pmu_allocation_v3 *)pmu_alloc_ptr;
+        return pmu_a_ptr->alloc.dmem.size;
+}
+
 static u16 pmu_allocation_get_dmem_size_v2(struct pmu_gk20a *pmu,
         void *pmu_alloc_ptr)
 {
@@ -412,6 +477,14 @@ static u16 pmu_allocation_get_dmem_size_v0(struct pmu_gk20a *pmu,
         return pmu_a_ptr->alloc.dmem.size;
 }
 
+static u32 pmu_allocation_get_dmem_offset_v3(struct pmu_gk20a *pmu,
+        void *pmu_alloc_ptr)
+{
+        struct pmu_allocation_v3 *pmu_a_ptr =
+                (struct pmu_allocation_v3 *)pmu_alloc_ptr;
+        return pmu_a_ptr->alloc.dmem.offset;
+}
+
 static u32 pmu_allocation_get_dmem_offset_v2(struct pmu_gk20a *pmu,
         void *pmu_alloc_ptr)
 {
@@ -436,6 +509,14 @@ static u32 pmu_allocation_get_dmem_offset_v0(struct pmu_gk20a *pmu,
         return pmu_a_ptr->alloc.dmem.offset;
 }
 
+static u32 *pmu_allocation_get_dmem_offset_addr_v3(struct pmu_gk20a *pmu,
+        void *pmu_alloc_ptr)
+{
+        struct pmu_allocation_v3 *pmu_a_ptr =
+                (struct pmu_allocation_v3 *)pmu_alloc_ptr;
+        return &pmu_a_ptr->alloc.dmem.offset;
+}
+
 static u32 *pmu_allocation_get_dmem_offset_addr_v2(struct pmu_gk20a *pmu,
         void *pmu_alloc_ptr)
 {
@@ -460,6 +541,14 @@ static u32 *pmu_allocation_get_dmem_offset_addr_v0(struct pmu_gk20a *pmu,
         return &pmu_a_ptr->alloc.dmem.offset;
 }
 
+static void pmu_allocation_set_dmem_offset_v3(struct pmu_gk20a *pmu,
+        void *pmu_alloc_ptr, u32 offset)
+{
+        struct pmu_allocation_v3 *pmu_a_ptr =
+                (struct pmu_allocation_v3 *)pmu_alloc_ptr;
+        pmu_a_ptr->alloc.dmem.offset = offset;
+}
+
 static void pmu_allocation_set_dmem_offset_v2(struct pmu_gk20a *pmu,
         void *pmu_alloc_ptr, u32 offset)
 {
@@ -484,6 +573,25 @@ static void pmu_allocation_set_dmem_offset_v0(struct pmu_gk20a *pmu,
         pmu_a_ptr->alloc.dmem.offset = offset;
 }
 
+static void *get_pmu_msg_pmu_init_msg_ptr_v2(struct pmu_init_msg *init)
+{
+        return (void *)(&(init->pmu_init_v2));
+}
+
+static u16 get_pmu_init_msg_pmu_sw_mg_off_v2(union pmu_init_msg_pmu *init_msg)
+{
+        struct pmu_init_msg_pmu_v2 *init =
+                (struct pmu_init_msg_pmu_v2 *)(&init_msg->v1);
+        return init->sw_managed_area_offset;
+}
+
+static u16 get_pmu_init_msg_pmu_sw_mg_size_v2(union pmu_init_msg_pmu *init_msg)
+{
+        struct pmu_init_msg_pmu_v2 *init =
+                (struct pmu_init_msg_pmu_v2 *)(&init_msg->v1);
+        return init->sw_managed_area_size;
+}
+
 static void *get_pmu_msg_pmu_init_msg_ptr_v1(struct pmu_init_msg *init)
 {
         return (void *)(&(init->pmu_init_v1));
@@ -522,6 +630,11 @@ static u16 get_pmu_init_msg_pmu_sw_mg_size_v0(union pmu_init_msg_pmu *init_msg)
         return init->sw_managed_area_size;
 }
 
+static u32 get_pmu_perfmon_cmd_start_size_v3(void)
+{
+        return sizeof(struct pmu_perfmon_cmd_start_v3);
+}
+
 static u32 get_pmu_perfmon_cmd_start_size_v2(void)
 {
         return sizeof(struct pmu_perfmon_cmd_start_v2);
@@ -537,6 +650,20 @@ static u32 get_pmu_perfmon_cmd_start_size_v0(void)
         return sizeof(struct pmu_perfmon_cmd_start_v0);
 }
 
+static int get_perfmon_cmd_start_offsetofvar_v3(
+        enum pmu_perfmon_cmd_start_fields field)
+{
+        switch (field) {
+        case COUNTER_ALLOC:
+                return offsetof(struct pmu_perfmon_cmd_start_v3,
+                counter_alloc);
+        default:
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
 static int get_perfmon_cmd_start_offsetofvar_v2(
         enum pmu_perfmon_cmd_start_fields field)
 {
@@ -579,6 +706,11 @@ static int get_perfmon_cmd_start_offsetofvar_v0(
         return 0;
 }
 
+static u32 get_pmu_perfmon_cmd_init_size_v3(void)
+{
+        return sizeof(struct pmu_perfmon_cmd_init_v3);
+}
+
 static u32 get_pmu_perfmon_cmd_init_size_v2(void)
 {
         return sizeof(struct pmu_perfmon_cmd_init_v2);
@@ -594,6 +726,19 @@ static u32 get_pmu_perfmon_cmd_init_size_v0(void)
         return sizeof(struct pmu_perfmon_cmd_init_v0);
 }
 
+static int get_perfmon_cmd_init_offsetofvar_v3(
+        enum pmu_perfmon_cmd_start_fields field)
+{
+        switch (field) {
+        case COUNTER_ALLOC:
+                return offsetof(struct pmu_perfmon_cmd_init_v3,
+                counter_alloc);
+        default:
+                return -EINVAL;
+        }
+        return 0;
+}
+
 static int get_perfmon_cmd_init_offsetofvar_v2(
         enum pmu_perfmon_cmd_start_fields field)
 {
@@ -636,6 +781,13 @@ static int get_perfmon_cmd_init_offsetofvar_v0(
         return 0;
 }
 
+static void perfmon_start_set_cmd_type_v3(struct pmu_perfmon_cmd *pc, u8 value)
+{
+        struct pmu_perfmon_cmd_start_v3 *start = &pc->start_v3;
+
+        start->cmd_type = value;
+}
+
 static void perfmon_start_set_cmd_type_v2(struct pmu_perfmon_cmd *pc, u8 value)
 {
         struct pmu_perfmon_cmd_start_v2 *start = &pc->start_v2;
@@ -654,6 +806,13 @@ static void perfmon_start_set_cmd_type_v0(struct pmu_perfmon_cmd *pc, u8 value)
         start->cmd_type = value;
 }
 
+static void perfmon_start_set_group_id_v3(struct pmu_perfmon_cmd *pc, u8 value)
+{
+        struct pmu_perfmon_cmd_start_v3 *start = &pc->start_v3;
+
+        start->group_id = value;
+}
+
 static void perfmon_start_set_group_id_v2(struct pmu_perfmon_cmd *pc, u8 value)
 {
         struct pmu_perfmon_cmd_start_v2 *start = &pc->start_v2;
@@ -672,6 +831,13 @@ static void perfmon_start_set_group_id_v0(struct pmu_perfmon_cmd *pc, u8 value)
         start->group_id = value;
 }
 
+static void perfmon_start_set_state_id_v3(struct pmu_perfmon_cmd *pc, u8 value)
+{
+        struct pmu_perfmon_cmd_start_v3 *start = &pc->start_v3;
+
+        start->state_id = value;
+}
+
 static void perfmon_start_set_state_id_v2(struct pmu_perfmon_cmd *pc, u8 value)
 {
         struct pmu_perfmon_cmd_start_v2 *start = &pc->start_v2;
@@ -690,6 +856,13 @@ static void perfmon_start_set_state_id_v0(struct pmu_perfmon_cmd *pc, u8 value)
         start->state_id = value;
 }
 
+static void perfmon_start_set_flags_v3(struct pmu_perfmon_cmd *pc, u8 value)
+{
+        struct pmu_perfmon_cmd_start_v3 *start = &pc->start_v3;
+
+        start->flags = value;
+}
+
 static void perfmon_start_set_flags_v2(struct pmu_perfmon_cmd *pc, u8 value)
 {
         struct pmu_perfmon_cmd_start_v2 *start = &pc->start_v2;
@@ -708,6 +881,13 @@ static void perfmon_start_set_flags_v0(struct pmu_perfmon_cmd *pc, u8 value)
         start->flags = value;
 }
 
+static u8 perfmon_start_get_flags_v3(struct pmu_perfmon_cmd *pc)
+{
+        struct pmu_perfmon_cmd_start_v3 *start = &pc->start_v3;
+
+        return start->flags;
+}
+
 static u8 perfmon_start_get_flags_v2(struct pmu_perfmon_cmd *pc)
 {
         struct pmu_perfmon_cmd_start_v2 *start = &pc->start_v2;
@@ -726,6 +906,14 @@ static u8 perfmon_start_get_flags_v0(struct pmu_perfmon_cmd *pc)
         return start->flags;
 }
 
+static void perfmon_cmd_init_set_sample_buffer_v3(struct pmu_perfmon_cmd *pc,
+        u16 value)
+{
+        struct pmu_perfmon_cmd_init_v3 *init = &pc->init_v3;
+
+        init->sample_buffer = value;
+}
+
 static void perfmon_cmd_init_set_sample_buffer_v2(struct pmu_perfmon_cmd *pc,
         u16 value)
 {
@@ -748,6 +936,14 @@ static void perfmon_cmd_init_set_sample_buffer_v0(struct pmu_perfmon_cmd *pc,
         init->sample_buffer = value;
 }
 
+static void perfmon_cmd_init_set_dec_cnt_v3(struct pmu_perfmon_cmd *pc,
+        u8 value)
+{
+        struct pmu_perfmon_cmd_init_v3 *init = &pc->init_v3;
+
+        init->to_decrease_count = value;
+}
+
 static void perfmon_cmd_init_set_dec_cnt_v2(struct pmu_perfmon_cmd *pc,
         u8 value)
 {
@@ -769,6 +965,14 @@ static void perfmon_cmd_init_set_dec_cnt_v0(struct pmu_perfmon_cmd *pc,
         init->to_decrease_count = value;
 }
 
+static void perfmon_cmd_init_set_base_cnt_id_v3(struct pmu_perfmon_cmd *pc,
+        u8 value)
+{
+        struct pmu_perfmon_cmd_init_v3 *init = &pc->init_v3;
+
+        init->base_counter_id = value;
+}
+
 static void perfmon_cmd_init_set_base_cnt_id_v2(struct pmu_perfmon_cmd *pc,
         u8 value)
 {
@@ -790,6 +994,14 @@ static void perfmon_cmd_init_set_base_cnt_id_v0(struct pmu_perfmon_cmd *pc,
         init->base_counter_id = value;
 }
 
+static void perfmon_cmd_init_set_samp_period_us_v3(struct pmu_perfmon_cmd *pc,
+        u32 value)
+{
+        struct pmu_perfmon_cmd_init_v3 *init = &pc->init_v3;
+
+        init->sample_period_us = value;
+}
+
 static void perfmon_cmd_init_set_samp_period_us_v2(struct pmu_perfmon_cmd *pc,
         u32 value)
 {
@@ -811,6 +1023,14 @@ static void perfmon_cmd_init_set_samp_period_us_v0(struct pmu_perfmon_cmd *pc,
         init->sample_period_us = value;
 }
 
+static void perfmon_cmd_init_set_num_cnt_v3(struct pmu_perfmon_cmd *pc,
+        u8 value)
+{
+        struct pmu_perfmon_cmd_init_v3 *init = &pc->init_v3;
+
+        init->num_counters = value;
+}
+
 static void perfmon_cmd_init_set_num_cnt_v2(struct pmu_perfmon_cmd *pc,
         u8 value)
 {
@@ -832,6 +1052,14 @@ static void perfmon_cmd_init_set_num_cnt_v0(struct pmu_perfmon_cmd *pc,
         init->num_counters = value;
 }
 
+static void perfmon_cmd_init_set_mov_avg_v3(struct pmu_perfmon_cmd *pc,
+        u8 value)
+{
+        struct pmu_perfmon_cmd_init_v3 *init = &pc->init_v3;
+
+        init->samples_in_moving_avg = value;
+}
+
 static void perfmon_cmd_init_set_mov_avg_v2(struct pmu_perfmon_cmd *pc,
         u8 value)
 {
@@ -873,6 +1101,21 @@ static void get_pmu_init_msg_pmu_queue_params_v1(struct pmu_queue *queue,
         queue->size = init->queue_info[id].size;
 }
 
+static void get_pmu_init_msg_pmu_queue_params_v2(struct pmu_queue *queue,
+        u32 id, void *pmu_init_msg)
+{
+        struct pmu_init_msg_pmu_v2 *init =
+                (struct pmu_init_msg_pmu_v2 *)pmu_init_msg;
+        queue->index    = init->queue_info[id].index;
+        queue->offset   = init->queue_info[id].offset;
+        queue->size = init->queue_info[id].size;
+}
+
+static void *get_pmu_sequence_in_alloc_ptr_v3(struct pmu_sequence *seq)
+{
+        return (void *)(&seq->in_v3);
+}
+
 static void *get_pmu_sequence_in_alloc_ptr_v1(struct pmu_sequence *seq)
 {
         return (void *)(&seq->in_v1);
@@ -883,6 +1126,11 @@ static void *get_pmu_sequence_in_alloc_ptr_v0(struct pmu_sequence *seq)
         return (void *)(&seq->in_v0);
 }
 
+static void *get_pmu_sequence_out_alloc_ptr_v3(struct pmu_sequence *seq)
+{
+        return (void *)(&seq->out_v3);
+}
+
 static void *get_pmu_sequence_out_alloc_ptr_v1(struct pmu_sequence *seq)
 {
         return (void *)(&seq->out_v1);
@@ -903,6 +1151,11 @@ static u8 pg_cmd_eng_buf_load_size_v1(struct pmu_pg_cmd *pg)
         return sizeof(pg->eng_buf_load_v1);
 }
 
+static u8 pg_cmd_eng_buf_load_size_v2(struct pmu_pg_cmd *pg)
+{
+        return sizeof(pg->eng_buf_load_v2);
+}
+
 static void pg_cmd_eng_buf_load_set_cmd_type_v0(struct pmu_pg_cmd *pg,
         u8 value)
 {
@@ -914,6 +1167,13 @@ static void pg_cmd_eng_buf_load_set_cmd_type_v1(struct pmu_pg_cmd *pg,
 {
         pg->eng_buf_load_v1.cmd_type = value;
 }
+
+static void pg_cmd_eng_buf_load_set_cmd_type_v2(struct pmu_pg_cmd *pg,
+        u8 value)
+{
+        pg->eng_buf_load_v2.cmd_type = value;
+}
+
 static void pg_cmd_eng_buf_load_set_engine_id_v0(struct pmu_pg_cmd *pg,
         u8 value)
 {
@@ -924,6 +1184,11 @@ static void pg_cmd_eng_buf_load_set_engine_id_v1(struct pmu_pg_cmd *pg,
 {
         pg->eng_buf_load_v1.engine_id = value;
 }
+static void pg_cmd_eng_buf_load_set_engine_id_v2(struct pmu_pg_cmd *pg,
+        u8 value)
+{
+        pg->eng_buf_load_v2.engine_id = value;
+}
 static void pg_cmd_eng_buf_load_set_buf_idx_v0(struct pmu_pg_cmd *pg,
         u8 value)
 {
@@ -934,6 +1199,11 @@ static void pg_cmd_eng_buf_load_set_buf_idx_v1(struct pmu_pg_cmd *pg,
 {
         pg->eng_buf_load_v1.buf_idx = value;
 }
+static void pg_cmd_eng_buf_load_set_buf_idx_v2(struct pmu_pg_cmd *pg,
+        u8 value)
+{
+        pg->eng_buf_load_v2.buf_idx = value;
+}
 
 static void pg_cmd_eng_buf_load_set_pad_v0(struct pmu_pg_cmd *pg,
         u8 value)
@@ -945,6 +1215,11 @@ static void pg_cmd_eng_buf_load_set_pad_v1(struct pmu_pg_cmd *pg,
 {
         pg->eng_buf_load_v1.pad = value;
 }
+static void pg_cmd_eng_buf_load_set_pad_v2(struct pmu_pg_cmd *pg,
+        u8 value)
+{
+        pg->eng_buf_load_v2.pad = value;
+}
 
 static void pg_cmd_eng_buf_load_set_buf_size_v0(struct pmu_pg_cmd *pg,
         u16 value)
@@ -956,6 +1231,11 @@ static void pg_cmd_eng_buf_load_set_buf_size_v1(struct pmu_pg_cmd *pg,
 {
         pg->eng_buf_load_v1.dma_desc.dma_size = value;
 }
+static void pg_cmd_eng_buf_load_set_buf_size_v2(struct pmu_pg_cmd *pg,
+        u16 value)
+{
+        pg->eng_buf_load_v2.dma_desc.params = value;
+}
 
 static void pg_cmd_eng_buf_load_set_dma_base_v0(struct pmu_pg_cmd *pg,
         u32 value)
@@ -968,6 +1248,12 @@ static void pg_cmd_eng_buf_load_set_dma_base_v1(struct pmu_pg_cmd *pg,
         pg->eng_buf_load_v1.dma_desc.dma_addr.lo |= u64_lo32(value);
         pg->eng_buf_load_v1.dma_desc.dma_addr.hi |= u64_hi32(value);
 }
+static void pg_cmd_eng_buf_load_set_dma_base_v2(struct pmu_pg_cmd *pg,
+        u32 value)
+{
+        pg->eng_buf_load_v2.dma_desc.address.lo = u64_lo32(value);
+        pg->eng_buf_load_v2.dma_desc.address.hi = u64_lo32(value);
+}
 
 static void pg_cmd_eng_buf_load_set_dma_offset_v0(struct pmu_pg_cmd *pg,
         u8 value)
@@ -979,6 +1265,12 @@ static void pg_cmd_eng_buf_load_set_dma_offset_v1(struct pmu_pg_cmd *pg,
 {
         pg->eng_buf_load_v1.dma_desc.dma_addr.lo |= value;
 }
+static void pg_cmd_eng_buf_load_set_dma_offset_v2(struct pmu_pg_cmd *pg,
+        u8 value)
+{
+        pg->eng_buf_load_v2.dma_desc.address.lo |= u64_lo32(value);
+        pg->eng_buf_load_v2.dma_desc.address.hi |= u64_lo32(value);
+}
 
 static void pg_cmd_eng_buf_load_set_dma_idx_v0(struct pmu_pg_cmd *pg,
         u8 value)
@@ -990,6 +1282,11 @@ static void pg_cmd_eng_buf_load_set_dma_idx_v1(struct pmu_pg_cmd *pg,
 {
         pg->eng_buf_load_v1.dma_desc.dma_idx = value;
 }
+static void pg_cmd_eng_buf_load_set_dma_idx_v2(struct pmu_pg_cmd *pg,
+        u8 value)
+{
+        pg->eng_buf_load_v2.dma_desc.params |= (value << 24);
+}
 
 
 int gk20a_init_pmu(struct pmu_gk20a *pmu)
@@ -1107,6 +1404,107 @@ int gk20a_init_pmu(struct pmu_gk20a *pmu)
                 g->ops.pmu_ver.get_pmu_seq_out_a_ptr =
                         get_pmu_sequence_out_alloc_ptr_v1;
                 break;
+        case APP_VERSION_GM206:
+                g->ops.pmu_ver.pg_cmd_eng_buf_load_size =
+                                pg_cmd_eng_buf_load_size_v2;
+                g->ops.pmu_ver.pg_cmd_eng_buf_load_set_cmd_type =
+                                pg_cmd_eng_buf_load_set_cmd_type_v2;
+                g->ops.pmu_ver.pg_cmd_eng_buf_load_set_engine_id =
+                                pg_cmd_eng_buf_load_set_engine_id_v2;
+                g->ops.pmu_ver.pg_cmd_eng_buf_load_set_buf_idx =
+                                pg_cmd_eng_buf_load_set_buf_idx_v2;
+                g->ops.pmu_ver.pg_cmd_eng_buf_load_set_pad =
+                                pg_cmd_eng_buf_load_set_pad_v2;
+                g->ops.pmu_ver.pg_cmd_eng_buf_load_set_buf_size =
+                                pg_cmd_eng_buf_load_set_buf_size_v2;
+                g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_base =
+                                pg_cmd_eng_buf_load_set_dma_base_v2;
+                g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_offset =
+                                pg_cmd_eng_buf_load_set_dma_offset_v2;
+                g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_idx =
+                                pg_cmd_eng_buf_load_set_dma_idx_v2;
+                g->ops.pmu_ver.get_perfmon_cntr_ptr = get_perfmon_cntr_ptr_v2;
+                g->ops.pmu_ver.set_perfmon_cntr_ut = set_perfmon_cntr_ut_v2;
+                g->ops.pmu_ver.set_perfmon_cntr_lt = set_perfmon_cntr_lt_v2;
+                g->ops.pmu_ver.set_perfmon_cntr_valid =
+                        set_perfmon_cntr_valid_v2;
+                g->ops.pmu_ver.set_perfmon_cntr_index =
+                        set_perfmon_cntr_index_v2;
+                g->ops.pmu_ver.set_perfmon_cntr_group_id =
+                        set_perfmon_cntr_group_id_v2;
+                g->ops.pmu_ver.get_perfmon_cntr_sz = pmu_perfmon_cntr_sz_v2;
+                g->ops.pmu_ver.cmd_id_zbc_table_update = 16;
+                g->ops.pmu_ver.get_pmu_cmdline_args_size =
+                        pmu_cmdline_size_v5;
+                g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq =
+                        set_pmu_cmdline_args_cpufreq_v5;
+                g->ops.pmu_ver.set_pmu_cmdline_args_secure_mode =
+                        set_pmu_cmdline_args_secure_mode_v5;
+                g->ops.pmu_ver.set_pmu_cmdline_args_trace_size =
+                        set_pmu_cmdline_args_falctracesize_v5;
+                g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_base =
+                        set_pmu_cmdline_args_falctracedmabase_v5;
+                g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_idx =
+                        set_pmu_cmdline_args_falctracedmaidx_v5;
+                g->ops.pmu_ver.get_pmu_cmdline_args_ptr =
+                        get_pmu_cmdline_args_ptr_v5;
+                g->ops.pmu_ver.get_pmu_allocation_struct_size =
+                        get_pmu_allocation_size_v3;
+                g->ops.pmu_ver.set_pmu_allocation_ptr =
+                        set_pmu_allocation_ptr_v3;
+                g->ops.pmu_ver.pmu_allocation_set_dmem_size =
+                        pmu_allocation_set_dmem_size_v3;
+                g->ops.pmu_ver.pmu_allocation_get_dmem_size =
+                        pmu_allocation_get_dmem_size_v3;
+                g->ops.pmu_ver.pmu_allocation_get_dmem_offset =
+                        pmu_allocation_get_dmem_offset_v3;
+                g->ops.pmu_ver.pmu_allocation_get_dmem_offset_addr =
+                        pmu_allocation_get_dmem_offset_addr_v3;
+                g->ops.pmu_ver.pmu_allocation_set_dmem_offset =
+                        pmu_allocation_set_dmem_offset_v3;
+                g->ops.pmu_ver.get_pmu_init_msg_pmu_queue_params =
+                                get_pmu_init_msg_pmu_queue_params_v2;
+                g->ops.pmu_ver.get_pmu_msg_pmu_init_msg_ptr =
+                                get_pmu_msg_pmu_init_msg_ptr_v2;
+                g->ops.pmu_ver.get_pmu_init_msg_pmu_sw_mg_off =
+                                get_pmu_init_msg_pmu_sw_mg_off_v2;
+                g->ops.pmu_ver.get_pmu_init_msg_pmu_sw_mg_size =
+                                get_pmu_init_msg_pmu_sw_mg_size_v2;
+                g->ops.pmu_ver.get_pmu_perfmon_cmd_start_size =
+                        get_pmu_perfmon_cmd_start_size_v3;
+                g->ops.pmu_ver.get_perfmon_cmd_start_offsetofvar =
+                        get_perfmon_cmd_start_offsetofvar_v3;
+                g->ops.pmu_ver.perfmon_start_set_cmd_type =
+                        perfmon_start_set_cmd_type_v3;
+                g->ops.pmu_ver.perfmon_start_set_group_id =
+                        perfmon_start_set_group_id_v3;
+                g->ops.pmu_ver.perfmon_start_set_state_id =
+                        perfmon_start_set_state_id_v3;
+                g->ops.pmu_ver.perfmon_start_set_flags =
+                        perfmon_start_set_flags_v3;
+                g->ops.pmu_ver.perfmon_start_get_flags =
+                        perfmon_start_get_flags_v3;
+                g->ops.pmu_ver.get_pmu_perfmon_cmd_init_size =
+                        get_pmu_perfmon_cmd_init_size_v3;
+                g->ops.pmu_ver.get_perfmon_cmd_init_offsetofvar =
+                        get_perfmon_cmd_init_offsetofvar_v3;
+                g->ops.pmu_ver.perfmon_cmd_init_set_sample_buffer =
+                        perfmon_cmd_init_set_sample_buffer_v3;
+                g->ops.pmu_ver.perfmon_cmd_init_set_dec_cnt =
+                        perfmon_cmd_init_set_dec_cnt_v3;
+                g->ops.pmu_ver.perfmon_cmd_init_set_base_cnt_id =
+                        perfmon_cmd_init_set_base_cnt_id_v3;
+                g->ops.pmu_ver.perfmon_cmd_init_set_samp_period_us =
+                        perfmon_cmd_init_set_samp_period_us_v3;
+                g->ops.pmu_ver.perfmon_cmd_init_set_num_cnt =
+                        perfmon_cmd_init_set_num_cnt_v3;
+                g->ops.pmu_ver.perfmon_cmd_init_set_mov_avg =
+                        perfmon_cmd_init_set_mov_avg_v3;
+                g->ops.pmu_ver.get_pmu_seq_in_a_ptr =
+                        get_pmu_sequence_in_alloc_ptr_v3;
+                g->ops.pmu_ver.get_pmu_seq_out_a_ptr =
+                        get_pmu_sequence_out_alloc_ptr_v3;
+                break;
         case APP_VERSION_GM20B_5:
         case APP_VERSION_GM20B_4:
                 g->ops.pmu_ver.pg_cmd_eng_buf_load_size =
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
index 7d91b111..8bf642d1 100644
--- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
@@ -51,6 +51,7 @@
 
 #define APP_VERSION_NC_1        20313802
 #define APP_VERSION_NC_0        20360931
+#define APP_VERSION_GM206       20652057
 #define APP_VERSION_GM20B_5 20490253
 #define APP_VERSION_GM20B_4 19008461
 #define APP_VERSION_GM20B_3 18935575
@@ -383,6 +384,16 @@ struct pmu_cmdline_args_v1 {
         struct pmu_mem_v1 gc6_ctx;              /* dmem offset of gc6 context */
 };
 
+struct flcn_u64 {
+        u32 lo;
+        u32 hi;
+};
+
+struct flcn_mem_desc_v0 {
+        struct flcn_u64 address;
+        u32 params;
+};
+
 struct pmu_cmdline_args_v2 {
         u32 cpu_freq_hz;                /* Frequency of the clock driving PMU */
         u32 falc_trace_size;            /* falctrace buffer size (bytes) */
@@ -419,6 +430,16 @@ struct pmu_cmdline_args_v4 {
         u8 pad;
 };
 
+struct pmu_cmdline_args_v5 {
+        u32 cpu_freq_hz;                /* Frequency of the clock driving PMU */
+        struct flcn_mem_desc_v0 trace_buf;
+        u8 secure_mode;
+        u8 raise_priv_sec;
+        struct flcn_mem_desc_v0 gc6_ctx;
+        struct flcn_mem_desc_v0 init_data_dma_info;
+        u32 dummy;
+};
+
 
 #define GK20A_PMU_TRACE_BUFSIZE     0x4000   /* 4K */
 #define GK20A_PMU_DMEM_BLKSIZE2         8
@@ -537,6 +558,13 @@ struct pmu_allocation_v2 {
         } alloc;
 };
 
+struct pmu_allocation_v3 {
+        struct {
+                struct pmu_dmem dmem;
+                struct flcn_mem_desc_v0 fb;
+        } alloc;
+};
+
 enum {
         PMU_INIT_MSG_TYPE_PMU_INIT = 0,
 };
@@ -571,10 +599,27 @@ struct pmu_init_msg_pmu_v1 {
         u16 sw_managed_area_offset;
         u16 sw_managed_area_size;
 };
+struct pmu_init_msg_pmu_v2 {
+        u8 msg_type;
+        u8 pad;
+        u16  os_debug_entry_point;
+
+        struct {
+                u16 size;
+                u16 offset;
+                u8  index;
+                u8  pad;
+        } queue_info[PMU_QUEUE_COUNT];
+
+        u16 sw_managed_area_offset;
+        u16 sw_managed_area_size;
+        u8 dummy[18];
+};
 
 union pmu_init_msg_pmu {
         struct pmu_init_msg_pmu_v0 v0;
         struct pmu_init_msg_pmu_v1 v1;
+        struct pmu_init_msg_pmu_v2 v2;
 };
 
 struct pmu_init_msg {
@@ -582,6 +627,7 @@ struct pmu_init_msg {
                 u8 msg_type;
                 struct pmu_init_msg_pmu_v1 pmu_init_v1;
                 struct pmu_init_msg_pmu_v0 pmu_init_v0;
+                struct pmu_init_msg_pmu_v2 pmu_init_v2;
         };
 };
 
@@ -709,6 +755,14 @@ struct pmu_pg_cmd_eng_buf_load_v1 {
         } dma_desc;
 };
 
+struct pmu_pg_cmd_eng_buf_load_v2 {
+        u8 cmd_type;
+        u8 engine_id;
+        u8 buf_idx;
+        u8 pad;
+        struct flcn_mem_desc_v0 dma_desc;
+};
+
 enum {
         PMU_PG_STAT_CMD_ALLOC_DMEM = 0,
 };
@@ -737,6 +791,7 @@ struct pmu_pg_cmd {
                 struct pmu_pg_cmd_elpg_cmd elpg_cmd;
                 struct pmu_pg_cmd_eng_buf_load_v0 eng_buf_load_v0;
                 struct pmu_pg_cmd_eng_buf_load_v1 eng_buf_load_v1;
+                struct pmu_pg_cmd_eng_buf_load_v2 eng_buf_load_v2;
                 struct pmu_pg_cmd_stat stat;
                 struct pmu_pg_cmd_gr_init_param gr_init_param;
                 /* TBD: other pg commands */
@@ -922,6 +977,14 @@ enum {
         PMU_PERFMON_CMD_ID_INIT  = 2
 };
 
+struct pmu_perfmon_cmd_start_v3 {
+        u8 cmd_type;
+        u8 group_id;
+        u8 state_id;
+        u8 flags;
+        struct pmu_allocation_v3 counter_alloc;
+};
+
 struct pmu_perfmon_cmd_start_v2 {
         u8 cmd_type;
         u8 group_id;
@@ -950,6 +1013,17 @@ struct pmu_perfmon_cmd_stop {
         u8 cmd_type;
 };
 
+struct pmu_perfmon_cmd_init_v3 {
+        u8 cmd_type;
+        u8 to_decrease_count;
+        u8 base_counter_id;
+        u32 sample_period_us;
+        struct pmu_allocation_v3 counter_alloc;
+        u8 num_counters;
+        u8 samples_in_moving_avg;
+        u16 sample_buffer;
+};
+
 struct pmu_perfmon_cmd_init_v2 {
         u8 cmd_type;
         u8 to_decrease_count;
@@ -989,10 +1063,12 @@ struct pmu_perfmon_cmd {
                 struct pmu_perfmon_cmd_start_v0 start_v0;
                 struct pmu_perfmon_cmd_start_v1 start_v1;
                 struct pmu_perfmon_cmd_start_v2 start_v2;
+                struct pmu_perfmon_cmd_start_v3 start_v3;
                 struct pmu_perfmon_cmd_stop stop;
                 struct pmu_perfmon_cmd_init_v0 init_v0;
                 struct pmu_perfmon_cmd_init_v1 init_v1;
                 struct pmu_perfmon_cmd_init_v2 init_v2;
+                struct pmu_perfmon_cmd_init_v3 init_v3;
         };
 };
 
@@ -1201,11 +1277,13 @@ struct pmu_sequence {
                 struct pmu_allocation_v0 in_v0;
                 struct pmu_allocation_v1 in_v1;
                 struct pmu_allocation_v2 in_v2;
+                struct pmu_allocation_v3 in_v3;
         };
         union {
                 struct pmu_allocation_v0 out_v0;
                 struct pmu_allocation_v1 out_v1;
                 struct pmu_allocation_v2 out_v2;
+                struct pmu_allocation_v3 out_v3;
         };
         u8 *out_payload;
         pmu_callback callback;
@@ -1391,6 +1469,7 @@ struct pmu_gk20a {
                 struct pmu_cmdline_args_v2 args_v2;
                 struct pmu_cmdline_args_v3 args_v3;
                 struct pmu_cmdline_args_v4 args_v4;
+                struct pmu_cmdline_args_v5 args_v5;
         };
         unsigned long perfmon_events_cnt;
         bool perfmon_sampling_enabled;